KR100516991B1 - Method of forming a gate in a semiconductor device - Google Patents
Method of forming a gate in a semiconductor device Download PDFInfo
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- KR100516991B1 KR100516991B1 KR10-2002-0031011A KR20020031011A KR100516991B1 KR 100516991 B1 KR100516991 B1 KR 100516991B1 KR 20020031011 A KR20020031011 A KR 20020031011A KR 100516991 B1 KR100516991 B1 KR 100516991B1
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- gate
- film
- oxide film
- forming
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 33
- 239000001301 oxygen Substances 0.000 claims abstract description 31
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 238000009832 plasma treatment Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 239000001257 hydrogen Substances 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910018516 Al—O Inorganic materials 0.000 claims description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 150000002431 hydrogen Chemical class 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 19
- 238000007254 oxidation reaction Methods 0.000 abstract description 19
- 238000010405 reoxidation reaction Methods 0.000 abstract description 9
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000006213 oxygenation reaction Methods 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 게이트 패터닝 공정에서 발생되는 게이트 산화막의 손상을 복구하기 위한 재산화 공정을 자외선이 조사되는 분위기의 산소 플라즈마 처리 공정으로 대체함으로써 폴리실리콘과 금속의 적층 게이트의 계면에서의 이상 산화 및 리프팅을 방지할 수 있고, 금속 단일 게이트에도 적용할 수 있는 반도체 소자의 게이트 형성 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, wherein a polysilicon and a metal are laminated by replacing a reoxidation process for repairing damage of a gate oxide film generated in a gate patterning process with an oxygen plasma treatment process in an ultraviolet-irradiated atmosphere. A method of forming a gate of a semiconductor device, which can prevent abnormal oxidation and lifting at an interface of a gate and can be applied to a metal single gate, is also proposed.
Description
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 특히 게이트 패터닝 공정에서 발생되는 게이트 산화막의 손상을 복구하기 위한 재산화 공정을 산소 플라즈마 처리로 대체함으로써 폴리실리콘과 금속의 적층 게이트의 계면에서의 이상 산화 및 리프팅을 방지할 수 있고, 금속 단일 게이트에도 적용할 수 있는 반도체 소자의 게이트 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and in particular, an abnormality at an interface between a polysilicon and a metal laminated gate by replacing an oxygenation process with a reoxidation process for repairing damage to a gate oxide film generated in a gate patterning process. The present invention relates to a method for forming a gate of a semiconductor device, which can prevent oxidation and lifting and can be applied to a single metal gate.
종래의 폴리실리콘막을 이용하여 게이트 전극을 형성하는 공정에서는 폴리실리콘막을 식각할 때 게이트 산화막에 발생된 마이크로트렌치(microtrench)와 손상(damage)을 복구시키고, 반도체 기판에 잔류하는 전극 물질의 산화 및 게이트 에지(edge)에 있는 게이트 산화막의 두께를 증가시켜 신뢰성을 향상하기 위한 목적으로 재산화 공정을 실시하였다. 이는 게이트 에지에 있는 게이트 산화막의 두께 및 막질에 의해 핫 캐리어 특성, 서브-쓰레쉬홀드 특성(off-leakage, GIDL 등), 펀치-쓰루 특성, 소자의 동작 속도, 신뢰성등에 무척 크게 영향을 미치게 되기 때문에 재산화 공정은 필수적으로 실시하여야 한다.In the process of forming a gate electrode using a conventional polysilicon film, microtrench and damage generated in the gate oxide film when the polysilicon film is etched are recovered, and oxidation and gate of the electrode material remaining on the semiconductor substrate are performed. The reoxidation process was performed for the purpose of increasing the thickness of the gate oxide film at the edge to improve the reliability. This greatly affects hot carrier characteristics, sub-threshold characteristics (off-leakage, GIDL, etc.), punch-through characteristics, device operation speed, and reliability due to the thickness and film quality of the gate oxide film at the gate edge. Therefore, the reprocessing process must be carried out.
최근에는 게이트의 저항을 낮추기 위해 폴리실리콘막과 금속막을 적층하여 게이트를 형성하고 있다. 그러나, 폴리실리콘막과 금속막의 적층 구조는 후속 고온 열공정 또는 산화 공정에서 급격한 부피 팽창, 표면 저항의 증가 등의 문제가 크게 발생하게 된다. 특히, 소정의 산화 분위기에서 금속막이 산화되어 리프팅 등이 발생하는 것이 공정상 가장 큰 문제점으로 부각되고 있는데, 이를 극복하기 위해 개발된 새로운 공정이 선택 산화(selective oxidation) 공정이다. 즉, 수소 리치(H2 rich)의 산화 분위기에서 금속막은 산화시키지 않고, 폴리실리콘막과 반도체 기판만을 산화시키는 공정이다. 그러나, 현재의 선택 산화 공정은 텅스텐막 또는 텅스텐 질화막을 금속 게이트 전극으로 사용할 때만 가능하다는 제약 조건이 있으며, 또한 수소 리치 분위기와 700℃ 이상의 매우 높은 온도에서만 가능하기 때문에 MOSFET 소자의 특성에 악영향을 줄 수 있다.Recently, in order to lower the resistance of the gate, a gate is formed by stacking a polysilicon film and a metal film. However, in the laminated structure of the polysilicon film and the metal film, problems such as rapid volume expansion and increase in surface resistance are greatly generated in a subsequent high temperature thermal process or an oxidation process. In particular, the lifting of the metal film in a predetermined oxidizing atmosphere and the lifting occurs as the biggest problem in the process, a new process developed to overcome this is a selective oxidation (selective oxidation) process. That is, a process in which, without oxidizing the metal film in an oxidizing atmosphere of a hydrogen-rich (H 2 rich), oxidizing only the polysilicon film and the semiconductor substrate. However, the current selective oxidation process is limited only when tungsten film or tungsten nitride film is used as the metal gate electrode, and it can only adversely affect the characteristics of the MOSFET device because it is possible only in a hydrogen rich atmosphere and very high temperature of 700 ° C or higher. Can be.
본 발명의 목적은 재산화 공정에서 폴리실리콘막과 금속막 계면의 산화를 방지할 수 있어 동작 특성을 안정적으로 향상시킬 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다.An object of the present invention is to provide a method for forming a gate of a semiconductor device that can prevent the oxidation of the polysilicon film and the metal film interface in the reoxidation process to be able to stably improve the operating characteristics.
본 발명의 다른 목적은 이상 산화 또는 리프팅 현상을 발생시키지 않으면서 낮은 온도에서 실시하는 산화 공정을 폴리실리콘막과 금속막의 적층 게이트 뿐만 아니라 금속막 단일 게이트에도 적용할 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 있다. Another object of the present invention is to provide a method for forming a gate of a semiconductor device, which can be applied to a single gate of a metal film as well as to a stacked gate of a polysilicon film and a metal film by performing an oxidation process performed at a low temperature without causing abnormal oxidation or lifting phenomenon. To provide.
산소 또는 H2O 분위기에서 고온 열처리를 이용하여 재산화 공정을 실시할 경우 매우 높은 온도에 의해 금속막의 표면 뿐만 아니라 그레인 바운더리(grain boundary) 및 벌크(bulk)를 통해 확산된 산소가 금속막 내부 및 폴리실리콘막과 금속막의 계면까지 산화시킬 수 있으며, 이로 인해 이상 산화와 리프팅 등이 발생될 수 있다. 이러한 산소 분위기의 고온 열처리 대신 낮은 온도에서 플라즈마 산화 처리를 실시하면 폴리실리콘막과 금속막의 적층 게이트 게이트의 표면에만 국부적으로 재산화시킬 수 있는 장점이 있다. 또한 산소 플라즈마 처리를 실시한 후 질소 또는 수소 분위기에서 고온 열처리를 실시하면 좀더 우수한 특성의 표면 산화막을 얻을 수 있다. 더욱이 이 방법은 금속의 종류에 관계없이 적용할 수 있다.When the reoxidation process is performed by using a high temperature heat treatment in an oxygen or H 2 O atmosphere, oxygen diffused through the grain boundary and the bulk as well as the surface of the metal film by the very high temperature, It may oxidize to the interface between the polysilicon film and the metal film, which may cause abnormal oxidation and lifting. Plasma oxidation treatment at a low temperature instead of the high temperature heat treatment of the oxygen atmosphere has the advantage that it can be locally reoxidized only on the surface of the laminated gate gate of the polysilicon film and the metal film. In addition, by performing an oxygen plasma treatment and then performing a high temperature heat treatment in a nitrogen or hydrogen atmosphere, a surface oxide film having better characteristics can be obtained. Moreover, this method can be applied regardless of the kind of metal.
본 발명에 따른 반도체 소자의 게이트 형성 방법은 반도체 기판 상부의 소정 영역에 게이트 산화막 및 도전층이 적층된 게이트 패턴을 형성하는 단계와, 산소 플라즈마 처리를 실시하여 상기 도전층 측면에 산화막을 형성하는 단계와, 열처리 공정을 실시하여 상기 산화막의 막질을 개선하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of forming a gate of a semiconductor device according to the present invention, forming a gate pattern in which a gate oxide film and a conductive layer are stacked in a predetermined region on a semiconductor substrate, and performing an oxygen plasma treatment to form an oxide film on the side of the conductive layer. And, by performing a heat treatment process characterized in that it comprises a step of improving the film quality of the oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 설명함으로써 본 발명을 상세히 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시 예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시 예는 본 발명의 개시가 완전하도록 하며, 이 기술 분야에서 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 또한, 도면상에서 동일 부호는 동일 요소를 지칭한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the present disclosure and to those skilled in the art. It is provided to fully inform the scope of the invention. In addition, in the drawings, like reference numerals refer to like elements.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a gate forming method of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12) 및 폴리실리콘막(13)을 형성한다. 폴리실리콘막(13) 형성 과정에서 폴리실리콘막(13) 상부에 형성되는 자연 산화막을 제거하기 위해 HF를 포함하는 용액을 이용하여 세정 공정을 실시한다. 그리고, 전체 구조 상부에 확산 방지막(14), 금속막(15) 및 하드 마스크(16)를 순차적으로 형성한다. 마스크 공정 및 식각 공정으로 하드 마스크(16), 금속막(15), 확산 방지막(14) 및 폴리실리콘막(13)을 패터닝하여 게이트 패턴을 형성한다.Referring to FIG. 1A, a gate oxide film 12 and a polysilicon film 13 are formed on a semiconductor substrate 11. In the process of forming the polysilicon film 13, a cleaning process is performed using a solution containing HF to remove the native oxide film formed on the polysilicon film 13. Then, the diffusion barrier film 14, the metal film 15, and the hard mask 16 are sequentially formed on the entire structure. The hard mask 16, the metal film 15, the diffusion barrier 14, and the polysilicon film 13 are patterned by a mask process and an etching process to form a gate pattern.
여기서, 게이트 산화막(12)은 SiO2, SiOxNy 등의 실리콘 산화막 또는 HfO2, ZrO2, Hf-Al-O, Zr-Al-O, Hf-실리케이트, Zr-실리케이트 등의 Hf 또는 Zr을 포함하는 고유전 금속 산화물로 형성한다. 그리고, 폴리실리콘막(13)은 도프트 폴리실리콘막으로 형성한다. 또한, 확산 방지막(14)은 WNx, W과 WNx의 적층막, WSix과 WNx의 적층막, TaSixNy 또는 TiAlxNy중에서 선택적으로 형성하는데, 여기서 x와 y는 0.03∼3.00의 값을 갖는다. 그리고, 금속막(15)은 W, Ta, TaN, Ti 또는 TiN중에서 선택적으로 형성한다. 한편, 공정의 단순화를 위해서 확산 방지막(14)과 금속막(15)은 같은 계열을 사용하는 것이 바람직한데, 확산 방지막(14)으로 WNx, W과 WNx의 적층막 또는 WSix과 WNx의 적층막을 형성하면 금속막(15)으로 W을 형성하고, 확산 방지막(14)으로 TaSixNy를 형성하면 금속막(15)으로 Ta 또는 TaN을 형성하며, 확산 방지막(14)으로 TiAlxNy를 형성하면 금속막(15)으로 Ti 또는 TiN을 형성한다. 그리고, 확산 방지막(14)은 10∼300Å의 두께로 형성하고, 금속막(15)은 100∼1000Å의 두께로 형성한다.Here, the gate oxide film 12 includes a silicon oxide film such as SiO 2 , SiOxNy, or Hf or Zr such as HfO 2 , ZrO 2 , Hf-Al-O, Zr-Al-O, Hf-silicate, Zr-silicate, or the like. It is formed of a high dielectric metal oxide. The polysilicon film 13 is formed of a doped polysilicon film. Further, the diffusion barrier 14 is selectively formed from WNx, a laminated film of W and WNx, a laminated film of WSix and WNx, TaSixNy or TiAlxNy, where x and y have a value of 0.03 to 3.00. The metal film 15 is selectively formed among W, Ta, TaN, Ti, or TiN. On the other hand, in order to simplify the process, it is preferable to use the same series as the diffusion barrier 14 and the metal layer 15. As the diffusion barrier 14, a laminated film of WNx, W and WNx or a laminated film of WSix and WNx is formed. W is formed on the lower surface metal film 15, TaSixNy is formed on the diffusion barrier film 14, Ta or TaN is formed on the metal film 15, and TiAlxNy is formed on the diffusion barrier film 14, and the metal film 15 is formed. To form Ti or TiN. The diffusion barrier 14 is formed to a thickness of 10 to 300 GPa, and the metal film 15 is formed to a thickness of 100 to 1000 GPa.
도 1(b)를 참조하면, 산소 플라즈마 처리를 실시하여 게이트 산화막(12)의 에지 부분, 폴리실리콘막(13), 확산 방지막(14) 및 금속막(15)의 측면을 산화시켜 산화막(17)을 형성한다. 산소 플라즈마 처리는 RF 소오스 파워를 100∼3000W, RF 바이어스 파워를 0∼100W 정도 인가하여 실시한다. 또한, 산소 플라즈마 처리를 위한 산소 소오스로는 O2, O3, N2O, NO, H2O등 산소가 포함된 기체를 각각 사용하거나 혼합하여 사용한다. 또한, 산소 플라즈마 처리는 산소와 수소를 함께 플라즈마 소오스로 사용하여 실시하는데, 산소와 수소를 플라즈마 소오스로 함께 사용하기 위해서 산소/수소의 유량비는 0.01∼0.2로 한다. 한편, 산소 플라즈마 처리는 기판 온도를 0∼450℃로 하여 실시하고, 산소 플라즈마 처리시 표면 산화 반응을 높이기 위해 자외선을 기판 상부에 조사하기도 한다.Referring to FIG. 1B, an oxygen plasma treatment is performed to oxidize the edge portion of the gate oxide film 12, the polysilicon film 13, the diffusion barrier 14, and the side surfaces of the metal film 15 to oxidize the oxide film 17. ). Oxygen plasma treatment is performed by applying an RF source power of 100 to 3000W and an RF bias power of about 0 to 100W. In addition, as an oxygen source for oxygen plasma treatment, gases containing oxygen such as O 2 , O 3 , N 2 O, NO, and H 2 O may be used or mixed. The oxygen plasma treatment is performed using oxygen and hydrogen together as a plasma source. In order to use oxygen and hydrogen together as a plasma source, the flow rate ratio of oxygen / hydrogen is set to 0.01 to 0.2. On the other hand, the oxygen plasma treatment is carried out at a substrate temperature of 0 to 450 占 폚, and in order to increase the surface oxidation reaction during the oxygen plasma treatment, ultraviolet rays may be irradiated onto the substrate.
도 1(c)를 참조하면, 산소 플라즈마에 의해 형성된 산화막(17)의 특성을 향상시키 위해 산소가 포함되지 않은 질소, 수소, 아르곤 또는 진공 분위기에서 600∼1000℃의 온도에서 10초∼60분동안 실시한다.Referring to FIG. 1 (c), in order to improve the properties of the oxide film 17 formed by the oxygen plasma, 10 seconds to 60 minutes at a temperature of 600 to 1000 ° C. in a nitrogen, hydrogen, argon, or vacuum atmosphere containing no oxygen To be carried out.
본 발명에서 제시한 산소 플라즈마 처리를 실시하면 비교적 낮은 온도에서도 플라즈마에 의해 활성화된 산소 래디컬(radical)에 의해 게이트 산화막의 에지와 게이트의 표면은 쉽게 산화되지만, 온도가 낮아 확산이 잘되지 않기 때문에 게이트의 내부까지는 산화시키지 않는다. 이는 고온 재산화 공정 또는 선택 산화에 의한 폴리실리콘막과 금속막 계면의 산화를 방지할 수 있는 장점이 있다. 또한 선택 산화가 불가능한 금속 게이트의 경우에도 위 방법을 사용하면 재산화 공정이 가능하다. 즉, 본 발명의 다른 실시 예로서, 폴리실리콘막을 형성하지 않고 확산 방지막과 금속막으로 게이트를 형성하고 산화 공정을 실시할 수 있다.When the oxygen plasma treatment proposed in the present invention is carried out, even at a relatively low temperature, the edge of the gate oxide film and the surface of the gate are easily oxidized by oxygen radicals activated by the plasma, but the gate is not easily diffused due to the low temperature. It does not oxidize until inside. This has the advantage of preventing oxidation of the polysilicon film and the metal film interface by high temperature reoxidation process or selective oxidation. In the case of metal gates that are not capable of selective oxidation, the reoxidation process is also possible using the above method. That is, as another embodiment of the present invention, a gate may be formed of a diffusion barrier film and a metal film without performing a polysilicon film, and an oxidation process may be performed.
상술한 바와 같이 본 발명에 의하면 게이트의 표면만 산화되기 때문에 고온 재산화 공정 또는 고온 선택 산화 공정에 의한 폴리실리콘막과 금속막 계면의 산화를 방지하여 안정적인 소자의 동작 특성을 얻을 수 있다. 또한, 선택 산화가 불가능한 금속 게이트의 경우에도 이 방법을 이용하여 재산화 공정이 가능하기 때문에 다양한 금속의 게이트 전극으로의 적용이 가능하다. 따라서, 폴리실리콘막과 금속막의 적층 게이트 뿐만 아니라 금속막 단일 게이트 MOSFET 제작도 가능하다. As described above, according to the present invention, since only the surface of the gate is oxidized, oxidation of the polysilicon film and the metal film interface by a high temperature reoxidation process or a high temperature selective oxidation process can be prevented, thereby obtaining stable operating characteristics of the device. In addition, even in the case of a metal gate that is not capable of selective oxidation, it is possible to apply the reoxidation process using this method to the gate electrode of various metals. Therefore, not only the laminated gate of the polysilicon film and the metal film but also the metal film single gate MOSFET can be manufactured.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method for forming a gate of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 폴리실리콘막 14 : 확산 방지막13: polysilicon film 14: diffusion barrier film
15 : 금속막 16 : 하드 마스크15: metal film 16: hard mask
17 : 산화막17: oxide film
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| KR100741983B1 (en) | 2004-07-05 | 2007-07-23 | 삼성전자주식회사 | Semiconductor device having a gate insulating layer of a high dielectric constant and method of manufacturing the same |
| US7576395B2 (en) | 2004-07-05 | 2009-08-18 | Samsung Electronics Co., Ltd. | Dual gate stack CMOS structure with different dielectrics |
| KR100927410B1 (en) | 2008-05-21 | 2009-11-19 | 주식회사 하이닉스반도체 | Method for forming fine pattern in semiconductor device |
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| KR100615585B1 (en) * | 2004-09-09 | 2006-08-25 | 삼성전자주식회사 | method of forming gate pattern of semiconductor device |
| KR100907181B1 (en) * | 2007-09-19 | 2009-07-09 | 주식회사 동부하이텍 | Semiconductor device and method of fabricating the same |
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| KR100741983B1 (en) | 2004-07-05 | 2007-07-23 | 삼성전자주식회사 | Semiconductor device having a gate insulating layer of a high dielectric constant and method of manufacturing the same |
| US7576395B2 (en) | 2004-07-05 | 2009-08-18 | Samsung Electronics Co., Ltd. | Dual gate stack CMOS structure with different dielectrics |
| KR100927410B1 (en) | 2008-05-21 | 2009-11-19 | 주식회사 하이닉스반도체 | Method for forming fine pattern in semiconductor device |
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