KR100515405B1 - Manufacturing method of the flip-chip package substrate having embedded capacitors - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flip chip substrate having a capacitor embedded therein. In particular, by forming a mask layer on a flip chip substrate and peeling a part of the formed mask layer, an embedded capacitor is formed on the exfoliated portion to improve electrical characteristics. It relates to a method for manufacturing a flip chip substrate.

In addition, according to the present invention, a first step of forming a mask layer on the flip-chip package substrate is copper-plated on the top and peeling a portion of the formed mask layer to secure a space for the built-in capacitor; A second step of forming an embedded capacitor in the part peeled off in the first step; Peeling and removing the mask layer formed in the first step, and removing the upper copper plating layer of the flip chip package substrate to form a lower electrode pattern; And a fourth step of stacking an insulating layer on top of the embedded capacitor and forming a through hole in the stacked insulating layer to impart conductivity to the upper electrode of the embedded capacitor, and then performing a build-up process. A method for manufacturing a flip chip substrate is provided.

Description

Manufacturing method of the flip-chip package substrate having embedded capacitors

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flip chip substrate having a capacitor embedded therein. In particular, by forming a mask layer on a flip chip substrate and peeling a part of the formed mask layer, an embedded capacitor is formed on the exfoliated portion to improve electrical characteristics. It relates to a method for manufacturing a flip chip substrate.

To date, most discrete printed circuit boards (PCBs) are equipped with a typical discrete chip resistor or a typical discrete chip capacitor, but recently printed circuits incorporating passive elements such as resistors or capacitors Substrates are being developed.

This passive element embedded printed circuit board technology replaces the role of the existing chip resistors and chip capacitors by inserting passive elements such as resistors or capacitors into the outer or inner layers of the substrate by using new materials and materials. . In other words, a printed circuit board having a passive element embedded therein is a passive element, for example, a capacitor buried inside or outside of the substrate itself. If so, this is referred to as an "embedded capacitor," and this substrate is called an embedded capacitor PCB.

The most important feature of such capacitor-embedded printed circuit boards is that they do not need to be mounted on the substrate surface because the capacitor is inherently part of the printed circuit board.

On the other hand, the capacitor embedded printed circuit board technology to date can be largely classified into three methods, which will be described in detail below.

First, there is a method of implementing a polymer thick film type capacitor which applies a polymer capacitor paste and thermally cures, that is, dries to form a capacitor. This method produces a built-in capacitor by applying a polymer capacitor paste to an inner layer of a printed circuit board, and then printing and drying the copper paste to form an electrode after drying it.

Secondly, a ceramic filled photo-dielectric resin is coated on a printed circuit board to realize an embedded discrete type capacitor. Holds. In this method, after the photosensitive resin containing ceramic powder is coated on a substrate, copper foils are laminated to form respective upper and lower electrodes, and then circuit patterns are formed and the photosensitive resin is etched. To implement individual capacitors.

Third, a capacitor is implemented by inserting a separate dielectric layer having a capacitance characteristic in an inner layer of the printed circuit board to replace the decoupling capacitor mounted on the surface of the printed circuit board. Saga holds related patented technology. This method implements a power distributed decoupling capacitor by inserting a dielectric layer consisting of a power electrode and a ground electrode into an inner layer of a printed circuit board.

On the other hand, the speed of parts continues to increase in order to satisfy various functions and excellent performance of electronic products, and in order to improve the speed of parts, the bonding method of the packet also includes lead frames and wire bonding. (Wire Bonding), pin type (Bonding) bonding (Bonding) method is changing from a small ball type bonding (Ball Type Bonding) method, flip-chip bonding (Flip-Chip Bonding) method.

 Currently, in the case of a high speed product employing flip-chip bonding, a clock operates at a speed of 2 GHz or more in the case of a CPU or a graphic chip set.

In the case of such a CPU or a chipset, a short signal rising time, more current is required, and signal lines with an IC, a flip chip package, and a main board are required to operate at a high speed. It is designed to keep the gap short.

 However, as the component speed increases, voltage fluctuations occur in the power supply wiring, and eventually high frequency noise called SSN (Simultaneous Switching Noise) or Delta-I (ΔI) is generated.

These high frequency noises (SSNs) can cause delays or logic faults in the system, resulting in poor system performance and poor system reliability.

To reduce these SSNs, it is most effective to reduce the inductance of the power supply wiring when the current required for the device operation and switching speed cannot be changed, and decoupling to reduce the power line voltage fluctuations of the power supply wiring. Capacitor).

Decoupling Chip Capacitors are installed in the power supply wiring to directly supply the current required for switching the circuit, shielding the inductance of the power supply wiring to significantly reduce the voltage drop effect and reduce the SSN. .

FIG. 1 shows that a flip-chip bonding package of a high-speed product such as a CPU or a graphic chip set according to the related art is mounted on a PCB main board.

Referring to FIG. 1, a power supply line 19 and a ground line 18 are embedded in the PCB motherboard 20, and a bulk capacitor 17 is generated near the VRM, and a decoupling capacitor 16 is provided. It is.

In addition, the flip chip substrate 14 is connected to the PCB motherboard 20 by ball bonding 15. The flip chip substrate 14 is provided with a low inductance capacitor 13, and the solder bumps 12 The chip 11 is mounted.

As shown in FIG. 1, the decoupling chip capacitor 16 may include a PCB Mother (Main) Board 20, a Flip-Chip Package Substrate 14, or a decoupling Chip Capacitor 16. It is mounted inside the IC to allow the system to operate smoothly even in the high frequency range.

 2 shows Delta I or ΔI (SSN) according to a mounting position of a decoupling capacitor according to the prior art. Referring to FIG. 2, a bulk capacitor 27 is generated near the VRM, and decoupling capacitors 26a, 26b, and 26c are positioned through the PCB P / G networks 23a and 23b, and are generated by ball bonding. There is an inductance 25 and an inductance 22 generated by flip chip bump bonding.

As can be seen in FIG. 2, it is an effective design method to place a decoupling capacitor inside the IC closest to the IC so that ΔI is the smallest.

However, implementing a decoupling capacitor inside the IC is expensive. Therefore, in case of current CPU or chipset, a decoupling capacitor is mounted on a flip chip package substrate to overcome problems such as high frequency noise and voltage fluctuation caused by high frequency. have.

As such, a decoupling capacitor having a capacitance of about 0.1 to 1 GHz on a CPU and a chipset package substrate (Chip Set Flip-Chip Package Substrate) is alone or an array type. 9 ~ 20 units are used to supply the current necessary for switching the IC.

As the system speeds up in the future, the current power supply loop inductance, path caused by relatively long power supply wiring to supply current to the decoupling capacitor is also switching. Decoupling capacitor (MLCC or LICC) consisting of inductance and ceramic chip itself, and parasitic inductance generated from solder contacts when mounting MLCC or LICC on a board. When a lot of high frequency noise (SSN) is generated in the supply wiring, as the power voltage level decreases, the supply current of the driver decreases, the signal delay increases, and EMI problems occur.

To overcome these problems, shorter power supply wiring and at the same time reduce parasitic inductance, a decoupling capacitor is installed inside the IC or inside the flip-chip package substrate. have.

The embedded decoupling capacitor is a method that enables stable power supply required by a CPU or chipset operating at a high frequency.

However, the built-in decoupling capacitor has the disadvantage that the material, capacitance capacity, implementation method, and manufacturing cost of implementing the embedded decoupling capacitor inside the IC are too high.

Currently, a lot of researches have been conducted to implement embedded decoupling capacitors in flip-chip package substrates for high speed products. Looking at it as follows.

3A to 3K illustrate a method of manufacturing a capacitor-embedded flip chip substrate according to the prior art.

3A to 3E are views illustrating a manufacturing process of a silicon chip capacitor, and FIGS. 3F to 3K include an embedded capacitor by mounting a manufactured capacitor in a package. It is a process of manufacturing a package substrate.

 First, as shown in FIG. 3A, a silicon substrate 301 is provided, and as shown in FIG. 3B, titanium or titanium nitride is deposited on the silicon substrate 301. Barrier layer 302 is formed.

Next, as shown in FIG. 3C, platinum, paradium, tungsten, or AlSiCu is deposited on the barrier layer 302 to have a thickness of 1 to 10 μm. A lower electrode 303 of a silicon chip capacitor is formed.

As shown in FIG. 3D, a dielectric layer of a capacitor having a thickness of 100 to 1000 Å is deposited by depositing a high dielectric constant material such as SrTiO 3, BaTiO 3, Pb (Zr) TiO 3, Ta 2 O 5, or the like on the lower electrode 303. Dielectric layer) 304 is formed.

As shown in FIG. 3E, the upper electrode 305 of the silicon chip capacitor is formed by forming the lower electrode 303 of the silicon chip capacitor on the dielectric layer 304. .

Thereafter, a silicon chip capacitor having a plurality of through holes and having a thickness of 30 to 150 μm is mounted on an electronic package on which a conductive material is deposited, and then an insulating layer is formed to form a silicon chip capacitor. To manufacture a flip chip package.

That is, as shown in FIG. 3F, a flip chip package substrate in which an electronic inner circuit in which a plurality of via holes and conductive materials are deposited is formed is illustrated, and a silicon chip manufactured thereon as shown in FIG. 3F is illustrated. Capacitor (Silicon Chip Capacitor) is mounted.

3H forms an insulating layer 309 having a thickness of 80 to 150 μm on the silicon chip capacitor mounted in FIG. 3F.

In FIG. 3I, a via hole 310 is formed in the insulating layer 309 through laser processing. At this time, the hole diameter is processed to about 50 ~ 300㎛.

In FIG. 3J, a conductive material 312 is deposited to electrically connect the upper electrode 305 of the silicon chip capacitor, and FIG. 3K illustrates a capacitor completed using a build-up process. A cross-sectional view of the built electrical package.

However, the capacitor-embedded flip chip substrate formed by the above-described conventional technology causes problems due to high manufacturing process cost and increase in lead type, and also increases the thickness of the package substrate and increases the resistance of the lower electrode of the silicon chip. There was an increasing problem.

That is, Intel patent (US 6,407,929) uses a process of manufacturing a silicon chip capacitor and a manufactured silicon chip capacitor in a package, and uses a build up technology. To fabricate a package substrate including an embedded capacitor, wherein the total number of processes includes a large number of processes with about 15 processes, and in particular, a silicon chip capacitor in the middle of manufacturing a package substrate. (Silicon Chip Capacitor) has to be mounted, so the continuous manufacturing process is difficult and a lot of lead time is required.

In addition, the silicon chip capacitor has an insulating distance between the lower upper conductive layer and the lower conductive layer due to the thickness of the conductive adhesive film or the conductive paste of 30 to 150 μm and the thickness of the conductive layer of the package substrate having a constant thickness. (This patent describes the formation of a nonconductive layer having a thickness of 80 to 150 μm, which is about 50 to 90 μm thicker than the 30 to 60 μm insulation distance of a typical Flip-Chip Package Substrate.) Increasing the insulation distance increases the height of the electrically conducting hole, increasing the parasitic inductance and causing problems in the electrical characteristics of flip chip ICs operating at high frequencies. In addition, the demand for low-insulation package substrates is increasing in many high-speed application electronic component markets.

 In addition, after forming a conductive adhesive film or a conductive paste on the package substrate, the silicon chip capacitor is mounted, and after printing the solder paste mainly used for mounting general chip parts, the IR reflow process When bonding to the electrode of a silicon chip capacitor using a conductive material rather than a metal bonding between the electrode and the substrate, the bonding reliability is lower than that of the metal, the resistance of the conductive adhesive film or paste is about 1 * 10-4 to 10-5 Ωcm, which is higher than the resistance of the bond between metals (about 1 * 10-6 Ωcm).

Accordingly, the present invention has been made to solve the above problems, and after forming a mask layer on a flip chip package substrate, a portion of the mask layer is exposed, developed, and peeled off to form an embedded capacitor in the exfoliated portion and then insulated. It is an object of the present invention to provide a method for manufacturing a capacitor-embedded flip chip substrate having improved electrical characteristics by laminating layers.

The present invention for achieving the above object is a first step of forming a mask layer on the copper plated flip chip package substrate and peeling a portion of the formed mask layer to secure the production space of the embedded capacitor; A second step of forming an embedded capacitor in the part peeled off in the first step; Peeling and removing the mask layer formed in the first step, and removing the upper copper plating layer of the flip chip package substrate to form a lower electrode pattern; And a fourth step of performing a build-up process after stacking an insulation layer on the embedded capacitor and forming a through hole in the stacked insulation layer to impart conductivity to the upper electrode of the embedded capacitor. .

Now, the preferred embodiment of the present invention will be described in detail with reference to FIG. 4A.

4A to 4L illustrate a method of manufacturing a flip chip substrate having a capacitor embedded therein according to an embodiment of the present invention.

Here, flip chip is derived from a shape in which a bare chip is inverted and bonded to a substrate, and flip chip is a low-reliability manual wire bonding made by IBM in the early 60's. It was developed as a replacement for IBM and was known by IBM at the time of development as the Controlled Collapse Chip Connection (C4) name.

This method deposits a solder bump on a metallization site formed on an Al pad of a bare chip, and forms a spherical shape of the solder by a reflow soldering process.

Bare chips with solder are bonded to the substrate by a reflow soldering process. In order to deposit solder bumps, metalizing such as Cr, Au, Ti, Cu, etc. is deposited or etched on Al pads on the bare chip surface. The surface must be treated to allow the wetting of the solder. This is also called UBM (Under Bump Metallurgy).

During melting of the solder, a layer of passivation is formed around the solder to prevent short-circuit in the circuit due to the flow of the solder to other places by wetting.

The passivation layer serves to protect not only insulation but also circuits or silicon surfaces from impurities and moisture. Solder uses 95% Pb-5% Sn (Tm = 315oC) for ceramic substrates and 37% Pb-63% Sn (Tm = 183oC) eutectic for PCBs and other substrates. Use the composition.

4A shows a cross-section of a single layer or multilayer flip chip package substrate. Referring to FIG. 4A, a via hole 403 having a diameter of 50 to 200 μm is formed by a mechanical drill or a laser drill on a copper foil laminate and filled or electroless using a conductive paste. After conducting conduction using electroless copper plating technology, the inner space of the via hole 403 is filled with a polymer resin.

Then, the upper portion of the non-copper laminate plate 401 is electroless copper plating to form an electroless plating layer 402 with a thickness of 0.8 ~ 1.5㎛.

Thereafter, in FIG. 4B, a dry film having a thickness of 20 to 40 μm is laminated, followed by exposure, development, and peeling to form a mask layer 404.

In this case, in order to increase the interfacial adhesion between the dry film and the electroless plating layer 402, a process of increasing the adhesion by forming roughness on the surface of the electroless plating layer 402 using chemical soft etching may be added. .

In addition, in FIG. 4C, the lower electrode 405 of the embedded capacitor having a thickness of 4 to 10 μm is formed by electrolytic copper plating on the electroless plating layer 402 exposed to the surface by peeling the dry film. Form.

Next, a high dielectric constant material such as BaTiO 3, Ta 2 O 5, or the like in FIG. 4D is dielectric layer 406 having a thickness of 100 to 8000 μm on top of the lower electrode 405 by using IBS (Ion Beam Sputter Deposition) technology at normal temperature and pressure. ).

In this case, in order to increase the adhesion between the electrolytic copper plating layer 405 and the dielectric layer 406, the surface of the copper plating layer (Copper) 405 may be chemically soft etched or plasma ion beam treatment. It can also increase surface energy.

In FIG. 4E, a thin conductive layer 407 is formed to form the upper electrode 407 of the embedded capacitor on top of the dielectric layer 406. At this time, the thin conductive layer 407 is deposited by using IBSD to target materials (copper) to 100 ~ 3000Å thickness at room temperature and atmospheric pressure conditions or less electroless copper plating (Electroless Copper Plating) ) To form a thin conductive layer for the upper electrode 407 to a thickness of 0.8 ~ 1.5㎛.

In FIG. 4F, electrolytic copper plating is performed on the thin conductive layer 407 to form a plating layer having a thickness of 4 to 10 μm to form the upper electrode 408 of the embedded capacitor.

In FIG. 4G, the upper electrode 408 and the thin conductive layer 407 covering the mask layer 404 are polished using a ceramic buffer so that the mask layer 404 is exposed to the outside. Cerrmic Buffer) is a technology widely used in the printed circuit board. Then, the mask layer 404 exposed to the outside is peeled off using the sodium hydroxide (NaOH) solution.

In FIG. 4H, the 0.8-1.5 μm-thick electroless plating layer 402 remaining after the mask layer 404 is peeled off is subjected to flash etching using an etching solution of hydrochloric acid type, such as fruit water or sodium chlorate.

At this time, while the electroless plating layer 402 is etched, the upper electrode 408 is also etched about 1.0 μm. The electroless plating layer 402, which has been electrically connected to each other through flash etching, is formed as a lower electrode 402 of an independent embedded capacitor.

In Fig. 4I, an insulating layer 409 having a thickness of 30 to 60 mu m is formed. At this time, the insulating material is bonded to the lower layer 401 at a constant temperature and pressure by using a resin having a dielectric constant of about 3.5 to 4.8.

At this time, roughness is formed on the surface by using H ₂ O ₂ and H ₂ SO ₄ to increase the adhesion between the upper copper electrode 408 and the insulating layer 409 constituting the lower layer 401 and the embedded capacitor. To increase the surface area.

In FIG. 4J, a via hole 410 is formed in a stacked insulating layer 409 using a laser. At this time, the hole diameter is processed to about 50 ~ 150㎛.

In FIG. 4K, a conductive material is deposited to electrically connect the surface of the insulating layer 410 and the upper electrode 408 of the embedded capacitor. In this case, the conductive material is filled or conducted using electroless copper plating technology, and then the inner space of the via hole 410 is filled with a polymer resin, or after electroless copper plating, the via hole 410 is electroplated again. ) Is plated with copper, and copper plating is also formed on the upper insulating layer 409.

4L is a cross-sectional view of an electronic package containing an embedded capacitor completed using a build-up process.

5 is a flowchart illustrating a manufacturing process of a capacitor-embedded flip chip substrate according to an embodiment of the present invention.

Referring to the drawings, the manufacturing process of the capacitor-embedded flip chip substrate according to an embodiment of the present invention is a manufacturing step (S501), a mask layer forming step (S502), a lower electrode forming process ( S503), high dielectric constant insulating layer forming process (S504), upper electrode conductive layer forming process (S505), upper electrode forming process (S506), ceramic polishing process (S507), mask layer peeling process (S508), lower electrode pattern formation The process (S509), the upper insulating layer forming process (S510), the micro via hole forming process (S511), the conductive layer forming process (S512), the build-up process is carried out (S513).

First, when a single layer or multilayer flip layer package substrate is manufactured in step S501, a dry film is laminated in step S502, followed by exposure, development, and peeling to form a mask layer.

In step S503, the dry film is peeled off to form a lower electrode by electrolytic copper plating on the top of the electroless plating layer exposed on the surface, and in step S504, a high dielectric constant material is subjected to IBSD (Ion Beam Sputter Deposition) technology at room temperature and pressure. A dielectric layer is formed on the lower electrode by using a.

In step S505, a thin conductive layer is formed on top of the dielectric layer, and in step S506, an electrolytic copper plating is formed on the top of the thin conductive layer to form an upper electrode, or an electroless copper plating with lower process cost. By forming a thin conductive layer for the upper electrode to a thickness of 0.8 ~ 1.5㎛.

In step S506, electrolytic copper plating is performed on the thin conductive layer to form a plating layer having a thickness of 4 to 10 μm to form an upper electrode of the embedded capacitor.

In step S507, the upper electrode covering the mask layer and the thin conductive layer are polished by using ceramic polishing to expose the mask layer to the outside, and the ceramic polishing is widely used in printed circuit boards. It is a skill.

After removing the dry film of the mask layer in step S508 to form a lower electrode in step S509 to form an insulating layer having a thickness of 30 ~ 60㎛ in step S510.

In step S511, a via hole is formed in the insulating layer using a laser, and in step S512, a conductive material is deposited to electrically connect the surface of the insulating layer and the upper electrode of the embedded capacitor. After that, the build-up process is performed.

Herein, while the present invention has been described with reference to the preferred embodiments, those skilled in the art can variously change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

According to the present invention as described above, it is possible to remove the pin bonding for providing the connection of the chip capacitor in the flip chip substrate, it is effective to enable the processing of a thinner flip chip package.

In addition, according to the present invention, the circuit density of the flip chip substrate can be increased due to the reduction in the mounting area due to the removal of the chip capacitor on the flip chip substrate.

In addition, according to the present invention, since the capacitor is embedded in the flip chip substrate, the impedance due to the power supply wiring is reduced, the noise is reduced, the wiring length is shortened, the parasitic inductance is reduced, and the electrical performance is improved.

FIG. 1 is a view showing a flip-chip bonding package of a high-speed product such as a CPU or a graphic chip set according to the related art mounted on a PCB main board.

 FIG. 2 is a diagram illustrating Delta I or ΔI (SSN) according to a mounting position of a decoupling capacitor according to the prior art.

3A to 3K illustrate a method of manufacturing a capacitor-embedded flip chip substrate according to the prior art.

4A to 4L illustrate a method of manufacturing a flip chip substrate having a capacitor embedded therein according to an embodiment of the present invention.

5 is a flowchart illustrating a method of manufacturing a flip chip substrate with a capacitor according to an embodiment of the present invention.

Description of the main parts of the drawing

401: copper-free laminated plate 402: electroless copper plating layer

403: via hole 404: mask layer

405: lower electrode 406: dielectric layer

407 thin conductive layer 408 upper electrode

409: insulating layer 410: via hole

Claims (13)

A first step of forming a mask layer on an upper plated flip chip package substrate and peeling a portion of the formed mask layer to secure a production space of an embedded capacitor; A second step of forming an embedded capacitor in the part peeled off in the first step; A third step of peeling and removing the mask layer formed in the first step, and peeling the upper plating layer of the flip chip package substrate to form a lower electrode pattern; And A fourth step of performing a build-up process after stacking an insulating layer on the embedded capacitor and forming a conductive hole in the stacked insulating layer to impart conductivity to the upper electrode of the embedded capacitor, and then performing a build-up process. Method of manufacturing a chip substrate. The method of claim 1, The first step is, A first step of manufacturing a flip-chip package substrate having an electroless copper plated upper surface thereof; And A flip chip including a capacitor comprising a first and second steps of laminating and peeling a dry film on the flip chip package substrate provided in step 1-1 to secure a space for generating an embedded capacitor. Method of manufacturing a substrate. The method of claim 2, After the first step 1-1, A method of manufacturing a flip chip substrate with a capacitor further comprising the first to third steps of increasing the surface energy of the electroless plating layer formed on the flip chip package substrate. The method of claim 1, The second step, A second step of forming a lower electrode of an embedded capacitor by electrolytic copper plating on the electroless plating layer from which the mask layer is peeled off; A step 2-2 of forming a dielectric layer by stacking a high dielectric constant material on the lower electrode formed in step 2-1; And And forming the upper electrode of the embedded capacitor on the dielectric layer formed in the above 2-2 step. The method of claim 4, wherein After the step 2-1, The method of claim 1, further comprising a step 2-4 of increasing the surface energy of the lower electrode formed in the step 2-1. The method of claim 4, wherein The second step is, Step 2-3-1 forming a thin conductive layer at room temperature and atmospheric pressure using copper as the target material using IBSD on the dielectric layer formed in step 2-2; And A step 2-3-2 of forming an upper electrode of the embedded capacitor by electrolytic copper plating on the thin conductive layer formed in the step 2-3-1; Method for manufacturing a flip chip substrate containing a capacitor made of a. The method of claim 4, wherein The second step is, Step 2-3-1 to form a thin conductive layer by electroless copper plating on the dielectric layer formed in the step 2-2; A step 2-3-2 of forming an upper electrode of the embedded capacitor by electrolytic copper plating on the thin conductive layer formed in the step 2-3-1; And Step 2-3-3 of removing the thin conductive layer and the upper electrode covering the mask layer by using ceramic polishing Method for manufacturing a flip chip substrate containing a capacitor made of a. The method of claim 6, The thickness of the electrolytic copper plating layer formed in the step 2-3-2 is 4 ~ 10㎛ the manufacturing method of the flip chip substrate with a capacitor. The method of claim 7, wherein The thickness of the electrolytic copper plating layer formed in the step 2-3-2 is 4 ~ 10㎛ the manufacturing method of the flip chip substrate with a capacitor. The method according to any one of claims 4 to 7, The electrolytic copper plating layer formed in the step 2-1 has a thickness of 4 ~ 10㎛ method for manufacturing a flip chip substrate with a capacitor. The method according to any one of claims 4 to 7, In the step of laminating the high dielectric constant material in the step 2-2, the high dielectric constant material is laminated to have a thickness of 100 to 8000Å over the lower electrode by using IBSD (Ion Beam Sputter Deposition) at normal temperature and pressure. A method of manufacturing a flip chip substrate incorporating a capacitor. The method of claim 1, The third step, Step 3-1 of peeling off the dry film of the mask layer using a sodium hydroxide (NaOH) solution; And A method of manufacturing a flip chip substrate with a built-in capacitor, comprising the step of removing the mask layer and flash etching the electroless plating layer exposed on the surface to form a lower electrode pattern. The method of claim 1, The fourth step, A step 4-1 of forming an insulating layer by stacking an insulating resin on top of the embedded capacitor; 4-2 step of forming a via hole by laser processing the insulating layer laminated in the step 4-1; And A method of manufacturing a flip chip substrate incorporating a capacitor, the method comprising: providing a conductivity to a via hole formed in step 4-2 and performing a build up process.