KR100512177B1 - Image sensor and method of fabricating the same - Google Patents

Abstract

An image sensor and a method of manufacturing the same are provided. In this image sensor, a blocking pattern is disposed on photodiodes formed on a substrate. The blocking pattern is made of an insulating film having a lower diffusion coefficient of a metal element than a silicon oxide film. Thus, the blocking pattern protects the photodiodes from contamination of metal elements. As a result, conventional dark defects can be minimized. In addition, the image sensor includes a color ratio adjusting film. The color ratio adjusting film adjusts the color ratio between the sensitivity of blue, green and red, which are three primary colors of color light. Accordingly, color sharpness of an image implemented by the image sensor may be improved.

Description

Image sensor and method of manufacturing the same {Image sensor and method of fabricating the same}

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an image sensor and a method of manufacturing the same.

Among semiconductor devices, an image sensor is an element that transforms an optical image into an electrical signal. The image sensor can be classified into two types. Complementary Metal-Oxide-Silicon (CMOS) image sensors and Charge Coupled Device (CCD) image sensors. The CCD image sensor is superior in sensitivity to noise and noise than the CMOS image sensor, but has high integration difficulty and high power consumption. In contrast, the CMOS image sensor has simpler processes, is suitable for high integration, and has lower power consumption than a CCD image sensor.

In recent years, as the manufacturing technology of semiconductor devices is highly developed, the manufacturing technology and characteristics of CMOS devices are greatly improved. Therefore, research on the CMOS image sensor is actively progressing.

Typically, a pixel of the CMOS image sensor includes a photodiode that receives light and CMOS elements that control image signals input from the photodiode.

1 is an equivalent circuit diagram illustrating a pixel of a typical CMOS image sensor.

Referring to FIG. 1, a CMOS image sensor may include a photodiode PD, a transfer transistor, a reset transistor, a select transistor, and an access transistor. transistor). The transfer transistor TT and the reset transistor TR are connected in series to the photodiode PD, and an applied voltage Vdd is connected to the drain of the reset transistor TR. The drain (source of the reset transistor) of the transfer transistor TT corresponds to a floating diffusion layer (F / D). The floating diffusion layer F / D is connected to the gate of the selection transistor TS. The selection transistor TS and the access transistor TA are connected in series, and an applied voltage Vdd is connected to the drain of the selection transistor TS. The gate of the access transistor TA is connected to an input port Pi, and the source of the access transistor TA is connected to an output port Po.

In operation of the CMOS image sensor having the above-described structure, first, the reset transistor TR is turned on to apply the applied voltage to the floating diffusion layer F / D, and then the reset transistor TR Off. Therefore, a predetermined potential is applied to the floating diffusion layer F / D, and a predetermined potential is also applied to the gate of the selection transistor TS. As a result, a predetermined potential is applied to the source of the selection transistor TS. This state is called a reset state.

In the reset state, when light is incident on the photodiode PD, electron-hole pairs (EHP) are generated to generate signal charges, and the signal charges are accumulated in the photodiode PD. do. At this time, when the transfer transistor TT is turned on, the accumulated signal charges move to the floating diffusion layer F / D to change the potential of the floating diffusion layer F / D. As a result, the gate potential of the selection transistor TS is also converted. As a result, the potential applied to the source of the selection transistor TS is also changed. According to the access signal applied to the input port Pi, data is output to the output port Po. After outputting the data, the image sensor is switched back to the reset state. These processes are repeated to output a video signal.

Some of the sources / drains of the transistors TT, TR, TS, and TA may form metal silicide films on their surfaces to reduce ohmic contact or resistance.

2 is a schematic cross-sectional view for explaining a method of manufacturing a conventional CMOS image sensor. In the drawings, reference numerals "a" and "b" denote light receiving element regions and CMOS element regions, respectively.

Referring to FIG. 2, an isolation region 2 is formed on a p-type semiconductor substrate 1 having a light receiving element region a and a CMOS element region b to define an active region. The light receiving element region a is a region in which a photodiode PD is formed, and the CMOS element region b is a region in which CMOS elements are formed. A gate oxide film 3 and a gate electrode film are sequentially formed on the entire surface of the semiconductor substrate 1 having the device isolation film 2, and the gate electrode film and the gate oxide film 3 are successively patterned to form a gate pattern 5. Form. The gate pattern 5 is formed in the CMOS element region b. The gate pattern 5 includes a stacked gate oxide film 3 and a gate electrode 4.

An n-type photodiode 6 is formed in the diode region, which is an active region disposed in the light receiving element region a. A p-type photodiode 7 is formed between the n-type photodiode 6 and the surface of the active region.

A low concentration impurity diffusion layer 8 is formed in active regions adjacent to both sides of the gate pattern 5. The spacer film 9 is formed on the entire surface of the semiconductor substrate 1 having the low concentration impurity diffusion layer 8. The spacer layer 9 is selectively isotropically etched to form spacers 9a on both sides of the gate pattern 5. In this case, the spacer layer 9 remains on the photodiodes 6 and 7.

A high concentration impurity diffusion layer 8a is formed in active regions on both sides of the spacer 9a. A metal film 10 is formed over the entire surface of the semiconductor substrate 1 having the high concentration impurity diffusion layer 8a, and the metal film 10 is silicided to form a metal silicide film 10a. The metal silicide film 10a is selectively formed only on the surface of the high concentration impurity diffusion layer 8a. That is, the spacer layer 9 on the photodiodes 6 and 7 prevents the metal silicide layer 10a from being formed on the photodiodes 6 and 7.

In the silicidation process, the metal film 10 on the photodiodes 6 and 7 remains as it is. Therefore, during the silicideation process, metal elements of the metal film 10 may penetrate into the photodiodes 6 and 7 through the spacer layer 9 on the photodiodes 6 and 7. have. Due to the penetrated metal elements, the photodiodes 6 and 7 may increase the amount of dark current. The dark current refers to a current flowing in a pixel in which no light is incident on the photodiodes 6 and 7. The dark current may increase a dark defect in which a pixel to which light is not incident operates.

It is an object of the present invention to provide an image sensor and a method of manufacturing the same that can minimize dark defects.

Another object of the present invention is to provide an image sensor capable of improving color distinction of an image and a method of manufacturing the same.

It provides an image sensor for solving the above-described technical problem and other technical problems. Provided are image sensors for solving the above-described technical problem and other technical problem. An image sensor according to an embodiment of the present invention may include a device isolation layer formed on a substrate of a first conductivity type to define a diode region and an active region. In the diode region, a second conductivity type photodiode having a predetermined depth from the surface of the substrate is disposed. A first conductive photodiode is interposed between the second conductive photodiode and the surface of the substrate. A first gate is disposed on the active region adjacent to the diode region. Sidewall spacers are disposed on at least one side wall of the first gate opposite to the diode region. The sidewall spacer is composed of a first spacer having a "L" shape and a second spacer disposed on the first spacer. A blocking pattern and an insulation pattern, which are sequentially stacked on the diode region, are disposed. The blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. According to another exemplary embodiment, an image sensor includes a device isolation layer formed on a substrate of a first conductivity type to define a diode region and an active region. can do. In the diode region, a second conductivity type photodiode having a predetermined depth from the surface of the substrate is disposed. A photoconductive diode of the first conductivity type is interposed between the photodiode of the second conductivity type and the surface of the substrate. A first gate is disposed on the active region adjacent to the diode region, and a floating diffusion layer is disposed in an active region on one side of the first gate opposite to the diode region. A silicide prevention pattern covering the diode region, the first gate and the floating diffusion layer is disposed, and a color ratio control layer is disposed on the silicide prevention pattern.

An image sensor according to another embodiment of the present invention may include an isolation layer formed on a substrate of a first conductivity type to define a diode region and an active region. A second conductive photodiode having a predetermined depth from the surface of the substrate is disposed in the diode region, and a first conductive photodiode is interposed between the second conductive photodiode and the surface of the substrate. do. A first gate is disposed on the active region adjacent to the diode region, and a floating diffusion layer is disposed in an active region on one side of the first gate opposite to the diode region. A blocking pattern is disposed on the diode region, and a silicide prevention pattern covering the blocking pattern, the first gate, and the floating diffusion layer is disposed. A color ratio adjusting layer is disposed on the silicide prevention pattern. In this case, the blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film.

It provides a method of manufacturing an image sensor for solving the above-described technical problem and other technical problems. The method of forming an image sensor according to an exemplary embodiment of the present invention may include forming an isolation layer defining a diode region and an active region on a substrate of a first conductivity type. Forming a second conductivity type photodiode having a predetermined depth from the surface of the substrate, a photodiode of the first conductivity type interposed between the second conductivity type photodiode and the surface of the substrate in the diode region; do. A first gate is formed on the active region adjacent to the diode region. A sidewall spacer formed of a blocking pattern and a spacer insulating pattern stacked on the diode region and at least one sidewall of the first gate facing the diode region is formed. In this case, the blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film, wherein the first spacer is in an “L” shape, and the second spacer is formed on the first spacer. According to another exemplary embodiment, a method of forming an image sensor may include forming an isolation layer defining a diode region and an active region on a substrate of a first conductivity type. Forming a second conductive photodiode having a predetermined depth from the surface of the substrate and a photodiode of the first conductive type interposed between the second conductive photodiode and the surface of the substrate in the diode region; . A first gate is formed on the active region adjacent to the diode region, and a floating diffusion layer is formed in the active region on one side of the first gate opposite to the diode region. A silicide prevention pattern covering the diode region, the first gate, and the floating diffusion layer is formed, and a color ratio control layer is formed on the entire surface of the substrate having the silicide prevention pattern.

In another embodiment, a method of forming an image sensor may include forming an isolation layer defining a diode region and an active region on a substrate of a first conductivity type. Forming a second conductive photodiode having a predetermined depth from the surface of the substrate and a photodiode of the first conductive type interposed between the second conductive photodiode and the surface of the substrate in the diode region; . A first gate is formed on the active region adjacent to the diode region, and a floating diffusion layer is formed in the active region on one side of the first gate opposite to the diode region. A blocking pattern is formed on the diode region, and a silicide prevention pattern covering the blocking pattern, the first gate, and the floating diffusion layer is formed. A color ratio control film is formed on the entire surface of the substrate having the silicide prevention pattern. The blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the implementations introduced herein are provided so that the disclosure may be thorough and complete, and the spirit of the present invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

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3 is a plan view illustrating an image sensor according to a preferred embodiment of the present invention, FIG. 4 is a cross-sectional view taken along the line II ′ of FIG. 3, and FIG. It is a simulation graph.

3 and 4, an image sensor according to a preferred embodiment of the present invention includes a first conductive semiconductor substrate 101. An isolation layer 103 is disposed in a predetermined region of the semiconductor substrate 101 to define the diode region 80 and the active region 90. The diode region 80 is a region where photodiodes are formed. The active region 90 is connected to one side of the diode region 80. First, second and third gates 107a, 107b, and 107c are sequentially disposed on the active region 90 at predetermined intervals. The first, second and third gates 107a, 107b, and 107c correspond to the gate of the transfer transistor TT, the gate of the reset transistor TR, and the gate of the selection transistor TS of FIG. 1, respectively. The first gate 107a is disposed on the active region 90 adjacent to the diode region 80. A fourth gate (not shown) spaced apart from the third gate 107c at a predetermined interval may be disposed on the active region 90. The fourth gate corresponds to the gate of the access transistor TA of FIG. 1. A gate insulating layer 105 is interposed between the gates 107a, 107b, and 107c and the semiconductor substrate 101.

A second conductive photodiode 113 having a predetermined depth from the surface of the semiconductor substrate 101 is disposed in the diode region 80. The first conductive photodiode 114 is disposed between the second conductive photodiode 113 and the surface of the semiconductor substrate 101. One side of the first conductive photodiode 114 is connected to the substrate 101. A first conductivity type well 111 surrounding the device isolation layer 103 may be further disposed. When the first conductivity type well 111 is disposed, one side of the first conductivity type photodiode 114 may extend to be connected to the first conductivity type well 111. Accordingly, the first conductivity type photodiode 114 is connected to the semiconductor substrate 101 via the first conductivity type well 111. The first conductivity type may be p-type, and the second conductivity type may be n-type. On the contrary, the second conductivity type may be n type and the first conductivity type may be p type.

The second conductive photodiode 113 forms a PN junction with the first conductive substrate 101, and a depletion layer is formed based on the PN junction surface. Light generated from the subject is incident on the depletion layer to form electron-hole pairs EHP from the depletion layer. Thus, signal charges are accumulated in the photoconductor 113 of the second conductivity type.

The first conductive photodiode 114 serves to suppress dark current caused by a dangling bond or the like distributed on the surface of the semiconductor substrate 101. That is, electron-hole pairs may be generated due to the dangling bond or the like to generate a dark current. The first conductivity type photodiode 114 emits one of the electrons and holes generated by the dangling bond and the like to the semiconductor substrate 101, and the other is self-recombined and extinguished. For example, when the first conductivity type is p-type and the second conductivity type is n-type, electrons generated by the dangling bond or the like are recombined with the holes in the p-type photodiode 114 to be extinguished. Holes generated by the dangling bond and the like are discharged to the semiconductor substrate 101 via the p-type well 111. In addition, the first conductive photodiode 114 forms a depletion layer by forming a PN junction with the second conductive photodiode 113. Accordingly, the depletion layer in the diode region 80 is increased to improve the performance of the image sensor.

The floating diffusion layer 119 is disposed in the active region 90 between the first and second gates 107a and 107b. The floating diffusion layer 119 may include a first low concentration diffusion layer 117a and a first high concentration diffusion layer 118a. The floating diffusion layer 119 may be formed of a DDD structure (DDD structure, Double Doped Drain structure) in which the first low concentration diffusion layer 117a surrounds the first high concentration diffusion layer 118a. Alternatively, it may be made of an LDD structure (Lighty Doped Drain). Alternatively, the floating diffusion layer 119 may be formed of only the first low concentration diffusion layer 117a by omitting the first high concentration diffusion layer 118a. The impurity diffusion layer 120 is disposed in the active region 90 at both sides of the third gate 107c. The impurity diffusion layer 120 may include a second low concentration diffusion layer 117b and a second high concentration diffusion layer 118b. The impurity diffusion layer 120 may also form the CD structure or the LED structure. Alternatively, the impurity diffusion layer 120 may be formed only of the second low concentration diffusion layer 117b by omitting the second high concentration diffusion layer 118b. The floating diffusion layer 119 and the impurity diffusion layer 120 are doped with a second conductivity type. The floating diffusion layer 119 and the impurity diffusion layer 120 may be doped at the same concentration. The channel diffusion layer 104 may be disposed on the surface of the active region 90 (the channel region of the first gate) between the floating diffusion layer 119 and the second conductivity type photodiode 113. The channel diffusion layer 104 may be doped with impurities of the second conductivity type same as the photodiode 113 of the second conductivity type and the floating diffusion layer 119. Of course, the channel diffusion layer 104 may be omitted. The floating diffusion layer 119 and the third gate are electrically connected by wiring (not shown).

Blocking patterns 125a are disposed on the photodiodes 113 and 114. The blocking pattern 125a is an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. For example, the blocking pattern 125a may be formed of a silicon nitride film. The blocking pattern 125a protects the photodiodes 113 and 114 from contamination of metal elements that may occur when the metal silicide layer 135 is formed. Accordingly, it is possible to minimize dark defects resulting from contamination of conventional metal elements. The blocking pattern 125a may extend to cover a portion of an upper surface of the first gate 107a. It is preferable that an oxide film 109 is interposed between the blocking pattern 125a and the semiconductor substrate 101. The oxide layer 109 serves to buffer stress between the blocking pattern 125a and the semiconductor substrate 101. The oxide film 109 may be formed of a thermal oxide film. A spacer insulating pattern 127a may be disposed on the blocking pattern 125a. The spacer insulating pattern 127a may be formed of a CVD silicon oxide film.

3 and 4, one side wall of the first gate 107a adjacent to the floating diffusion layer 119, both side walls of the second gate 107b, and both sides of the third gate 107c. Sidewall spacers 129 are disposed on the wall. The sidewall spacers 129 may be formed of stacked first and second spacers 125b and 127b. The first spacer 125b may be formed of the same material as the blocking pattern 125a in an “L” shape. The second spacer 127b has a typical spacer shape and may be made of the same material as the spacer insulating pattern 127a.

The spacer insulation pattern 127a and the second spacer 127b may be omitted. In this case, the sidewall spacers 129 may be in the form of a typical single layer spacer formed of the same material as the blocking pattern 125a.

The silicide prevention pattern 131 covering the spacer insulation pattern 127a, the first gate 107a, and the floating diffusion layer 119 on the blocking pattern 125a is disposed. The silicide prevention pattern 131 may be formed of a CVD silicon oxide layer. The metal silicide layer 135 is disposed on the impurity diffusion layer 120. The metal silicide layer 135 may be formed of a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer. The silicide prevention pattern 131 serves to prevent the metal silicide layer 135 from being formed on the surface of the floating diffusion layer 119. Accordingly, it is possible to prevent the surface of the floating diffusion layer 119 from being damaged. The oxide layer 109 may be interposed between the silicide prevention pattern 131 and the floating diffusion layer 119. A buffer insulating layer 148 and a color ratio control layer 150 sequentially stacked on the silicide prevention pattern 131. , color-ratio control layer). The buffer insulating layer 148 and the color ratio adjusting layer 150 may extend to cover the second and third gates 107b and 107c, the sidewall spacer 129, and the metal silicide layer 135. The color ratio control layer 150 is an insulating layer capable of adjusting color ratios, which are ratios between sensitivity of blue, green, and red, which are three primary colors of colored light, among the light incident on the image sensor. The sensitivity of the colors refers to the degree of response of the image sensor according to the intensity of the incident colors. The color ratio control film 150 is preferably made of a silicon nitride film. The buffer insulating layer 148 may be formed of a CVD silicon oxide layer. The buffer insulating layer 148 may serve to buffer stress between the color ratio adjusting layer 150 and the metal silicide layer 135. In the image sensor, a method of implementing a color of an incident object may include Use an additive color mixture between the three primary colors. In other words, a predetermined filter is disposed on the plurality of pixels having the photodiodes 113 and 114, respectively. The filters may be classified into a blue filter, a green filter, and a red filter. The blue filter polarizes blue in incident light, the green filter polarizes green in incident light, and the red filter polarizes red in incident light. The pixel with the blue filter, the pixel with the green filter and the pixel with the red filter are arranged adjacently. Accordingly, according to the intensity of the polarized colors, the pixels generate electrical signals and transmit the electrical signals to a display means (not shown). The display means reproduces colors from the transmitted electrical signals, and adds and mixes the reproduced colors to display an image.

The color ratio controlled by the color ratio adjusting layer 150 is preferably a blue / green color ratio and a red / green color ratio.

The color ratio control layer 150 may be converted in the color ratio according to the thickness. This will be described with reference to the graph of FIG. 5. The data shown in the graph of FIG. 5 are simulation data. Referring to FIGS. 4 and 5, in the graph of FIG. 5, the x-axis represents the thickness of the color ratio control film 150, and the y-axis represents the color ratio. Curve 200 represents the color ratios of red / green according to the thickness of the color ratio control film 150, and curve 220 represents the color ratios of blue / green according to the thickness of the color ratio control film 150. The curve 210 is green / green color ratios according to the thickness of the color ratio adjusting layer 150, and is 1 for all thicknesses of the color ratio adjusting layer 150. The curve 200 and the curve 220 are changed according to the thickness of the color ratio control layer 150. In this case, it is preferable that the color ratio adjusting layer 150 is formed to have a minimum thickness difference between the color ratio of the red / green and the color ratio of the blue / green. That is, by minimizing the difference between the sensitivity of the pixel for the incident blue and the sensitivity of the pixel for the incident red, it is possible to improve the color sharpness of the image implemented by the image sensor. In the graph of FIG. 10, when the color ratio adjusting layer 150 is 1000 μs, the difference between the curve 200 and the curve 220 is minimal. Of course, since the data of FIG. 10 are simulation data, the thickness of the color ratio control film 150 applied to the actual image sensor may be changed. Referring to FIGS. 3 and 4, the color ratio control film ( At least one interlayer insulating layers 152 and 154 are stacked on the layer 150. In FIG. 4, first and second interlayer insulating films 152 and 154 are illustrated. A wiring (not shown) for electrically connecting the floating diffusion layer 119 and the third gate 107c may be disposed between the first and second interlayer insulating layers 152 and 154. The interlayer dielectric films 152 and 154 may be formed of a CVD silicon oxide film.

The passivation layer 156 is disposed on the interlayer insulating layers 152 and 154. The passivation film 156 is an insulating film that protects the image sensor from contamination sources such as external moisture, and may be formed of a silicon nitride film. FIG. 6 is a graph illustrating a dark defect of the image sensor of FIG. In the graphs, the x-axis represents the number of dark defects and the y-axis represents the number of chips. Referring to FIG. 6, graph A represents the number of dark defect pixels of conventional image sensor chips. A graph B is a graph showing the number of dark defective pixels of the image sensor chips of FIG. 4. The total number of conventional chips and chips according to the present invention is 47, respectively, and the dark defective pixel is defined as a pixel that outputs signal charges of 5 mV / sec or more in the state where no light is incident. The number of pixels of the conventional chip and the number of pixels of the chip according to the present invention are equally 300,000.

As shown in the graph (A), in the conventional chips, all 47 chips have more than 800 dark defect pixels. The largest number of dark-defective pixels is between 18 and 1000 with 1000 to 1200 chips. On the contrary, as shown in the graph (B), the chips according to the present invention all have 47 or fewer dark defective pixels, and the number of chips having 0 to 200 dark defective pixels is 39 as most. many.

As a result, the image sensor according to the present invention can be seen that due to the blocking pattern 125a of Fig. 4, the photodiodes 113 and 114 are protected from the contamination of conventional metal elements. The color ratio characteristics of the sensor will be described with reference to the graph of FIG. 7. FIG. 7 is a graph showing the color ratio characteristics of the image sensor of 4. FIG. In the drawing, the x-axis represents the wavelength of incident light and the y-axis represents the color ratio. Referring to FIGS. 4 and 7, the curves 250a, 250b, and 250c may each include a first pixel and a green filter having a blue filter. The color ratios of the first pixel having and the first pixel having the red filter are shown. Curves 300a, 300b, and 300c represent color ratios of a second pixel having a blue filter, a second pixel having a green filter, and a second pixel having a red filter, respectively. The first pixels have the thicknesses of the thermal oxide film 109, the blocking pattern 125a, the spacer insulation pattern 127a, and the silicide prevention pattern 131 to be 100 μs, 400 μs, 1300 μs, and 1000 μs, respectively. ) Is not provided. The second pixels may include thicknesses of the thermal oxide layer 109, the blocking pattern 125a, the spacer insulation pattern 127a, the silicide prevention pattern 131, and the color ratio control layer 150, respectively. 1300 kHz, 1000 kHz and 1000 kHz. As shown, the color ratio of the highest blue / green of the first pixel is about 0.62 when the wavelength of incident light is 480 nm, and the color ratio of the highest red / green of the first pixel. Is about 1.21 when the wavelength of incident light is 640 nm. In contrast, the color ratio of the highest blue / green of the second pixel is about 0.73 when the wavelength of incident light is 480 nm, and the color ratio of the red / green of the second pixel is about 1 when the wavelength of incident light is 640 nm. to be. That is, the color ratio adjusting layer 150 increases the color ratio of blue / green and decreases the color ratio of red / green, thereby minimizing the difference between the color ratio of blue / green and the color ratio of red / green. As a result, the image sensor having the second pixel provided with the color ratio adjusting layer 150 improves the color clarity of the image. As a result, the image sensor having the above-described structure is made of metal due to the blocking pattern 125a. It is possible to protect the photodiodes 113 and 114 from contamination of the element. Therefore, it is possible to minimize dark defects caused by contamination of conventional metal elements. In addition, the image sensor may improve the color clarity of an image by providing the color ratio adjusting layer 150.

8 to 11 are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 4.

3 and 8, the device isolation layer 103 is formed in a predetermined region of the first conductive semiconductor substrate 101 to define the diode region 80 and the active region 90. The active region 90 is connected to one side of the diode region 80. Impurity ions are selectively implanted into the semiconductor substrate 101 having the device isolation film 103 to form a first conductivity type well 111 surrounding the device isolation film 103. In this case, a well (not shown) may also be formed in the active region 90.

The second conductive photodiode 113, the second conductive photodiode 113, and the semiconductor substrate 101 having a predetermined depth in the diode region 80 from the surface of the semiconductor substrate 101. Photodiode 114 of the first conductivity type is formed between the surfaces of the < RTI ID = 0.0 >

The first conductivity type photodiode 114 may be formed such that one side of the first conductivity type well diode 111 is connected. The channel diffusion layer 104 is formed in the active region 90 adjacent to the diode region 80. A gate insulating film 105 and a gate film 105 are sequentially formed on the entire surface of the substrate 101 having the channel diffusion layer 104, and the gate film and the gate insulating film 105 are successively patterned to sequentially form the active region 90. The first, second and third gates 107a, 107b, and 107c spaced apart from each other by the predetermined intervals are formed. The first gate 107a is formed on the channel diffusion layer 104. A second low concentration diffusion layer 117b in the active region 90 between the first and second gates 107a and 107b and a second low concentration diffusion layer 117b in the active region 90 on both sides of the third gate 107c. ).

The order in which the photodiodes 113 and 114 and the gates 107a, 107b and 107c are formed may be first formed in the photodiodes 113 and 114 and the gates 107a, 107b and 107c. . Alternatively, the gates 107a, 107b, and 107c may be formed first, followed by the photodiodes 113 and 114.

An oxide layer 109 is formed on the active region 90 on both sides of the gates 107a, 107b, and 107c and the surface of the diode region 80. The oxide film 109 may be formed as a thermal oxide film. That is, the oxide film 109 is formed by performing a thermal oxidation process on the semiconductor substrate 101 having the gates 107a, 107b, and 107c. At this time, the thermal oxidation process also serves to heal the etch damage of the gays (107a, 107b, 107c). Accordingly, a thermal oxide film (not shown) may be formed on the surfaces of the gates 107a, 107b, and 107c.

9 and 10, a blocking film 125 and a spacer insulating film on the entire surface of the semiconductor substrate 101 including the oxide film 109, the photodiodes 113 and 114, and the gates 107a, 107b and 107c. (127) are formed in sequence. The blocking film 125 is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. For example, the blocking film 125 may be formed of a silicon nitride film. The spacer insulating layer 127 may be formed of a CVD silicon oxide layer.

The photoresist pattern 130 is formed on the spacer insulating layer 127. The photoresist pattern 130 covers at least the diode region 80. The photoresist pattern 130 may cover a portion of the first gate 107a.

Anisotropically etch the entire surface using the photoresist pattern 130 as a mask to form a blocking pattern 125a and a spacer insulation pattern 127a sequentially stacked below the photoresist pattern 130, and the first low concentration diffusion layer 117a. Sidewall spacers 129 are formed on one sidewall of the first gate 107a and sidewalls of the second and third gates 107b and 107c adjacent to the first gate 107a. The sidewall spacers 129 may be formed of stacked first and second spacers 125b and 127b. The first spacer 125a is a “L” shape as part of the blocking film 125, and the second spacer 127b is a typical spacer shape as part of the spacer insulating film 127. The spacer insulating layer 127 may serve to adjust a lower width of the sidewall spacer 129. That is, by adjusting the thickness of the spacer insulating layer, the sidewall spacer 129 may have a lower width required. The spacer insulating layer 127 may be omitted, and in this case, the sidewall spacer 129 may be formed only as a part of the blocking layer 125.

Subsequently, the photoresist pattern 130 is removed using an ashing process or the like.

Impurity ions are implanted using the blocking pattern 125a, the spacer insulation pattern 127a, and the sidewall spacer 129 as a mask to form a first high concentration diffusion layer 118a and a second high concentration diffusion layer 118b. The first high concentration diffusion layer 118a is formed in the active region 90 between the first and second gates 107a and 107b, and the second high concentration diffusion layer 118b is disposed on both sides of the third gate 107c. Is formed in the active region 90 of. The first low concentration and first high concentration diffusion layers 117a and 118a constitute the floating diffusion layer 119, and the second low concentration and second high concentration diffusion layers 117b and 118b constitute the impurity diffusion layer 120. The floating diffusion layer 119 and the impurity diffusion layer 120 may be formed in a CD structure or an LED structure. Alternatively, the first high concentration diffusion layer 118a and the second high concentration diffusion layer 118b are omitted so that the first low concentration diffusion layer 117a constitutes the floating diffusion layer 119 and the second low concentration diffusion layer 119 117b) may constitute the impurity diffusion layer 120.

A silicide prevention layer (not shown) is formed on an entire surface of the semiconductor substrate 101 including the floating diffusion layer 119 and the impurity diffusion layer 120, and the silicide prevention layer is patterned to form the spacer insulation pattern 127a and the first gate. A silicide prevention pattern 131 is formed to cover 107a and the floating diffusion layer 119. The silicide prevention pattern 131 may be formed of a CVD silicon oxide layer.

Subsequently, a metal film 133 is formed on the entire surface of the semiconductor substrate 101 having the silicide prevention pattern 131. The metal silicide film is formed on the surface of the impurity diffusion layer 120 by performing a metal silicide process on the semiconductor substrate 101 having the metal film 133. The process of depositing the metal film 133 and the metal silicideization process may be performed in-situ.

In the metal silicide forming process, the blocking pattern 125a protects the photodiodes 113 and 114 from contamination of metal elements that may be generated by the metal layer 133 on the silicide prevention pattern 131. As a result, dark defects caused by contamination of conventional metal elements can be minimized. The silicide prevention pattern 131 prevents the metal silicide layer 135 from being formed on the surface of the floating diffusion layer 119. It is preferable that a metal silicide film is not formed on the surface of the floating diffusion layer 119. This is because the performance of the image sensor is improved by preventing the surface of the floating diffusion layer 119 from being damaged by the metal silicide layer 135.

Referring to FIG. 11, an unreacted portion of the metal film 133 is removed by an etching process. Subsequently, a buffer insulating film 148 and a color ratio control film 150 are sequentially formed on the entire surface of the semiconductor substrate 101. The color ratio adjusting layer 150 is formed of an insulating layer that can control color ratios, which are ratios between sensitivity of blue, green, and red, which are three primary colors of colored light, among the light incident on the image sensor. For example, it is preferable to form with a silicon nitride film. The color ratio adjusting layer 150 may be formed to have a thickness that minimizes the difference between the color ratio of blue / green and the color ratio of red / green. The buffer insulating layer 148 may play a role of buffering stress between the color ratio adjusting layer 150 and the metal silicide layer 135. The buffer insulating layer 148 may be omitted. The color ratio adjusting layer 150 may improve color sharpness of an image implemented by an image sensor. At least one interlayer on the color ratio adjusting layer 150 may be improved. The insulating films 152 and 154 are formed. In FIG. 11, first and second interlayer insulating films 152 and 154 are illustrated. Before forming the second interlayer insulating film 154, a wiring (not shown) for electrically connecting the floating diffusion layer 119 and the third gate 107c to the first interlayer insulating film 152 may be formed. Can be. A portion of the wiring penetrates through the first interlayer insulating layer 152, the color ratio adjusting layer 150, the buffer insulating layer 148, the silicide prevention pattern 127a, and the oxide layer 109 and the floating diffusion layer 119. ) Can be accessed. The other part of the wiring may be connected to the third gate 107c by passing through the first interlayer insulating layer 152, the color ratio adjusting layer 150, and the buffer insulating layer 148. The passivation film 156 of FIG. 4 is formed on 154. The passivation film 156 serves to protect the image sensor from contamination sources such as external moisture. The passivation film 156 may be formed of a silicon nitride film.

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As described above, in the image sensor according to the present invention, a blocking pattern is disposed on the photodiodes. The blocking pattern protects the photodiodes from contamination of metal elements. Therefore, it is possible to minimize dark defects caused by conventional metal pollution sources.

In addition, the image sensor according to the present invention includes a color ratio adjusting layer on the photodiodes. The color ratio adjusting film adjusts the color ratio between the sensitivity of blue, green and red, which are three primary colors of color light. In particular, the color ratio adjusting layer may minimize the difference between the color ratio of blue / green and the color ratio of red / green. As a result, color clarity of an image implemented by the image sensor may be improved.

1 is an equivalent circuit diagram illustrating a pixel of a typical CMOS image sensor.

2 is a schematic cross-sectional view for explaining a method of manufacturing a conventional image sensor.

3 is a plan view illustrating an image sensor according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line II ′ of FIG. 3.

FIG. 5 is a simulation graph illustrating color ratios according to thicknesses of color ratio adjusting layers in the image sensor of FIG. 4.

6 is a graph for explaining a dark defect of the image sensor of 4.

7 is a graph illustrating color ratio characteristics of the image sensor of FIG. 4.

8 to 11 are cross-sectional views illustrating a method of manufacturing the image sensor of FIG. 4.

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Claims (59)

An isolation layer formed on the first conductive substrate to define a diode region and an active region; A second conductive photodiode formed in the diode region and having a predetermined depth from the surface of the substrate; A first conductive type photodiode interposed between the second conductive type photodiode and the surface of the substrate; A first gate disposed on the active region adjacent to the diode region; A sidewall spacer disposed on at least one side wall of the first gate facing the diode region, the sidewall spacer comprising a first spacer having a "L" shape and a second spacer disposed on the first spacer; And And a blocking pattern and an insulation pattern, which are sequentially stacked on the diode region, wherein the blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. The method of claim 1, And an oxide film interposed between the blocking pattern and the substrate. The method of claim 1, And a floating diffusion layer formed in an active region of the other side of the first gate opposite to the diode region. The method of claim 3, wherein And a silicide prevention pattern covering the blocking pattern, the first gate, and the floating diffusion layer. The method of claim 1, A second gate and a third gate formed on the active region spaced apart from the first gate by a predetermined distance, and sequentially formed spaced apart from each other; And And a metal silicide layer formed on surfaces of the active region on both sides of the third gate, wherein the sidewall spacers are also disposed on sidewalls of the second and third gates. The method of claim 1, The blocking pattern is an image sensor, characterized in that made of a silicon nitride film. The method of claim 1, And the insulating pattern and the second spacer are made of the same material. An isolation layer formed on the first conductive substrate to define a diode region and an active region; A second conductive photodiode formed in the diode region and having a predetermined depth from the surface of the substrate; A first conductive type photodiode interposed between the second conductive type photodiode and the surface of the substrate; A first gate disposed on the active region adjacent to the diode region; A floating diffusion layer formed in an active region on one side of the first gate opposite to the diode region; A silicide prevention pattern covering the diode region, the first gate and the floating diffusion layer; And An image sensor comprising a color ratio control layer disposed on the silicide prevention pattern. The method of claim 8, And a blocking pattern interposed between the silicide prevention pattern and the second conductive photodiode, wherein the blocking pattern is an insulating film having a lower diffusion coefficient of metal elements than a silicon oxide film. The method of claim 9, And an oxide film interposed between the blocking pattern and the substrate. The method of claim 9, The blocking pattern is an image sensor, characterized in that made of a silicon nitride film. The method of claim 9, An insulation pattern interposed between the blocking pattern and the silicide prevention pattern; And A sidewall spacer disposed on one side wall of the first gate opposite to the diode region, the sidewall spacer including a first spacer having an “L” shape and a second spacer disposed on the first spacer; Image sensor. The method of claim 12, And the insulating pattern and the second spacer are made of the same material. The method of claim 8, A second gate and a third gate formed on the active region spaced apart from the first gate by a predetermined distance, and sequentially formed spaced apart from each other; And And a metal silicide layer formed on surfaces of active regions on both sides of the third gate, wherein the color ratio adjusting layer extends to cover the second gate, the third gate, and the metal silicide layer. The method of claim 14, A blocking pattern and an insulation pattern sequentially stacked between the diode region and the silicide prevention pattern; And And a sidewall spacer disposed on one sidewall of the first gate and the sidewalls of the second and third gates opposite to the diode region, wherein the sidewall spacer is an “L” shaped first spacer and the first sidewall spacer. An image sensor comprising: a second spacer disposed on one spacer. The method of claim 15, And the insulating pattern and the second space are made of the same material. The method of claim 14, And a buffer insulating layer interposed between the color ratio control layer and the silicide prevention pattern, between the color ratio control layer and the metal silicide layer, and between the color ratio control layer and the second and third gates. Image sensor. The method of claim 8, The color ratio control film is an image sensor, characterized in that made of a silicon nitride film. The method of claim 8, At least one interlayer insulating film formed on the color ratio adjusting film; And And a passivation film formed on the interlayer insulating film. An isolation layer formed on the first conductive substrate to define a diode region and an active region; A second conductive photodiode formed in the diode region and having a predetermined depth from the surface of the substrate; A first conductive type photodiode interposed between the second conductive type photodiode and the surface of the substrate; A first gate disposed on the active region adjacent to the diode region; A floating diffusion layer formed in an active region on one side of the first gate opposite to the diode region; A blocking pattern disposed on the diode region; A silicide prevention pattern covering the blocking pattern, the first gate, and the floating diffusion layer; And And a color ratio control film disposed on the silicide prevention pattern, wherein the blocking pattern is an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. The method of claim 20, And an oxide film interposed between the blocking pattern and the substrate. The method of claim 20, The blocking pattern is an image sensor, characterized in that made of a silicon nitride film. The method of claim 20, An insulation pattern interposed between the blocking pattern and the silicide prevention pattern; And A sidewall spacer disposed on one side wall of the first gate opposite to the diode region, the sidewall spacer including a first spacer having an “L” shape and a second spacer disposed on the first spacer; Image sensor. The method of claim 23, And the insulating pattern and the second spacer are made of the same material. The method of claim 20, A second gate and a third gate formed on the active region spaced apart from the first gate by a predetermined distance, and sequentially formed spaced apart from each other; And And a metal silicide layer formed on surfaces of active regions on both sides of the third gate, wherein the color ratio adjusting layer extends to cover the second gate, the third gate, and the metal silicide layer. The method of claim 25, An insulation pattern interposed between the blocking pattern and the silicide prevention pattern; And And a sidewall spacer disposed on one sidewall of the first gate and the sidewalls of the second and third gates opposite to the diode region, wherein the sidewall spacer is an “L” shaped first spacer and the first sidewall spacer. An image sensor comprising: a second spacer disposed on one spacer. The method of claim 26, And the insulating pattern and the second spacer are made of the same material. The method of claim 25, And a buffer insulating layer interposed between the color ratio control layer and the silicide prevention pattern, between the color ratio control layer and the metal silicide layer, and between the color ratio control layer and the second and third gates. Image sensor. The method of claim 20, The color ratio control film is an image sensor, characterized in that made of a silicon nitride film. The method of claim 20, At least one interlayer insulating film formed on the color ratio adjusting film; And And a passivation film formed on the interlayer insulating film. Forming an isolation layer defining a diode region and an active region on the first conductive substrate; Forming a second conductivity type photodiode having a predetermined depth from the surface of the substrate and a photodiode of the first conductivity type interposed between the second conductivity type photodiode and the surface of the substrate in the diode region; step; Forming a first gate on the active region adjacent the diode region; And Forming a blocking pattern and a spacer insulating pattern stacked on the diode region and at least one sidewall spacer formed of at least one sidewall of the first gate opposite to the diode region, wherein the sidewall spacers are formed. The blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film, wherein the first spacer is in an “L” shape, and the second spacer is formed on the first spacer. Method of formation. The method of claim 31, wherein Before forming the blocking pattern, And forming an oxide film on the substrate having the first gate. The method of claim 31, wherein After forming the first gate, And forming a floating diffusion layer in an active region of one side of the first gate opposite to the diode region. The method of claim 31, wherein The method may further include forming a second gate and a third gate disposed on the active region spaced apart from the first gate and spaced apart from each other, and sequentially spaced apart from each other. And formed on both side walls of the gate. The method of claim 34, wherein After forming the blocking pattern, And forming a metal silicide film on surfaces of the active region on both sides of the third gate. The method of claim 31, wherein After forming the first gate, And forming a floating diffusion layer in an active region of one side of the first gate opposite to the second conductivity type photodiode. The method of claim 36, And forming a silicide prevention pattern covering the blocking pattern, the first gate and the floating diffusion layer. The method of claim 31, wherein And the blocking pattern is formed of a silicon nitride film. Forming an isolation layer defining a diode region and an active region on the first conductive substrate; Forming a second conductivity type photodiode having a predetermined depth from the surface of the substrate and a photodiode of the first conductivity type interposed between the second conductivity type photodiode and the surface of the substrate in the diode region; step; Forming a first gate on the active region adjacent the diode region; Forming a floating diffusion layer in an active region of one side of the first gate opposite to the diode region; Forming a silicide prevention pattern covering the diode region, the first gate, and the floating diffusion layer; And And forming a color control film on the entire surface of the substrate having the silicide prevention pattern. The method of claim 39, Before forming the silicide prevention pattern, And forming a blocking pattern on the diode region, wherein the blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. The method of claim 40, Before forming the blocking pattern, And forming an oxide film on the substrate having the first gate. The method of claim 40, And the blocking pattern is formed of a silicon nitride film. The method of claim 40, Forming a sidewall spacer composed of a spacer insulating pattern disposed on the blocking pattern and first and second spacers on one side wall of the first gate opposite to the diode region, wherein the first spacer Is in the form of an “L” and the second spacer is formed on the first spacer. The method of claim 39, And forming a second gate and a third gate disposed on the active region spaced apart from the first gate by a predetermined distance, and sequentially spaced apart from each other. The method of claim 44, Before forming the silicide prevention pattern, A blocking pattern and a spacer insulating pattern stacked on the second conductive photodiode, and sidewall spacers disposed on one side wall of the first gate and opposite side walls of the second and third gates facing the diode region. And forming a sidewall spacer, wherein the sidewall spacer comprises a first spacer having an “L” shape and a second spacer disposed on the first spacer. The method of claim 44, After the silicide prevention pattern is formed, And forming a metal silicide film on surfaces of the active region on both sides of the third gate. The method of claim 39, Before forming the color ratio control film, And forming a buffer insulating film on the entire surface of the substrate having the silicide prevention pattern. The method of claim 39, The color ratio adjusting film is formed of a silicon nitride film. The method of claim 39, After forming the color ratio adjustment film, Forming at least one interlayer insulating film on the entire surface of the substrate; And And forming a passivation film on the interlayer insulating film. Forming an isolation layer defining a diode region and an active region on the first conductive substrate; Forming a second conductivity type photodiode having a predetermined depth from the surface of the substrate and a photodiode of the first conductivity type interposed between the second conductivity type photodiode and the surface of the substrate in the diode region; step; Forming a first gate on the active region adjacent the diode region; Forming a floating diffusion layer in an active region of one side of the first gate opposite to the diode region; Forming a barrier pattern on the diode region; Forming a silicide prevention pattern covering the blocking pattern, the first gate and the floating diffusion layer; And And forming a color ratio control film on the entire surface of the substrate having the silicide prevention pattern, wherein the blocking pattern is formed of an insulating film having a diffusion coefficient of a metal element lower than that of a silicon oxide film. 51. The method of claim 50 wherein Before forming the blocking pattern, And forming an oxide film on the substrate having the first gate. 51. The method of claim 50 wherein And the blocking pattern is formed of a silicon nitride film. 51. The method of claim 50 wherein Forming a sidewall spacer composed of a spacer insulating pattern disposed on the blocking pattern and first and second spacers on one side wall of the first gate opposite to the diode region, wherein the first spacer Is in the form of an “L” and the second spacer is formed on the first spacer. 51. The method of claim 50 wherein And forming a second gate and a third gate disposed on the active region spaced apart from the first gate by a predetermined distance, and sequentially spaced apart from each other. The method of claim 54, wherein Before forming the silicide prevention pattern, Forming a spacer insulating pattern disposed on the blocking pattern and sidewall spacers disposed on one sidewall of the first gate and opposite sidewalls of the second and third gates facing the diode region, And the sidewall spacer comprises a first spacer having an “L” shape and a second spacer disposed on the first spacer. The method of claim 54, wherein After forming the blocking pattern, And forming a metal silicide film on surfaces of the active region on both sides of the third gate. 51. The method of claim 50 wherein Before forming the color ratio control film, And forming a buffer insulating film on the entire surface of the substrate having the silicide prevention pattern. 51. The method of claim 50 wherein The color ratio adjusting film is formed of a silicon nitride film. 51. The method of claim 50 wherein After forming the color ratio adjustment film, Forming at least one interlayer insulating film on the entire surface of the substrate; And And forming a passivation film on the interlayer insulating film.