KR100509816B1 - Method for self planarizating by using a mixed slurry - Google Patents
Method for self planarizating by using a mixed slurry Download PDFInfo
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- KR100509816B1 KR100509816B1 KR10-2002-0032617A KR20020032617A KR100509816B1 KR 100509816 B1 KR100509816 B1 KR 100509816B1 KR 20020032617 A KR20020032617 A KR 20020032617A KR 100509816 B1 KR100509816 B1 KR 100509816B1
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000011268 mixed slurry Substances 0.000 title claims description 3
- 239000002002 slurry Substances 0.000 claims abstract description 49
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000002131 composite material Substances 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000002245 particle Substances 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 39
- 239000010409 thin film Substances 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- -1 and in particular Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000006210 lotion Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
본 발명은 복합 슬러리를 이용한 자기 평탄화 방법에 관한 것으로, 실리콘 기판 상에 산화막을 증착한 후, 증착된 산화막 상에 배리어 메탈(barrier metal) 및 메탈 라인(metal line)을 형성한다. 이후, 형성된 배리어 메탈 및 메탈 라인 상에 층간 절연막을 형성한 후, 형성된 층간 절연막 상에 복합 슬러리를 사용하여 증착 및 식각을 동시에 형성시켜 평탄화 작업을 수행한다. 따라서, 디싱(dishing)을 완전히 방지할 수 있고, 필름에 종류에 관계없이 얇게 증착하고 적게 연마하므로, 생산성을 크게 향상시킬 수 있으며, 층간 절연막 CMP 시에도 엔드 포인트 검출을 사용할 수 있어 안정성 및 신뢰성을 향상시켜 소자의 수율 향상에 기여할 수 있는 효과가 있다. The present invention relates to a self-planarization method using a composite slurry, and after depositing an oxide film on a silicon substrate, a barrier metal and a metal line are formed on the deposited oxide film. Subsequently, after the interlayer insulating film is formed on the formed barrier metal and the metal line, deposition and etching are simultaneously formed using a composite slurry on the formed interlayer insulating film to perform planarization. Therefore, dishing can be completely prevented, and thin films are deposited and polished irrespective of the type, so that productivity can be greatly improved, and end point detection can be used even during the interlayer insulating film CMP, thereby improving stability and reliability. There is an effect that can contribute to improve the yield of the device by improving.
Description
본 발명은 복합 슬러리를 이용한 자기 평탄화 방법에 관한 것으로, 특히 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리와, 입자 크기가 1㎚이하로 매우 작은 슬러리를 복합하여 코팅 및 연마를 동시에 작업하여 평탄도가 뛰어난 층간 절연막을 형성할 수 있도록 하는 방법에 관한 것이다.The present invention relates to a self-planarization method using a composite slurry, and in particular, coating and polishing are simultaneously performed by mixing a slurry having a particle size of about 30 nm to 200 nm and a slurry having a particle size of less than 1 nm. The present invention relates to a method for forming an interlayer insulating film having excellent flatness.
통상적으로, 반도체 소자에는 트랜지스터 및 커패시터 등의 단위소자로 된 셀(cell)들이 반도체 소자의 용량에 따라 제한된 면적 내에 다수개가 집적되어 있는데, 이 셀들은 서로 독립적인 동작 특성을 위해 전기적으로 분리(또는 격리)되어 있다. In general, a plurality of cells of unit devices, such as transistors and capacitors, are integrated in a limited area according to the capacity of the semiconductor device, and the cells are electrically separated (or separated) for independent operation characteristics. It is isolated.
이러한, 셀들 간의 전기적인 분리를 위해 트랜치를 식각하여 절연물질로 재매립하는 트랜치 분리(trench isolation) 공정작업을 수행한다. 또한 반도체 소자는 신호전달을 위해 배선이 필요하며 디바이스의 크기를 줄이기 위해 다층의 배선을 형성하는데, 다층배선은 층간 및 층내에서 배선간을 절연시키기 위해 층간 절연막을 사용한다. In order to electrically isolate the cells, a trench isolation process for etching the trench and refilling it with an insulating material is performed. In addition, semiconductor devices require wiring for signal transmission and form multilayer wiring to reduce the size of the device. The multilayer wiring uses an interlayer insulating film to insulate the wiring between layers and within layers.
즉, 배선간의 전기적인 분리를 위한 층간 절연막 형성 방법에는 배선 상에 상압화학기상증착(Atmospheric Pressure Chemical Vapor Deposition : APCVD) 또는 상압과 저압 사이의 화학 기상 증착(Sub Atmosphere CVD : SACVD) 방법으로 O3-티이오에스(TetraEthy Lorthosilicate : TEOS)를 USG 막을 사용하거나 SOG(Spin On Glass) 방법을 이용한 산화막, 또는 플라즈마 CVD 방법에 의한 PE-TEOS, PE-SiH4, HDP 산화막 등을 증착한다.In other words, the method of forming an interlayer insulating film for electrical separation between wires may be performed by using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method or a Sub Atmosphere CVD (SACVD) method between atmospheric pressure and low pressure. TeOeth (TetraEthy Lorthosilicate: TEOS) is deposited using an USG film, an oxide film using a SOG (Spin On Glass) method, or a PE-TEOS, PE-SiH4, HDP oxide film by plasma CVD.
그러나, 트랜치 분리 방법이나 층간 절연막 형성 공정 방법 모두가 불필요한 막제거나 리풀로우 공정이나 에치백 공적으로 달성할 수 없는 넓은 영역의 글로벌 평탄화 및 저온 평탄화 실현을 위해 씨엠피(Chemical Mechanical Polishing : CMP) 공정이 필수적으로 요구되는 실정이다.However, the CMP process has been implemented to realize global planarization and low temperature planarization in a wide area which cannot be achieved by both the trench isolation method and the interlayer insulating film formation process, which cannot be achieved by retardation process or etchback process. It is a required situation.
한편, 기존의 CMP 방법은 슬러리와 패드의 마찰력을 이용하여 물리 화학적으로 슬러리 내에 존재하는 웨이퍼의 표면을 가공할 때, 단일 패드 상에서 단일 슬러리를 이용하여 단순히 연마를 통해 평탄도를 향상시켰다.On the other hand, the conventional CMP method improves flatness by simply polishing by using a single slurry on a single pad when processing the surface of the wafer physically and chemically present in the slurry using the friction between the slurry and the pad.
그러나, 도 1a를 참조하면, 실리콘 기판(10) 상에 O3 TEOS Oxide, PE-TEOS, PE-SiH4, HDP CVD Oxide, FSG과 SiN의 절연 박막의 산화막(20)을 증착하며, 증착된 산화막(20) 상에 배리어 메탈(barrier metal)(30) 및 메탈 라인(metal line)(40)을 형성하고, 형성된 배리어 메탈(30) 및 메탈 라인(40) 상에 층간 절연막(50)을 형성한다. However, referring to FIG. 1A, an oxide film 20 of an insulating thin film of O 3 TEOS Oxide, PE-TEOS, PE-SiH 4, HDP CVD Oxide, FSG and SiN is deposited on the silicon substrate 10, and the deposited oxide film ( A barrier metal 30 and a metal line 40 are formed on the 20, and an interlayer insulating layer 50 is formed on the formed barrier metal 30 and the metal line 40.
다음으로, 도 1b를 참조하면, 형성된 층간 절연막(50) 상에 입자 크기가 크고 점도가 낮은 일반적인 Silica/Ceria/Alumina 등의 입자를 가진 슬러리를 이용할 경우, 패드의 변형 및 화학 연마에 의해 디싱(dishing)(70)이 발생하여 평탄화가 이루어지지 않으며, 일반적인 슬러리에 의한 화학 연마 웨이퍼의 패턴에 따른 패드의 변형 및 웨이퍼상 패턴 밀도(pattern density) 변환에 의해 마이크로 디싱(micro dishing) 및 에로션(erosion) 현상이 발생하게 되어 그 양을 조절할 수 없고, 이로 인하여 평탄도가 떨어져 두께 차이를 유발시킴과 동시에 각 소자간의 성능 차이를 유발시켜 후속 포토공정에서의 마진이 감소하게 되어 신뢰성 및 수율 감소가 되는 문제점이 있다. Next, referring to FIG. 1B, when using a slurry having particles of general Silica / Ceria / Alumina having a large particle size and a low viscosity on the formed interlayer insulating film 50, dishing may be performed by deformation and chemical polishing of a pad ( No flattening occurs due to dishing (70) and micro dishing and lotion due to deformation of the pad and pattern density conversion on the wafer according to the pattern of the chemically polished wafer by a general slurry. erosion) occurs, and the amount cannot be adjusted, which causes flatness to decrease, and at the same time, causes performance differences between the devices, thereby reducing margins in subsequent photo processes, thereby reducing reliability and yield. There is a problem.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리와, 입자 크기가 1㎚이하로 매우 작은 슬러리를 복합하여 코팅 및 연마를 동시에 일어나게 하여 평탄도와 균일도가 뛰어난 층간 절연막을 형성할 수 있도록 하는 복합 슬러리를 이용한 자기 평탄화 방법을 제공함에 있다. Accordingly, the present invention has been made to solve the above-described problems, the object of the coating and coating a slurry having a particle size of about 30nm to 200nm size, and a slurry of very small particle size of less than 1nm The present invention provides a self-planarization method using a composite slurry that allows simultaneous polishing to form an interlayer insulating film having excellent flatness and uniformity.
상술한 목적을 달성하기 위하여 본 발명에서 복합 슬러리를 이용한 자기 평탄화 방법은 실리콘 기판 상에 산화막을 증착한 후, 증착된 산화막 상에 배리어 메탈(barrier metal) 및 메탈 라인(metal line)을 형성하는 단계; 형성된 배리어 메탈 및 메탈 라인 상에 층간 절연막을 형성한 후, 형성된 층간 절연막 상에 복합 슬러리를 사용하여 증착 및 식각을 동시에 형성시켜 평탄화 작업을 수행하는 단계를 포함하는 것을 특징으로 한다.Self-planarization method using a composite slurry in the present invention in order to achieve the above object is a step of forming a barrier metal (barrier metal) and a metal line on the deposited oxide film after depositing an oxide film on a silicon substrate ; And forming an interlayer insulating film on the formed barrier metal and the metal line, and simultaneously performing deposition and etching using the composite slurry on the formed interlayer insulating film to perform planarization.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 복합 슬러리를 이용한 자기 평탄화를 위한 공정과정을 도시한 도면으로서, 도 2a를 참조하면, 실리콘 기판(10) 상에 산화막(20)을 증착하는데, 산화막(20)은 O3 TEOS Oxide, PE-TEOS, PE-SiH4, HDP CVD Oxide, FSG과 SiN의 절연 박막을 이용하여 증착한다. 2 is a view illustrating a process for self-planarization using a composite slurry according to the present invention. Referring to FIG. 2A, an oxide film 20 is deposited on a silicon substrate 10, and the oxide film 20 is formed of O 3. Deposition is made using an insulating thin film of TEOS oxide, PE-TEOS, PE-SiH4, HDP CVD oxide, FSG and SiN.
이후, 증착된 산화막(20) 상에 배리어 메탈(barrier metal)(30) 및 메탈 라인(metal line)(40)을 형성하고, 형성된 배리어 메탈(30) 및 메탈 라인(40) 상에 층간 절연막(50)을 형성한다.Thereafter, a barrier metal 30 and a metal line 40 are formed on the deposited oxide film 20, and an interlayer insulating layer 30 is formed on the formed barrier metal 30 and the metal line 40. 50).
다음으로, 도 2b를 참조하면, 형성된 층간 절연막(50) 상에 복합 슬러리(80)를 사용하여 증착 및 식각(etch)을 동시에 형성한다. 여기서, 복합 슬러리는 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리와 입자 크기가 1㎚이하로 매우 작고 점도가 높은 슬러리를 혼합시켜 만드는데, 1㎚이하의 슬러리는 층간 절연막 상을 연마하지 않는 반면에 층간 절연막 상을 코팅하는 특징이 있다.Next, referring to FIG. 2B, deposition and etching are simultaneously formed using the composite slurry 80 on the formed interlayer insulating layer 50. Here, the composite slurry is made by mixing a slurry having a particle size of about 30 nm to 200 nm and a slurry having a very small and high viscosity having a particle size of 1 nm or less. A slurry of 1 nm or less does not polish the interlayer insulating film. On the other hand, there is a feature of coating on the interlayer insulating film.
그리고, 1㎚이하의 슬러리는 실리카(Silica)와, 알루미나(Alumina)와, 티타늄 옥사이드(Titanium Oxide)와, 세리아(Ceria)의 혼합 입자로 되어 있고, 혼합된 슬러리의 형태는 SiO2 폴리머 졸(Polymeric Sol)이며, 1㎚이하의 슬러리는 층간 절연막 상에서 낮은 부분을 코팅하여 채움으로써, 웨이퍼의 낮은 부분이 입자가 큰 슬러리에 의해 연마되는 것을 방지하게 되며, 코팅 막은 표면의 단차를 없애 자기 평탄화를 이루면서 연마를 진행하는 것이다. The slurry of 1 nm or less is composed of mixed particles of silica, alumina, titanium oxide, and ceria, and the mixed slurry is formed of SiO 2 polymer sol (Polymeric). Sol), the slurry of less than 1nm is coated by filling the lower portion on the interlayer insulating film, thereby preventing the lower portion of the wafer from being polished by the large slurry, the coating film is self-planarized by eliminating the step difference To proceed polishing.
다음으로, 도 2c를 참조하면, CMP 후의 층간 절연막(60) 상에 디싱(dishing) 현상이 발생하지 않는 평탄화된 막(90)을 형성한다. Next, referring to FIG. 2C, a planarized film 90 in which dishing does not occur is formed on the interlayer insulating film 60 after CMP.
즉, 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리에 의해 코팅된 부분이 연마되더라도 원래의 웨이퍼 표면이 완전히 평탄해질 때까지 계속적으로 코팅을 반복하여 디싱(dishing) 현상을 완전하게 방지할 수 있는 것이다. That is, even if the coated portion is polished by a slurry having a particle size of about 30 nm to 200 nm, the coating is continuously repeated until the original wafer surface is completely flat to completely prevent dishing. It can be.
그리고, 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리와 입자 크기가 1㎚이하로 매우 작고 점도가 높은 슬러리의 비율을 조절하여 웨이퍼 표면의 필름 종류나 모양에 관계없이 평탄한 막을 형성하며, 상술한 바와 같이, 평탄한 막을 형성할 경우, 코팅막에 의해 연마 속도가 급격히 떨어져 엔드 포인트(End Point)를 쉽게 찾을 수 있다.In addition, by controlling the ratio of the slurry having a particle size of about 30 nm to 200 nm and the slurry having a very small and high viscosity having a particle size of 1 nm or less, a flat film is formed regardless of the film type or shape of the wafer surface. As described above, when the flat film is formed, the polishing rate is drastically reduced by the coating film, so that the end point can be easily found.
그러므로, 본 발명은 입자 크기가 30㎚∼200㎚ 정도의 크기를 갖는 슬러리와, 입자 크기가 1㎚이하로 매우 작은 슬러리를 복합하여 코팅 및 연마를 동시에 일어나게 하여 평탄도와 균일도가 뛰어난 층간 절연막을 형성함으로써, 디싱을 완전히 방지할 수 있고, 필름에 종류에 관계없이 얇게 증착하고 적게 연마하므로, 생산성을 크게 향상시킬 수 있으며, 층간 절연막 CMP 시에도 엔드 포인트 검출을 사용할 수 있어 안정성 및 신뢰성을 향상시켜 소자의 수율 향상에 기여할 수 있는 효과가 있다. Therefore, in the present invention, a slurry having a particle size of about 30 nm to 200 nm and a slurry having a particle size of less than 1 nm are mixed to simultaneously coat and polish to form an interlayer insulating film having excellent flatness and uniformity. Thus, dishing can be completely prevented, and thin films are deposited and polished regardless of the type, so that productivity can be greatly improved, and end point detection can be used even during interlayer insulating film CMP, thereby improving stability and reliability. There is an effect that can contribute to improving the yield.
도 1은 종래 슬러리를 이용한 평탄화 공정 과정을 도시한 도면이며,1 is a view showing a planarization process using a conventional slurry,
도 2는 본 발명에 따른 복합 슬러리를 이용한 자기 평탄화 공정 과정을 도시한 도면이다.2 is a view showing a self-planarization process using a composite slurry according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 실리콘 기판 20 : 산화막10 silicon substrate 20 oxide film
30 : 배리어 메탈(barrier metal) 40 : 메탈 라인(metal line)30: barrier metal 40: metal line
50 : 층간 절연막 60 : CMP 후의 층간 절연막50: interlayer insulation film 60: interlayer insulation film after CMP
70 : 디싱(dishing) 80 : 복합 슬러리70 dishing 80 composite slurry
90 : 평탄화된 막90: planarized film
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH088218A (en) * | 1994-04-21 | 1996-01-12 | Sony Corp | Polishing particle and polishing method |
| JPH08302338A (en) * | 1995-05-15 | 1996-11-19 | Sony Corp | Slurry and production of semiconductor device by using same |
| KR20000066941A (en) * | 1999-04-22 | 2000-11-15 | 김영환 | Method For Planarization The Isolation Oxide Layer |
| KR20010063731A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | Method of forming an isolation layer in a semiconductor device |
| JP2001271058A (en) * | 2000-03-27 | 2001-10-02 | Rodel Nitta Co | Method of producing polishing slurry |
| KR20020015282A (en) * | 2000-08-21 | 2002-02-27 | 니시무로 타이죠 | Slurry for chemical mechanical polishing and method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH088218A (en) * | 1994-04-21 | 1996-01-12 | Sony Corp | Polishing particle and polishing method |
| JPH08302338A (en) * | 1995-05-15 | 1996-11-19 | Sony Corp | Slurry and production of semiconductor device by using same |
| KR20000066941A (en) * | 1999-04-22 | 2000-11-15 | 김영환 | Method For Planarization The Isolation Oxide Layer |
| KR20010063731A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | Method of forming an isolation layer in a semiconductor device |
| JP2001271058A (en) * | 2000-03-27 | 2001-10-02 | Rodel Nitta Co | Method of producing polishing slurry |
| KR20020015282A (en) * | 2000-08-21 | 2002-02-27 | 니시무로 타이죠 | Slurry for chemical mechanical polishing and method for manufacturing semiconductor device |
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