JPH088218A - Polishing particle and polishing method - Google Patents

Abstract

PURPOSE:To provide polishing particles and a polishing method having excellent polishing speed and low damaging property, which are used for flattening the stepped surface of an interlayer insulating film, a wiring layer and the like formed in the manufacturing process of a semiconductor device. CONSTITUTION:The stepped surface of a second interlayer insulating film 3, which is formed of a wiring layer 2 on a first interlayer insulating film 1, is flattened by a chemical machine polishing method. Slurry used at this time contains the polishing particles having the structure, wherein particles comprising the first material are covered with the second material having the high hardness. Therefore, the polishing, whose polishing speed is high from the initial period to intermediate period of the polishing and damage is low at the later period of the polishing, can be performed. Thus, the flattening polishing, wherein the throughput and the high quality are compatible, can be accomplished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to abrasive particles and a polishing method, and more specifically, for example, flattening a step of an interlayer insulating film or an electrode wiring on a substrate to be processed which occurs during a manufacturing process of a semiconductor device or the like. The present invention relates to abrasive particles and a polishing method suitable for so-called global planarization.

[0002]

2. Description of the Related Art The degree of integration of semiconductor devices such as LSIs has increased,
As the design rule is scaled down from the sub-half micron level to the quarter micron level, the pattern width of the internal wiring is being reduced. On the other hand, in order to keep the wiring resistance at a low level and prevent the signal propagation delay and various migrations, it is necessary to secure the wiring cross-sectional area.
That is, since the height of the wiring cannot be reduced so much, the aspect ratio of the wiring tends to increase.

In the case of forming a multi-layer wiring structure having such fine wiring as a lower layer, a flattened interlayer insulating film is formed so as to fill the steps and recesses formed by the lower layer wiring to secure a flat surface. It is necessary to repeat the process of forming the upper wiring on top. This is important not only for preventing the disconnection of the upper layer wiring but also for compensating for the decrease in the depth of focus due to the shortening of the exposure light wavelength in the lithography for resist patterning and the increase in the NA of the lens. As an example, KrF with a wavelength of 248 nm
In order to control the line and space of 0.3 μm rule with good controllability by the excimer laser stepper exposure, the surface step of the exposed surface is required to be 0.3 to 0.4 μm or less.

Conventionally, various methods for forming a planarized interlayer insulating film have been developed. For example, monthly Semiconductor World magazine (published by Press Journal) November 1989, No. 7
A review of these forming methods is published on pages 4-95. These forming methods either improve the self-flow characteristics by optimizing the film forming conditions, or improve the reflow shape by heat treatment after the film formation. In either method, there is still room for improvement in terms of flat shape in stepped recesses with wide wiring intervals and prevention of voids.

On the other hand, in recent years, a global flattening method by chemical mechanical polishing (CMP) applying a mirror polishing method for a silicon wafer has been proposed. This chemical mechanical polishing method is considered to be promising as a method capable of surely flattening various steps and protrusions on the substrate once formed by post-treatment.

FIG. 4 is a schematic sectional view showing a general chemical mechanical polishing apparatus. In the figure, a rotating carrier 1
The substrate 11 to be processed, which is attached to No. 2 with the polishing surface facing downward,
This is also set so as to face the platen 13, which is a rotating polishing plate. The slurry 17 is supplied from the slurry supply system 15 to the polishing cloth called the pad 14 on the platen via the nozzle 16, and the substrate 11 to be processed is pressure-bonded to the pad 14 with a predetermined pressure for polishing. At this time, the number of rotations of the carrier 12 and the platen 13 and the adjustment of the rotation axis are optimized, and the polishing particles and p suitable for the substrate to be processed are adjusted.
One of the points is the selection of a slurry having H and the like. As an example, when polishing a silicon oxide-based interlayer insulating film, a so-called CMP in which a chemical reaction and mechanical polishing are used in combination with a KOH aqueous solution in which silica fine particles are suspended is used.
(Chemical-Mechanical Poli
is performed. According to this method, not only the interlayer insulating film can be flattened, but also the wiring layer and the like can be flattened.

[0007]

However, the planarization method using the chemical mechanical polishing method still has problems to be solved for practical use. One of them is that the polishing rate for flattening is low, and it usually takes 10 minutes or more to polish one substrate to be processed. In the planarization of the interlayer insulating film, the silicon oxide-based insulating film or the like deposited thickly by absorbing the step difference of the underlying wiring layer or the like is polished, and therefore improvement of throughput by increasing the polishing rate is an important issue. .

Another problem is the problem of a damage layer induced on the polished surface of the substrate to be processed. That is, when the rotation speed of the carrier and the platen is increased or the polishing pressure is increased with the intention of increasing the polishing rate, an amorphous layer or an altered layer may be formed on the polished surface. These damage layers also enter when the hardness of the abrasive particles is too high. Any incompatibility of these polishing conditions leads to deterioration of device characteristics such as withstand voltage and resistivity of the semiconductor device.

In order to solve these problems, a part of the stepped convex portion in the thickness direction of the interlayer insulating film is previously removed by isotropic etching using a resist pattern as a mask.
A method of performing chemical mechanical polishing after this is disclosed in US Pat.
4,459. This method is shown in Figure 5.
Will be described with reference to.

A plurality of wiring layers 2 having different line widths are patterned on a first interlayer insulating film 1 on a semiconductor substrate (not shown), and a second interlayer insulating film 3 is thickly formed. The second interlayer insulating film 3 has a mixture of large-area stepped protrusions and narrow-area stepped protrusions. If polishing is performed in this state, the polishing speed of a particularly large-area stepped protrusion is reduced, which is satisfactory. Global flattening cannot be achieved. Therefore, as shown in FIG. 5A, a resist pattern 4 is formed in the stepped concave portion, and as shown in FIG. 5B, a part of the stepped convex portion in the thickness direction of the interlayer insulating film is removed. When the resist pattern 4 is removed, the second interlayer insulating film 3 is removed as shown in FIG.
Leaves only small protrusions. Since the volume of the minute protrusions is almost uniform, the polishing time can be shortened by polishing from the state shown in FIG. 5 (c), and the surface shape becomes extremely small as shown in FIG. 5 (d). Excellent flatness can be achieved.

According to this conventional technique, the polishing time is shortened, but the processes of forming a resist pattern, etching and removing the resist pattern are required to be added, and there is a problem that the throughput of the entire planarization process is lowered. appear.

[0012] Therefore, an object of the present invention is to provide a polishing particle and a polishing method, which have a higher polishing rate than in the past and do not damage the substrate to be processed.

Another object of the present invention is to achieve the above object by a single polishing process without complicating the process.

[0014]

The abrasive particles of the present invention are proposed to achieve the above-mentioned object, and have a structure in which the surface of the particles made of the first material is covered with the second material. Is. The hardness of the first material is preferably lower than the hardness of the second material. Further, it is desirable that the material is contamination-free with respect to the substrate to be processed. A specific example of such a material is a combination in which the surface of silica particles is coated with alumina or silicon carbide.

Further, the polishing method of the present invention is to polish a substrate to be processed using the slurry containing the above-mentioned polishing particles. It is desirable to employ a chemical mechanical polishing method in which a basic or acidic aqueous solution is adopted as a solvent for the slurry and a chemical reaction is also used.

[0016]

The point of the present invention is to use abrasive particles, which are conventionally made of a single material, as a double structure, and the surface of the particles made of the first material is coated with the second material. That is. Another point is to polish a substrate to be processed using a slurry containing abrasive particles having this structure. According to the polishing method using such abrasive particles, the polishing with the second material of the outer core is preferentially performed in the initial or middle stages of polishing, and the polishing with the first material of the inner core is performed in the latter stage of polishing. . That is, as the polishing progresses, the second material of the outer core is worn or peeled off, and the abrasive particles made of the first material of the inner core are exposed.

At this time, if the abrasive grain structure is such that the hardness of the second material of the outer core is high and the hardness of the first material of the inner core is lower than this, high-speed polishing in the initial or middle stage of polishing and the latter stage of polishing are performed. It is possible to achieve polishing at low speed but with low damage.

The layer thickness of the coating layer of the second material of the outer core is set in accordance with the surface material and the polishing thickness of the substrate to be polished, which is the object of polishing, and the polishing conditions, so that high quality and high throughput can be obtained. Polishing is possible. That is, the desired high-speed and low-damage polishing can be achieved by setting a single polishing condition, and it is not necessary to set the slurry composition and polishing conditions in multiple stages during the polishing process.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. First, the abrasive particles of the present invention will be described before starting the description of the actual polishing process.

FIG. 3 is a schematic view showing abrasive particles 6 according to the present invention. FIG. 3A shows a configuration example in which an aggregate in which a plurality of particles 7 made of a first material is lightly sintered is covered with a second material 8 so as to be surrounded by the aggregate. In this embodiment, the first material is silica (SiO ₂ ) or silica containing impurities, and the particle size thereof is, for example, 1 to 100 nm, preferably 2 to 50 nm. The second material of the outer core is alumina (Al ₂ O ₃ ) in this embodiment, and the layer thickness thereof is, for example, 1 to 100 nm, preferably 2 to 50 nm. Although the abrasive particles 6 in the figure are substantially spherical, they may be indefinite. Further, in the figure, the abrasive particles 6 have a structure in which a plurality of the first particles 7 are included, but the structure may be such that only one first particle 7 is covered with the second material.

The abrasive particles having the above structure can be produced by the following steps. That is, commercially available silica particles are suspended and dispersed in water to obtain secondary silica particles which are aggregates of silica particles. The size of the aggregate can be controlled by the dispersion conditions of the silica particles, specifically, the stirring conditions of the disperser, the pH of the medium, the presence or absence of the dispersant, and the type thereof. A predetermined amount of aluminum chloride (AlCl ₃ ) is dissolved therein, and an aqueous solution of potassium hydroxide (KOH) is further added to add aluminum hydroxide [Al (OH) ₃ or Al (OH) ₃ · nH.
₂ O or AlO (OH)] coating is formed on the surface of silica particles. Next, the secondary silica particles coated with aluminum hydroxide are filtered, washed with water and dried to obtain 900
Sintered in a non-reducing atmosphere of about ℃ ~ 1500 ℃,
The abrasive particles shown in (a) are obtained. The reason why the sintering temperature varies is that it corresponds to the difference in the impurity concentration in the silica particles and the particle size. That is, the temperature at which the silica particles 7 melt at the contact surface with each other to form a bridge and form an aggregate is selected. The melting point of silica (SiO ₂ ) is 1610 ° C., but that containing impurities lowers the melting point. Further, the sintering temperature of the fine particles is generally lower than the melting point of the bulk material.

On the other hand, aluminum hydroxide has a γ
It becomes α-Al ₂ O ₃ via -Al ₂ O ₃ . The melting point of alumina (α-Al ₂ O ₃ ) is 2015 ° C., but the transition temperature from the aluminum hydroxide thin film is much lower than this.

In the abrasive particles 6 shown in FIG. 3A, the alumina of the outer core is worn or peeled off as the polishing progresses, and the silica particles of the inner core are exposed. Since the silica particle aggregate is only weakly sintered due to the bridge, it is immediately re-dispersed in the original silica particles as shown in FIG. 3 (b), and polishing by the silica particles is performed. The hardness of pure silica is 7 and the hardness of alumina is 9.

The abrasive particles according to the present invention can be prepared by using TMA (Trimethyl Alum) in addition to the wet precipitation method as described above.
CV using an organoaluminum compound such as
It can also be formed by a dry method such as the D method or various PVD methods. The method of forming a film on powder such as silica particles is
A general device may be adopted as the fluidized bed system.

Example 1 This example is an example in which the present invention is used for flattening an interlayer insulating film formed on an Al-based metal wiring, which is shown in FIG.
This will be described with reference to (b). It should be noted that parts having the same functions as those shown in FIGS. 5A to 5D, which are used to explain the conventional chemical mechanical polishing method, are designated by the same reference numerals.

First, as shown in FIG. 1A, a first interlayer insulating film 1 made of SiO ₂ and a wiring layer 2 made of Al-based metal are formed on a semiconductor substrate made of Si or the like (not shown). .
The wiring layer 2 has a distribution in pattern density and wiring width. The line and space of the dense portion of the wiring layer 2 is 0.35 μm, for example, and that of the sparse portion is 2.0 μm. The height of each wiring layer is 0.5 μm. Next, the second interlayer insulating film 3 is formed thick by, for example, plasma CVD or low pressure CVD to have a thickness of 0.8 μm in the flat portion.
The sample thus formed is used as a substrate to be processed.

Next, using the general chemical mechanical polishing apparatus shown in FIG. 4, the above-mentioned substrate 11 to be processed is adhered downward to the carrier 12 by using wax or the like. The insulating film 3 was subjected to chemical mechanical polishing. The slurry used was the above-mentioned alumina-coated silica particles of the present invention suspended in a basic solvent of KOH / ethanol / water system. Platen rotation speed 50 rpm Carrier rotation speed 17 rpm Polishing pressure 8 psi Pad temperature 30-40 ° C. Slurry flow rate 225 ml / min

As a result, as shown in FIG. 1B, the second interlayer insulating film 3 was flattened by chemical mechanical polishing. The above polishing conditions are common as polishing conditions for the interlayer insulating film. However, by adopting the abrasive particles of the present invention, a polishing rate about 3 times that of the conventional method using only silica particles was obtained, and the damage on the flattened surface was 1/10 or less. The polishing of the second interlayer insulating film is performed on the wiring layer by 0.2 μ as an example.
The process is completed with the thickness of m left, and if necessary, an insulating film is further stacked by plasma CVD, low pressure CVD or the like to form an upper layer wiring.

Embodiment 2 This embodiment is an example in which a W layer deposited by blanket CVD is polished and W is embedded in a connection hole in a contact plug forming process of a multilayer wiring.
This will be described with reference to (a) and (b).

First, as shown in FIG. 1A, a first interlayer insulating film 1 such as SiO ₂ and a wiring layer 2 made of Al-based metal or the like are formed on a semiconductor substrate (not shown) such as Si. .
Next, a _second interlayer insulating film 3 made of SiO ₂ or the like is formed,
A connection hole facing the wiring layer 2 is opened here. The opening diameter of the connection hole is 0.35 μm and the depth is 0.7 μm, for example. After that, the refractory metal layer 5 made of W is formed by general blanket CVD so as to fill the connection hole. The refractory metal layer 5 has a thickness of, for example, 0.5 μm on the flat portion of the second interlayer insulating film 3. If necessary, T
The refractory metal layer 5 may be formed after forming an adhesion layer such as i, TiN or TiON or a barrier metal layer by sputtering or the like. The refractory metal layer grows as a columnar structure, and its surface is rough. In addition, a recess called a seam, which is a seam of the growth surface, is seen above the connection hole. The sample thus formed is used as a substrate to be processed.

Next, using the chemical mechanical polishing apparatus also shown in FIG. 2, the above-mentioned substrate 11 to be processed is adhered downward to the carrier 12 using wax or the like, and as an example, the refractory metal layer 5 is formed under the following conditions. Chemical mechanical polishing was performed. The slurry used was a suspension of the above-mentioned alumina-coated silica particles in a dilute hydrofluoric acid / ethanol / water weak acidic solvent. Platen rotation speed 50 rpm Carrier rotation speed 17 rpm Polishing pressure 10 psi Pad temperature 30-40 ° C. Slurry flow rate 225 ml / min

As a result, as shown in FIG. 1 (b), the gentle protrusions in the vicinity of the contact holes of the refractory metal layer 5 and the second interlayer insulating film 3 are flattened by chemical mechanical polishing, and the buried plug of W is plugged. Was formed. The above polishing conditions are common as the polishing conditions for the refractory metal layer such as W. However, by adopting the polishing particles of the present invention, a polishing rate about three times that of the conventional method using only silica particles was achieved, and the process deterioration of the W plug and the second interlayer insulating film 3 was 1/10 or less. . After that, an Al-based metal or the like is formed by sputtering to form an upper wiring layer. Although the refractory metal layer 5 is polished by blanket CVD in this embodiment, the refractory metal layer may be polished by selective CVD. Particularly, when selective growth is simultaneously performed in a plurality of connection holes having different depths, good results are obtained when removing an overgrowth portion called a nail head of a shallow connection hole portion. According to this embodiment, since the upper layer wiring is formed on the flat surface, highly accurate patterning is possible. Further, since the W plug is not damaged, a low resistance contact plug can be obtained.

Although the present invention has been described with reference to the two examples, the present invention is not limited to these examples.

Although SiO ₂ has been exemplified as the first material constituting the inner core of the polishing particles, SiO containing impurities such as P and B is used.
₂ or other material may be used. The second material forming the outer core is Sialon (SiAl _x O _{y) in} addition to Al ₂ O _3.
N _z , hardness 8), Spinel (MgAlO ₄ , hardness 7.5-8), Zircon (ZrSiO ₄ , hardness 7.
5), SiC (hardness 9.5), diamond-like carbon (hardness 10) and the like, a material having a hardness higher than that of the first inner core material can be selected and used.

The flattening of the interlayer insulating film made of SiO ₂ and the refractory metal layer such as W as the substrate to be processed has been exemplified, but silicate glass such as PSG, BSG, BPSG and AsSG, SiON and Si ₃ N _{4 are used.} It may be flattening of the insulating film. Further, it may be applied to isolation between elements and flattening by embedding an insulating material, a dielectric material or Poly-Si in a trench forming a capacitor cell of DRAM.
Furthermore, an Al-based metal layer as a wiring layer, Poly-Si
The layer, the refractory metal layer other than W, the refractory metal silicide layer, or the like may be used for planarization. The chemical mechanical polishing apparatus of the present invention can also be used for mirror polishing of semiconductor substrates such as Si and GaAs that do not undergo a chemical reaction.
In addition to the semiconductor process, it can also be used for various optical devices such as an optical waveguide and a flattening process of a thin film magnetic head.

As the solvent, a combination of KOH / ethanol / water-based solvent and dilute hydrofluoric acid / ethanol / water-based solvent has been exemplified. Basic solvents such as hydrazine and various organic amines, and acidic solvents such as buffered hydrofluoric acid (BHF). May be selected according to the substrate to be processed. H ₃ PO ₄ / H ₂ O ₂ -based solvent is suitable for flattening the Al-based metal layer, and H ₂ O ₂ / KOH-based solvent is suitable for flattening the W layer in addition to the above-mentioned solvent. .

[0037]

As is apparent from the above description, according to the present invention, a slurry containing abrasive particles having a structure in which the surface of the particle made of the first material is covered with the second material having a hardness higher than that of the particle is used. Polishing or chemical mechanical polishing makes it possible to achieve both high-speed polishing from the initial stage to the middle stage of polishing and low-damage polishing in the latter stage of polishing. This effect can be achieved in one step by using an ordinary polishing apparatus, because it is not necessary to set the polishing conditions in multiple steps or to change the polishing particle and slurry concentrations while performing multi-step polishing.

By virtue of the above effects, the improvement of the throughput and the reduction of damage in the surface flattening process of the semiconductor device in which the high level difference is generated by the adoption of the multi-layer wiring structure are achieved at the same time, and the semiconductor in which the present invention is highly integrated. The effect of contributing to the manufacturing process of devices and the like is extremely large.

[Brief description of drawings]

1A and 1B are schematic cross-sectional views illustrating a polishing method according to a first embodiment of the present invention, where FIG. 1A is a state in which a step is formed in an interlayer insulating film formed on a plurality of wiring layers, and FIG. This is a state in which the interlayer insulating film is flattened.

FIG. 2 is a schematic cross-sectional view illustrating a polishing method according to a second embodiment of the present invention, in which (a) shows a refractory metal layer formed on a second interlayer insulating film having a connection hole facing a wiring layer. State,
(B) is a state in which the refractory metal layer is flattened.

FIG. 3 is a schematic view showing abrasive particles of the present invention, (a)
Shows a state in which the particles made of the first material are coated with the second material, and FIG. 9B shows a state in which the particles made of the first material are exposed as the polishing progresses.

FIG. 4 is a schematic sectional view showing a general chemical mechanical polishing apparatus.

5A and 5B are schematic cross-sectional views illustrating a conventional chemical mechanical polishing method, in which FIG. 5A is a state in which a step is formed in an interlayer insulating film formed on a plurality of wiring layers, and FIG. A state where a resist pattern is formed on the stepped concave portion, (c) a state where the stepped convex portion of the interlayer insulating film is removed by etching using the resist pattern as a mask, and (d) a state where the interlayer insulating film is planarized by chemical mechanical polishing. Is.

[Explanation of symbols]

 1 First Interlayer Insulating Film 2 Wiring Layer 3 Second Interlayer Insulating Film 4 Resist Pattern 5 Refractory Metal Layer 6 Abrasive Particles 7 Particles Made of First Material 8 Second Material 11 Target Substrate 12 Carrier 13 Platen 14 Pad 15 Slurry supply system 16 Nozzle 17 Slurry

Claims (4)

[Claims] 1. Abrasive particles having a structure in which particles made of a first material are coated with a second material. 2. The abrasive particles according to claim 1, wherein the hardness of the first material is smaller than the hardness of the second material. 3. In a polishing method for flattening a surface of a substrate to be processed having a step, particles made of a first material are mixed with a second material.
A polishing method comprising polishing with a slurry containing abrasive particles having a structure coated with the above material. 4. In a polishing method for flattening a surface of a substrate to be processed having a step, particles made of a first material are mixed with a second material.
A chemical mechanical polishing method using a slurry containing abrasive particles having a structure coated with the above material.