KR100495879B1 - Multi device controll systme and controlling method thereof - Google Patents

Abstract

The present invention relates to a multi-device control system and a control method thereof. In the conventional multi-device control system, a master generates a control signal for operation of each slave and provides it to each slave, and each slave corresponds to a corresponding time. Since the data is exchanged 1: 1 with the master in the slot section, when a device having a master authority fails, communication between all slaves dependent on the master becomes impossible. This is impossible and the communication channel is limited.

Accordingly, when the failure of the device performing the master operation is detected, the present invention enables the device performing the slave operation to perform the master operation, so that the system can operate normally even when the device having the master authority has failed. On the other hand, it provides a multi-device control system and a control method that can provide a diversified communication channel by enabling data transmission and reception between each device.

Description

Multi-device control system and its control method {MULTI DEVICE CONTROLL SYSTME AND CONTROLLING METHOD THEREOF}

The present invention relates to a multi-device control system and a method of controlling the same. In particular, when a plurality of devices constituting the system have a function as a master and a slave, and a device fails to perform a master operation, data transmission and reception between the devices can be performed. The present invention relates to a possible multi-device control system and a control method thereof.

In a multi-device system composed of a plurality of processor devices, a device performing a master function applies a control signal to a device serving as a slave function, thereby enabling signal transmission and reception between the master device and the slave device.

1 is a schematic configuration diagram of a conventional multi-device control system. As shown in FIG. 1, the conventional multi-device control system includes a master 1 and a plurality of slaves 7 controlled by the master 1, and outputs a signal from the master 1 to the slave 7. And a second bus 5 for receiving a signal output from each slave 7.

The master 1 generates a control signal such as a frame synchronization signal FRS, a clock signal CLK, and timeslot information for data transmission and reception with each slave 7, and generates the generated control signal and the transmission data to be transmitted ( TxD) is provided to each slave 7 via the first bus 3.

The plurality of slaves 7 connected to the master 1 check their time slot positions and the number of timeslots through the time slot information received from the master 1. The slave 7 checks its time slot position based on the frame synchronization signal transmitted from the master 1, and receives and processes the transmission data TxD of the corresponding time slot position.

On the other hand, when data is transmitted from the slave 7 side to the master 1, the slave 7 provides the received data RxD to the master 1 side through the second bus 5 in the corresponding timeslot section. do. The master 1 receives the data RxD transmitted from the slave 7 via the second bus 5 in accordance with the timeslots assigned to each slave 7.

Here, the master 1 and the slave 7 check whether or not the received data is data to be processed according to the processor address assigned to them to process or discard the data.

The control flow of the conventional multi-device control system having such a configuration is as shown in FIG.

When the driving of the multi-device system starts, the master 1 generates a control signal such as a frame synchronization signal FRS, a clock signal CLK, and timeslot information for data transmission and reception with each slave 7. Provided to the plurality of slaves 7 through (3) (S1).

Each slave 7 that has received the timeslot information from the master 1 checks the timeslot position assigned to itself through the received timeslot information (S3).

The master 1 transmits a frame synchronization signal and a clock signal to the first bus 3 together with the transmission data TxD for transmission to the slave 7 (S5).

Each slave 7 checks the timeslot based on the frame synchronization signal and the clock signal from the master 1, and receives the data TxD of the timeslot section allocated thereto (S7).

In addition, each slave 7 may transmit data RxD in the timeslot section allocated to it (S9).

As described above, in the conventional multi-device control system, the master 1 generates a control signal for the operation of each slave 7 and provides it to each slave 7, where each slave 7 is a master 1. Data is transmitted and received according to the control signal provided from the side. In this case, since each slave 7 transmits or receives data only in a time slot section assigned to itself, each slave 7 can exchange data 1: 1 with the master 1 in the corresponding time slot section. have.

However, such a conventional multi-device control system has a problem in that when a device having a master's authority fails, communication of all slaves dependent on the master becomes impossible.

In addition, all the slaves can exchange data with the master, but communication between each slave is impossible, so there is a disadvantage in that the communication channel is limited.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a plurality of devices capable of transmitting and receiving data between devices even when a device in which a plurality of devices constituting the system have a function of a master and a slave to perform a master operation fails. Its purpose is to provide a control system and its control method.

A multi-device control system according to the present invention for achieving the above object, and a data bus for transmitting a signal for each device; A data transmitting / receiving unit for controlling data transmitted / received through the data bus; A buffer unit for controlling each control signal from the data bus; A data processor for processing data transmitted and received through the data transmitter and receiver and generating various control signals for signal transmission and reception; And an input / output control unit for generating a control signal for controlling the buffer unit and the data transmission / reception unit according to the control signal received through the buffer unit.

Here, the input / output controller divides a clock signal, which is a control signal received from the data bus, according to a predetermined priority, and generates a reference clock signal for determining whether a clock signal exists on the data bus. A dispensing part; A frame error detection unit for comparing the sameness between the frame synchronization signal, which is a control signal received from the data bus, and the frame synchronization signal generated through the data processing unit, to determine whether the control signal is supplied to the data bus; In order to determine whether the control signal is supplied to the data bus, an operation error detection unit for comparing an identity of an active signal, which is a control signal received from the data bus, with an internal active signal generated through the data processing unit, may be included. Do.

The frame error detection unit includes a delay unit for delaying a frame synchronization signal received from the data bus in a predetermined frame unit; It is possible to include a signal comparison unit for comparing the phase difference between the frame synchronization signal delayed through the delay unit and the frame synchronization signal received in real time from the data bus.

The operation error detection unit may include a signal comparison unit for comparing a phase difference between the active signal received from the data bus through the buffer unit and an internal active signal generated through the data processing unit.

On the other hand, the above object is according to another field of the invention, the step of receiving a control signal, such as a clock signal, a frame synchronization signal, an active signal from the data bus; Determining whether a failure of the received control signal occurs; If it is determined that a failure occurs in the control signal, blocking the control signal transmission of the device currently supplying the control signal; It is also achieved by a multi-device control method comprising the step of supplying a control signal to the data bus via another device.

Hereinafter, a multi-device control system and a control method thereof according to a preferred embodiment of the present invention with reference to the accompanying drawings will be described in detail.

3 is a schematic diagram of a multi-device control system according to the present invention. As shown in FIG. 3, the system is composed of a plurality of devices 20 which are given a predetermined priority, and a bus 10 for signal transmission between the devices 20.

The bus 10 transmits control signals such as a frame synchronization signal FRS and a clock signal CLK, which are input to each device 20, and transmit / receive data TRxD transmitted and received from each device 20. That is, in this system, signals and data are exchanged between the devices 20 using a single bus 10.

Each device 20 connected to the bus 10 is given a predetermined priority, and the device 20 having the highest priority among the devices 20 frames the other device 20 via the bus 10. A control signal such as a synchronization signal FRS, a clock signal CLK, and timeslot information is provided. Here, when a failure occurs in the device 20 providing the control signal, the device 20 having the highest priority among the remaining devices 20 provides the control signal according to the priority given to each device 20.

On the other hand, each device 20 determines the time slot section assigned to itself based on the time slot information provided through the bus 10, and transmits data to the bus 10 in the corresponding time slot section and other timeslots. In the section, data is received from the bus 10.

An internal configuration of the device 20 performing such a task will be described in detail with reference to FIGS. 4 to 7.

4 is a control block diagram of a device 20 constituting a multi-device control system according to the present invention. The device 20 includes a buffer unit 28 that intercepts control signals transmitted and received via the bus 10, a data transmission and reception unit 26 that intercepts data transmitted and received via the bus 10, and data transmitted and received. The data processor 22 generates various control signals for signal transmission and reception, and controls the operations of the buffer unit 28 and the data transmission / reception unit 26 based on the control signals received through the buffer unit 28. And an input / output control unit 30 for applying the control signals CONT_0, CONT_1, and CONT_2.

The data processing unit 22 converts the transmission target data into transmission data TD in a form that can be output to the bus 10 and processes the received data RD received from the bus 10. Here, it is preferable that the data processor 22 processes the transmission / reception data in a time division multiple manner by using a communication processor for time division multiplex processing.

The buffer unit 28 includes a plurality of buffer units interposed on signal lines of respective control signals inputted and outputted to the input / output control unit 30 to control each control signal. The buffer unit is interposed in the frame synchronization signal (FRS) line, the clock (CLK) line, and the active signal (ACT) line, respectively, and is activated in the forward or reverse direction according to the control signals CONT_0 and CONT_2 from the input / output control unit 30. You can control the entry and exit of signals. The buffer unit 28a placed on the frame synchronization signal (FRS) line and the buffer unit 28b placed on the clock line are controlled according to the CONT_0 signal, and the buffer unit 28c placed on the active signal line is connected to the CONT_2 signal. Are controlled accordingly. Here, the buffer unit has a transmit buffer activated when the control signals CONT_0 and CONT_2 are high and the receive buffer is activated when the low signal.

The internal structure of the data transmission / reception unit 26 is as shown in FIG. As shown in FIG. 5, a buffer unit 27 for intermittent transmission / reception of data to and from the bus 10 and a data transmission / reception control unit 29 for transmitting and receiving data through the buffer unit are included.

The buffer unit 27 inherent in the data transmission / reception unit 26 is activated in the forward or reverse direction according to the CONT_1 signal applied from the input / output control unit 30. The data transmission / reception control unit 29 transmits the transmission data TD provided from the data processing unit 22 to the bus 10 through the buffer unit 27 in accordance with the CONT_1 signal applied from the input / output control unit 30 and the bus 10. ) Receives the transmission / reception data TRxD and transmits the reception data RD to the data processing unit 22. Here, when the CONT_1 signal is in the 'High' state, the buffer unit 27 transmits the TD data and the data transmission / reception control unit 29 transmits the TD data. When the CONT_1 signal is low, the buffer unit 27 The reception buffer is activated and the data transmission / reception control unit 29 provides the data processing unit 22 with the reception data RD of the transmission / reception data TRxD received from the bus 10.

The input / output controller 30 applies a control signal to the data transmission / reception unit 26 and the buffer unit 28 based on the control signal input from the bus 10 to transmit / receive data or transmit the control signal to another device 20. Can provide them.

The input / output controller 30 checks the timeslot based on the frame synchronization signal FRS and the clock signal CLK received from the bus 10 during initial driving. The input / output control unit 30 applies CONT_1 = High signal to the buffer unit 27 and the data transmission / reception control unit 29 of the data transmission / reception unit 26 only for the allocated time slot period. As a result, the buffer unit 27 is activated as an outgoing buffer, and the data transmission / reception control unit 29 transmits data. On the other hand, in a time slot section in which no use is allowed, the input / output control unit 30 sends the CONT_1 = Low signal to the data transmission / reception unit 26 to maintain the buffer unit 27 in the reception buffer state, thereby providing a buffer unit ( The reception data RD of the transmission / reception data TRxD received through the operation 27 is received. That is, when not transmitting data, the data reception state is always maintained, and when the other device 20 transmits the transmission / reception data TRxD, it can be received.

The input / output controller 30 operates as a master based on the division unit 35 for dividing the clock signal CLK received from the bus 10 and the active signal provided through the bus 10 during operation. On the basis of the frame error signal (FRS) provided through the bus 10 and the operation error detection unit 32 that detects whether or not the device 20 has failed, whether the device 20 operating as a master has failed. It further comprises a frame error detection unit 34 for detecting.

The input / output controller 30 receives the clock signal CLK from the bus 10 during initial driving, and based on this, the input / output controller 30 receives the clock signal CLK and the frame synchronization signal FRS generated in the device 20 based on the external bus. 10) It is determined whether to provide. Here, the input / output controller 30 divides the initially received clock signal CLK according to a preset method through the divider 35, and has a reference clock signal having a longer period than the initially input clock signal CLK. CLK_R). When the clock signal CLK is not received from the bus 10 for one period of the reference clock signal CLK_R, the input / output controller 30 transmits the clock signal CLK to the bus 10 to send another device 20. ) Provides a clock signal CLK.

Here, since the input / output controller 30 divides the clock signal CLK at different ratios through the divider 35 according to the priority given to each device 20, each device 20 has a different reference clock. It has a signal CLK_R. For example, first, if the highest ranked device 20 and to one-half the clock generates a reference clock, and the second priority ranking device 20 is a ^second half clock generates a reference clock, first The device 20 having the rank N ranks the clock 1/2 ^N to generate a reference clock. Therefore, since the higher priority device 20 has a reference clock with a shorter period than other devices 20, when the clock signal CLK is not detected from the bus 10, the highest priority device ( 20 first detects this and outputs the clock signal CLK and the frame synchronization signal FRS to the outside so as to have the possession of the bus 10.

6 is a signal state diagram for the operation of the operation error detection unit 32 controlled by the input and output control unit 30. The operation error detector 32 receives the active signal ACT_O received through the buffer unit 28c which intercepts the transmission and reception of the active signal ACT and is delayed through the delay unit 31 and under the control of the input / output control unit 30. The generated active signal ACT_I is compared to determine whether the device 20 is in a normal state.

If the clock signal CLK is not detected on the bus 10, the input / output controller 30 checks the state of the device 20 through the operation error detector 32. If the clock signal CLK is not detected, the input / output controller 30 provides the active signal ACT_I to the operation error detector 32. The operation error detection unit 32 latches the active signal ACT_O received from the bus 10 by one frame sync period through the delay unit 31 to compare the generated active signal ACT_I.

The operation error detection unit 32 determines whether the active signal ACT_O received from the bus 10 and the active signal ACT_I generated in the device 20 are the same, and has the right to occupy the current bus 10. Check whether the device 20 is itself. The operation error detection unit 32 may verify the identity between the active signal ACT_O and the active signal ACT_I generated in the device 20 by an exclusive OR operation. As a result of the exclusive OR operation of the two signals, if '0' is outputted, ACT_O and ACT_I are the same, and if '1' is outputted, it may be determined that they are different.

When it is determined that the operation error detection unit 32 has the current possession of the bus 10, the input / output control unit 30 applies the control signals CONT_0, CONT_1, and CONT_2 all low, The transmission of the frame synchronization signal FRS, the clock signal CLK, and the active signal ACT provided to the bus 10 is blocked.

On the other hand, when the active signal ACT_O received from the bus 10 and the active signal ACT_I generated in the device 20 are different, an abnormality occurs on the side of the device 20 having the occupancy right of the bus 10. This is a fault condition where no clock signal CLK is generated. Therefore, when the clock signal CLK is not received from the bus 10 for one period of the reference clock signal CLK_R, the input / output controller 30 transmits the clock signal CLK to the bus 10 so that the other device can receive the signal. The clock signal CLK is provided to 20 to occupy the bus 10.

7 is a control block diagram of the frame error detection unit 34. The frame error detection unit 34 receives a frame synchronization signal FRS received from the bus 10 and delays the frame synchronization signal FRS by one frame period, and the delayed frame synchronization signal FRS and the bus 10 in real time. Comparing unit 36 for comparing the phase difference between the received frame synchronization signal (FRS).

The frame error detection unit 34 delays the frame synchronization signal FRS input through the buffer unit 28a by one period through the delay unit 38 and performs a real time from the delayed frame synchronization signal FRS and the bus 10. The phase difference of the received frame signal is compared through the comparison unit 36. Here, the comparison unit 36 performs an exclusive OR operation to determine whether the two are identical. As a result of analyzing the frame synchronization signal (FRS) through the frame error detection unit 34, when it is determined that the frame synchronization signal delayed by one frame period and the frame synchronization signal input in real time are different, the frame synchronization signal FRS supplied to the bus 10 is provided. It is judged that there is an abnormality in).

If it is determined that the frame synchronization signal FRS is abnormal, another device 20 having a priority outputs the clock signal CLK and the frame synchronization signal FRS to occupy the bus 10.

A signal diagram of a multi-device control system in which a plurality of devices 20 having such a configuration exchange data through one bus 10 is shown in FIG. 8.

The device 20 having the highest priority among the plurality of devices 20 supplies the frame synchronization signal FRS, the clock signal CLK, and the active signal ACT through the bus 10, and each device Time slot is assigned to (20).

The devices 20 connected to the bus 10 set the CONT_1 signal, which is the data transmission signal, to “High” only for the timeslot period assigned to the bus 10 to transmit data in the corresponding timeslot period.

In the period where the timeslot is not allocated, each device 20 maintains a state of receiving transmission / reception data TRxD of the bus 10.

For example, the device 20 having the n-1th priority transmits data by setting the CONT_1 signal to 'High' in the n-1th time slot, and maintains the data receiving state in the remaining sections. .

 9 is a flowchart of a method of occupying the bus 10 of the device 20 during initial driving according to the method for controlling the multiple device 20 of the present invention.

When the system is booted and the first drive is started (S10), the CONT_0 signals of the devices 20 are basically set to 'Low' so that the frame sync signal FRS and the clock signal CLK are not output. In accordance with the state of the present invention or one of the plurality of devices 20, the device 20 provides the initial clock signal CLK and the frame synchronization signal FRS to the bus 10 (S12).

Each device 20 receives a clock signal CLK from the bus 10 and divides the clock signal CLK according to a preset method to generate a reference clock signal CLK_R having a longer period than the initially input clock signal CLK. (S14). Here, the clock division ratios of the devices 20 are all different according to the priority given to the devices 20, and each device has a different reference clock signal CLK_R.

Each device 20 determines whether the clock signal CLK is detected from the bus 10 within one period of the reference clock signal CLK_R (S16).

Any one of the devices 20 which detects that the clock signal CLK is not supplied to the bus 10 sets the CONT_0 signal to 'High' so that its clock signal CLK and the frame synchronization signal FRS Outputs the bus 10 to occupy the bus 10 (S18).

According to this process, when the device 20 performing the function as the master is determined, each device 20 starts a normal operation. 10 is a flowchart of a method for controlling multiple devices 20 in accordance with the present invention.

Each device 20 checks the time slots allocated to the area available to the user, based on the time slot information output from the device 20 performing the master function (S20).

Each device 20 determines whether the current timeslot belongs to a section allocated to the area in which it is available (S22).

If it is determined that the current timeslot interval is available, the control signal CONT_1 for data transmission and reception is set to 'High' to transmit data (S24). Here, the data actually transmitted is TD data, and the TD data is added to the transmission / reception data TRxD of the bus 10.

On the other hand, when the current time slot section corresponds to a section in which no use is allowed, the control signal CONT_1 for data transmission and reception is set to 'Low' so that the reception data RD of the transmission / reception data TRxD is received. (S26).

The device 20 receiving the data checks the processing address of the received device 20 (S28), processes valid data (S30), and discards the received data when it is determined that the data is not the processing target data (S32). ).

As such, when a failure occurs in the device 20 of the master qualification of the system in which the multi-operational device 20 operates normally, a method of detecting a failure state and transferring the occupancy rights to the bus 10 is illustrated in FIG. 11. .

In a normal operation state in which a control signal is supplied from the one device 20 occupying the bus 10 to the bus 10 (S40), each device 20 receives a clock signal CLK from the bus 10. Check whether it is being input (S42).

When the clock signal CLK is not detected on the bus 10, the active signal ACT_I is generated inside the device 20 (S44), and the active signal ACT_O is received from the bus 10 (S46). ).

It is determined whether the active signal ACT_O received from the bus 10 and the active signal ACT_I generated in the device 20 are the same (S48).

As a result of the determination, when the active signal ACT_O received from the bus 10 and the active signal ACT_I generated in the device 20 are different, the device 20 has an occupancy right on the bus 10 side. This is a fault condition in which the clock signal CLK is not generated. Therefore, when the clock signal CLK is not received from the bus 10 for one period of the reference clock signal CLK_R, the input / output controller 30 transmits the clock signal CLK to the bus 10 so that the other device can receive the signal. The clock signal CLK is provided to the 20 to occupy the bus 10 (S50).

When the active signal ACT_O received from the bus 10 and the active signal ACT_I generated in the device 20 are determined to be the same, the device 20 has the right to occupy the current bus 10. Since the input / output controller 30 applies the control signals CONT_0, CONT_1, and CONT_2 all low, the frame synchronization signal FRS, the clock signal CLK, and the active signal provided to the bus 10 are provided. Block the transmission of the (ACT) (S52).

Accordingly, when a failure of the device supplying the clock is detected, the occupancy of the bus can be transferred to another device. That is, when an error occurs in a device that performs a master function by occupying a bus, any one of the devices operating as a slave occupies the bus to perform a master function so that the entire system can operate normally.

As described above, the multi-device control system and its control method according to the present invention, by detecting the error of the clock signal, the frame synchronization signal, and the like supplied to the bus to detect the failure of the device occupying the bus, When a failure of a device occupying the bus is detected, another device occupies the bus.

Accordingly, the system can operate normally even when a device having a master authority fails, and a variety of communication channels can be provided by enabling data transmission and reception between each device.

1 is a block diagram of a conventional multi-device control system,

2 is a control flow diagram of a conventional multi-device control system,

3 is a block diagram of a multi-device control system according to the present invention;

4 is an internal control block diagram of the device of FIG.

5 is a control block diagram of a data transmitter and receiver of FIG. 3;

6 is a signal state diagram of an operation error detection unit of FIG. 3;

7 is a control block diagram of the frame error detector of FIG. 3;

8 is a signal diagram of a multi-device control system according to the present invention;

9 is a flowchart of a bus occupancy method of a device during initial driving according to a multi-device control method of the present invention;

10 is a flowchart of a multi-device control method according to an embodiment of the present invention;

11 is a flowchart of a multi-device control method according to another embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

10 bus 20 device

22: data processing unit 26: data transmission and reception unit

28: buffer unit 30: input and output control unit

32: motion error detection unit 34: frame error detection unit

Claims (10)

A data bus for transmitting signals for each device; A data transmitting / receiving unit for controlling data transmitted / received through the data bus; A buffer unit for controlling each control signal from the data bus; A data processor for processing data transmitted and received through the data transmitter and receiver and generating various control signals for signal transmission and reception; A divider for dividing a clock signal, which is a control signal received from the data bus, according to a predetermined priority, to generate a reference clock signal for determining whether a clock signal exists on the data bus; A frame error detection unit for comparing the sameness between the frame synchronization signal, which is a control signal received from the data bus, and the frame synchronization signal generated through the data processing unit, to determine whether the control signal is supplied to the data bus; In order to determine whether a control signal is supplied, an error of the control signal is checked through an operation error detection unit that compares the identity of an active signal, which is a control signal received from the data bus, and an internal active signal generated by the data processor, and confirms. As a result, an error has occurred in the control signal supplied to the bus. If the multi-device control system comprising the input-output control unit for outputting to the data bus through the buffer to the control signals generated in the data processor. delete The method of claim 1, wherein the frame error detection unit, A delay unit for delaying the frame synchronization signal received from the data bus in a predetermined frame unit; And a signal comparison unit for comparing a phase difference between the frame synchronization signal delayed through the delay unit and the frame synchronization signal received in real time from the data bus. The method of claim 1, wherein the operation error detection unit, And a signal comparator for comparing a phase difference between the active signal received from the data bus through the buffer unit and an internal active signal generated through the data processor. Receiving a control signal such as a clock signal, a frame synchronization signal, an active signal from the data bus; Generating a reference clock signal by dividing the clock signal received from the data bus according to a predetermined priority order; Determining whether a clock signal is present on the data bus based on the reference clock signal; And if it is determined that the clock signal does not exist on the data bus, supplying a clock signal to the data bus. delete The method of claim 5, wherein Determining whether a clock signal is present on the data bus; Generating an active signal internally when the clock signal is not detected on the data bus; Determining whether the generated active signal is identical to the active signal received from the data bus; And supplying a control signal to the data bus when the generated active signal and the active signal received from the data bus are different. The method of claim 7, wherein And if it is determined that the generated active signal and the active signal received from the data bus are the same, blocking transmission of a control signal supplied to the data bus. The method of claim 5, wherein Delaying the frame synchronization signal received from the data bus in a predetermined frame unit; Determining whether the delayed frame synchronization signal and the frame synchronization signal received in real time from the data bus are identical; And determining that the frame synchronization signal is in an error state when it is determined that the two are different from each other. The method of claim 5, wherein Determining an allocated timeslot section based on the control signal received from the data bus; Determining whether the current timeslot section is a section to which a usage right is assigned; And if it is determined that the current time slot section is not the allocated time slot section, receiving the data from the data bus.