KR100493044B1 - Optical disk reproduction system having integrated circuit with a reduced pin number - Google Patents

Abstract

An optical disc reproducing system having an integrated circuit with a reduced number of pins is provided. An optical disc reproducing system relates to an optical disc reproducing system which processes audio / video information picked up from an optical disc and transmits output data to a speaker or a monitor. An optical disc reproduction system includes a digital signal processor, a decoder, and a microcomputer. The digital signal processor picks up the audio / video information picked up from the optical disc, performs error correction, and prepares for transmission of the error corrected data. The decoding unit receives the data in which the error is corrected, decodes the received data to generate output data. The microcomputer controls the operation of the digital signal processing unit and the operation of the decoding unit. Microcomputer register pins used to write / read data related to data transmitted from the digital signal processor to the decoder in registers included in the digital signal processor and the decoder, respectively, and used to transmit data from the digital signal processor to the decoder. The data interface pins are jointly used by enabling / disabling predetermined signals exchanged between the digital signal processor, the decoder, and the digital signal processor. Since the optical disc reproducing system has a digital signal processor and a decoding unit with a reduced number of pins, the manufacturing cost of the optical disc reproducing system can be saved and the wiring on the printed circuit board can be simplified.

Description

Optical disk reproduction system having integrated circuit with a reduced pin number

The present invention relates to an optical disc reproducing system, and more particularly, to an optical disc reproducing system having an integrated circuit (IC) with a reduced number of pins.

An optical disk reproducing system (for example, a digital versatile disk player (DVDP)) that reproduces an optical disk such as a digital versatile disk (DVD) in which audio / video information is recorded is picked up from an optical disk. -Up) Digitally processes and decodes the audio / video information to generate a signal for operating a monitor or a speaker.

1 is a diagram schematically showing a conventional optical disc reproducing system. Referring to FIG. 1, an optical disc reproducing system is a system for processing information (DPU) picked up from an optical disc (DISK) and transmitting output data (DO) to a speaker or a monitor. The processor 110 includes a processor 110, a micom 130, and a decoder 150.

The microcomputer 130 stores the control information and performs overall control. That is, it generates a control signal for controlling the overall operations of the digital signal processor 110 and the decoder 150, and generates an audio / video data output control signal required by other users.

The digital signal processing unit 110 is controlled by the microcomputer 130, picks up the audio / video information (DPU) from the optical disk (DISK), performs error correction on the data encoded by MPEG, etc., and the decoding unit 150 Prepare for data transfer. The digital signal processing unit 110 includes a register, which registers data (or information) related to the format of data transmitted from the digital signal processing unit 110 and the decoding unit 150 and the number of error corrections. The microcomputer 130 temporarily stores the signals received from the 110 to control the digital signal processor 110 to be read by the microcomputer 130.

The decoding unit 150 is controlled by the microcomputer 130 and generates output data DO after decoding the data transmitted from the digital signal processing unit 110 to the decoding unit 150. The decoding process is to decode the data transmitted from the digital signal processing unit 110 to the decoding unit 150 by MPEG standard or the like to generate output data DO which is transmitted to a speaker or a monitor. The decoding unit 150 also includes a register, which registers data (or information) related to the format of data transmitted from the digital signal processing unit 110 and the decoding unit 150 and the number of error corrections, and the like. ) And temporarily store the signals controlling the decoder 150 to be read by the microcomputer 130.

FIG. 2 is a diagram schematically illustrating a pin configuration of integrated circuits (ICs) corresponding to the digital signal processor, the microcomputer, and the decoder of FIG. 1 according to the related art. Referring to FIG. 2, pins for interfacing the digital signal processing unit 110, the microcomputer 130, and the decoding unit 150 will be described.

First, the pins for interfacing between the microcomputer 130 and the digital signal processor 110 and the microcomputer 130 and the decoder 150 will be described below. The RSTB pin included in the microcomputer 130, the digital signal processor 110, and the decoder 150 transmits a signal in which the microcomputer 130 sets the digital signal processor 110 and the decoder 150 to initial values. It is a pin. The WAIT pin included in the microcomputer 130, the digital signal processing unit 110, and the decoding unit 150 confirms whether the digital signal processing unit 110 and the decoding unit 150 correctly received the command of the microcomputer 130. It is a pin that transmits a signal. The IRQ0 pin and the IRQ pin included in the microcomputer 130 and the digital signal processing unit 110 are pins for transmitting a signal for interrupting the microcomputer 130 to the microcomputer 130. The IRQ1 pin and the IRQ pin respectively included in the microcomputer 130 and the decoding unit 150 are pins for transmitting a signal that interrupts the microcomputer 130 to the microcomputer 130. The CSB0 pin and the CSB pin included in the microcomputer 130 and the digital signal processor 110 are pins for transmitting a signal for the microcomputer 130 to select the digital signal processor 110. The CSB1 pin and the CSB pin included in the microcomputer 130 and the decoding unit 150 are pins for transmitting a signal for the microcomputer 130 to select the decoding unit 150. The DAB pins included in the microcomputer 130, the digital signal processor 110, and the decoder 150 have addresses of the microcomputer 130 transmitted to the registers of the digital signal processor 110 and the decoder 150. This pin transmits a signal indicating whether it is a value or a data value. The MWRB pin included in the microcomputer 130, the digital signal processor 110, and the decoder 150 includes an address value or a data value of the microcomputer 130 as registers of the digital signal processor 110 and the decoder 150. This is a pin that transmits a control signal used to write. The MRDB pins included in the microcomputer 130, the digital signal processor 110, and the decoder 150 may read data values of registers included in the digital signal processor 110 and the decoder 150 by the microcomputer 130. This is a pin that transmits a control signal used when reading. The MDAT0 to MDAT7 pins (hereinafter, referred to as micom register pins) included in the microcomputer 130, the digital signal processor 110, and the decoder 150, are referred to as the digital signal processor. A pin for transmitting data used when writing or reading an address value or a data value into the registers of the 110 and the decoder 150.

Next, the pins for interfacing between the digital signal processor 110 and the decoder 150 will be described below. The DAT_REQ pins included in the digital signal processor 110 and the decoder 150 are pins for transmitting a signal for the decoder 150 to transmit data to the digital signal processor 110. The DAT_ACK pins included in the digital signal processor 110 and the decoder 150 are pins for the digital signal processor 110 to transmit a signal indicating that the data is ready to be transmitted to the decoder 150. The DATA_ERR pin included in the digital signal processing unit 110 and the decoding unit 150 is a pin that the digital signal processing unit 110 transmits to the decoding unit 150 to signal that an error value is included in the transmission data. The DATA_TOS pins included in the digital signal processing unit 110 and the decoding unit 150 are pins for transmitting signals indicating the top of the transmission data of the digital signal processing unit 110. The DAT_ST pins included in the digital signal processing unit 110 and the decoding unit 150 are pins for transmitting a reference signal informing of a change in transmission data of the digital signal processing unit 110. The SDT0 pins to the SDT7 pins included in the digital signal processing unit 110 and the decoding unit 150 are pins for transmitting data of the digital signal processing unit 110, respectively. Data transmitted through the SDT0 to SDT7 pins (hereinafter referred to as data interface pins) are data including audio / video information picked up from the optical disk.

However, since the optical disc reproducing system according to the related art is composed of integrated circuits including a relatively large number of pins, the manufacturing cost may be increased when the optical disc reproducing system is implemented as integrated circuits. In addition, a lot of wiring for connecting three integrated circuits (that is, the digital signal processing unit 110, the microcomputer 130, and the decoding unit 150) on a printed circuit board (PCB) is required. This can be complicated.

Accordingly, a technical problem to be achieved by the present invention is to jointly use the microcomputer register pins for interfacing between the microcomputer and the digital signal processor and between the microcomputer and the decoder, and the data interface pins for interfacing between the digital signal processor and the decoder. An optical disc playback system is provided.

In order to achieve the above technical problem, an optical disc reproducing system according to the present invention relates to an optical disc reproducing system for processing audio / video information picked up from an optical disc and transmitting output data to a speaker or a monitor. An optical disc reproducing system according to the present invention comprises: a digital signal processing unit which picks up audio / video information picked up from the optical disc, performs error correction, and prepares to transmit the error corrected data;

A decoding unit which receives the data with the error corrected, decodes the received data to generate the output data; And a microcomputer for controlling the operation of the digital signal processing unit and the operation of the decoding unit, and writing data related to data transmitted from the digital signal processing unit to the decoding unit in registers included in the digital signal processing unit and the decoding unit, respectively. Microcomputer register pins used for reading / reading, and data interface pins used for transferring data from the digital signal processing unit to the decoding unit, which are exchanged between the digital signal processing unit, the decoding unit and the digital signal processing unit. It is characterized in that it is used jointly by the activation / deactivation of the signals of.

According to a preferred embodiment, the signals are a first chip select signal indicating that the digital signal processing unit is selected by the microcomputer, a second chip select signal indicating that the decoding unit is selected by the microcomputer, and the decoding unit is the digital signal. A data request signal for instructing a signal processor to request data and a data transmission ready signal for instructing that the digital signal processor is ready to transmit data to the decoding unit, wherein the first chip select signal is activated; In the case of the deactivation of the second chip select signal, the deactivation of the data request signal, and the deactivation of the data transmission ready signal, the microcomputer and the digital signal processing unit may be used through the commonly used microcomputer register pins and data interface pins. Of data between registers The commonly used micom register pins are performed in the case of deactivation of the first chip select signal, activation of the second chip select signal, deactivation of the data request signal, and deactivation of the data transmission ready signal. And data exchange between the microcomputer and the register of the decoding unit through data interface pins, deactivation of the first and second chip select signals, activation of the data request signal, and activation of the data transmission ready signal. In the case of, the transmission of data from the digital signal processing unit to the decoding unit is performed through the commonly used microcomputer register pins and data interface pins.

According to a preferred embodiment, the first and second chip select signals are activated at a low level, and the data request signal and the data transfer ready signal are activated at a high level.

According to a preferred embodiment, the data transmitted from the digital signal processor to the decoding unit via the commonly used microcomputer interface pins and data interface pins is 8-bit data.

In the optical disc reproducing system according to the present invention, since the microcomputer register pins for interfacing between the microcomputer and the digital signal processing unit and between the microcomputer and the decoding unit and the data interface pins for interfacing between the digital signal processing unit and the decoding unit are commonly used, The number of pins of the integrated circuit corresponding to each of the digital signal processor and the decoder may be reduced. Therefore, the manufacturing cost of integrated circuits for implementing the optical disc reproducing system can be saved and the wiring for connecting the integrated circuits on the printed circuit board can be simplified.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram schematically illustrating a pin configuration of integrated circuits (ICs) included in an optical disk reproducing system according to an exemplary embodiment of the present invention. That is, FIG. 3 is a diagram schematically illustrating a pin configuration of integrated circuits respectively corresponding to the digital signal processing unit, the microcomputer, and the decoding unit of FIG. 1. Referring to FIG. 3, an optical disc reproducing system 200 according to an embodiment of the present invention includes a digital signal processor (DSP) 210, a micom 230, and a decoder 250. do.

The microcomputer 230 stores control information and performs overall control. That is, it generates a control signal for controlling the overall operations of the digital signal processor 210 and the decoder 250, and generates an audio / video data output control signal required by other users.

The digital signal processor 210 is controlled by the microcomputer 230, picks up audio / video information from an optical disc (not shown), performs error correction on data encoded by MPEG, etc., and then decodes the decoder 250. Prepare for data transfer. The digital signal processor 210 includes a register, which registers data (or information) related to the format of data transmitted from the digital signal processor 210 to the decoder 250 and the number of error corrections. The signals received from the 230 to control the digital signal processor 210 are temporarily stored so that the microcomputer 230 can read the signals.

The decoder 250 is controlled by the microcomputer 230, and decodes data transmitted from the digital signal processor 210 to the decoder 250 to generate output data. The decoding process is to decode the data transmitted from the digital signal processing unit 210 to the decoding unit 250 according to the MPEG standard to generate output data transmitted to the speaker or the monitor. The decoder 250 also includes a register, which registers data (or information) related to the format of data transmitted from the digital signal processor 210 to the decoder 250 and the number of error corrections. ) And temporarily store the signals controlling the decoder 250 to be read by the microcomputer 230.

Referring to FIG. 3, the pins for interfacing the digital signal processor 110, the microcomputer 130, and the decoder 150 will be described.

First, the pins interfaced between the microcomputer 230 and the digital signal processor 210 and the microcomputer 230 and the decoder 250 will be described below. The RSTB pin included in the microcomputer 230, the digital signal processor 210, and the decoder 250 transmits a signal in which the microcomputer 230 sets the digital signal processor 210 and the decoder 250 to initial values. It is a pin. The WAIT pins included in the microcomputer 230, the digital signal processor 210, and the decoder 250 determine whether the digital signal processor 210 and the decoder 250 correctly receive the command of the microcomputer 230. This is a pin that transmits a signal. The IRQ0 pin and the IRQ pin included in the microcomputer 230 and the digital signal processor 210, respectively, are pins for transmitting a signal for interrupting the microcomputer 230 to the microcomputer 230. The IRQ1 pin and the IRQ pin included in the microcomputer 230 and the decoder 250, respectively, are pins for the decoder 250 to transmit an interrupt signal to the microcomputer 230. The CSB0 pin and the CSB pin included in the microcomputer 230 and the digital signal processor 210, respectively, are pins for the microcomputer 230 to transmit a first chip select signal for selecting the digital signal processor 210. The CSB1 pin and the CSB pin included in the microcomputer 230 and the decoder 250 are pins for transmitting the second chip select signal for the microcomputer 230 to select the decoder 250. The DAB pins included in the microcomputer 230, the digital signal processor 210, and the decoder 250 have addresses of the microcomputer 230 transmitted to the registers of the digital signal processor 210 and the decoder 250. This pin transmits a data / address confirmation signal indicating whether it is a value or a data value. The MWRB pin included in the microcomputer 230, the digital signal processor 210, and the decoder 250 includes an address value or a data value of the microcomputer 230 as registers of the digital signal processor 210 and the decoder 250. This pin transmits a write control signal used to write. In the MRDB pin included in the microcomputer 230, the digital signal processor 210, and the decoder 250, the microcomputer 230 reads data values of registers of the digital signal processor 210 and the decoder 250. It is a pin that transmits read control signal used when). The MDAT0 / SDT0 pins to MDAT7 / SDT7 pins (that is, the microcomputer interface pins and the data interface pins) included in the digital signal processor 210 and the decoder 250 are connected to the MDAT0 pins to the MDAT7 pins of the microcomputer 230, respectively. The microcomputer 230 is a pin that transmits data used when the microcomputer 230 writes or reads an address value or a data value to the registers of the digital signal processor 210 and the decoder 250. In addition, the MDAT0 / SDT0 to MDAT7 / SDT7 pins are also used to transmit data including audio / video information of the optical disk from the digital signal processor 210 to the decoder 250. A method for jointly using the MDAT0 / SDT0 to MDAT7 / SDT7 pins will be described with reference to FIG. 4 to be described later.

Next, the pins for interfacing between the digital signal processor 210 and the decoder 250 will be described below. The DAT_REQ pins included in the digital signal processor 210 and the decoder 250 are pins for transmitting the data request signal for requesting data transmission to the digital signal processor 210. The DAT_ACK pins included in the digital signal processor 210 and the decoder 250 are pins for the digital signal processor 210 to transmit a data transmission ready signal informing the decoder 250 that data is ready for data transmission. The DATA_ERR pin included in the digital signal processor 210 and the decoder 250 is a pin that the digital signal processor 210 transmits a signal indicating to the decoder 250 that an error value is included in the transmission data. The DATA_TOS pin included in the digital signal processor 210 and the decoder 250 is a pin that transmits a signal indicating the top of the transmission data of the digital signal processor 110. The DAT_ST pins included in the digital signal processor 210 and the decoder 250 are pins for transmitting a reference signal for notifying change of transmission data of the digital signal processor 110. As described above, the MDAT0 / SDT0 to MDAT7 / SDT7 pins included in the digital signal processing unit 210 and the decoding unit 250 are not only data of the digital signal processing unit 210 but also the digital signal processing unit 210 and the decoding unit ( Pins capable of transmitting data stored in the registers of 250).

Accordingly, in the optical disc reproducing system 200 according to an embodiment of the present invention, data stored in a register is transmitted through the MDAT0 / SDT0 pins to the MDAT7 / SDT7 pins, which are used in common, and data including video / audio information is transmitted. As a result, the number of pins of the digital signal processor 210 and the decoder 250 may be reduced by eight, respectively, as compared with the related art. Therefore, when the optical disc reproducing system is implemented with integrated circuits corresponding to the digital signal processing unit 210 and the decoding unit 250, the manufacturing cost can be reduced and the wiring connecting the integrated circuits can be simplified.

FIG. 4 is a timing diagram showing main signals transmitted through pins of integrated circuits included in the optical disk reproducing system shown in FIG. 3. That is, FIG. 4 illustrates an embodiment of the present invention in which the microcomputer register pins and the data interface pins among the pins of the digital signal processor 210 and the decoder 250 illustrated in FIG. 3 are jointly used (that is, shared). A timing diagram showing the timing of the major signals transmitted through the pins of the integrated circuits of an optical disc playback system according to an example.

Referring to FIG. 4, periods in which signal exchange between the microcomputer 230 and the digital signal processor 210 are performed (that is, the register value writing interval of the microcomputer 230 with respect to the digital signal processor 210 and the digital signal processor) are performed. The register value reading section of the microcomputer 230 for 210, and the sections in which signal exchange between the microcom 230 and the decoding unit 250 is performed (that is, the microcomputer 230 for the decoding unit 250). The register value writing section, the register value reading section of the microcomputer 230 with respect to the decoding unit 250), and the section in which signal exchange between the digital signal processing unit 210 and the decoding unit 250 are performed are described.

First, an interval in which the microcomputer 230 writes / reads an 8-bit address value Address [7: 0] and an 8-bit data value DAT [7: 0] into a register of the digital signal processor 210. It will be described as follows. When the first chip select signal CSB0 transmitted to the digital signal processor 210 through the CSB0 pin of the microcomputer 230 is activated at a low level, the digital signal processor 210 is selected. Similarly, when the second chip select signal CSB1 transmitted to the decoder 250 through the CSB1 pin of the microcomputer 230 is activated at a low level, the decoder 250 is selected. Meanwhile, when the first chip select signal CSB0 is activated at a low level, the second chip select signal CSB1 is deactivated at a high level so that the decoding unit 250 is not selected and a data request is transmitted through the DAT_REQ pin. The signal DAT_REQ and the data transmission ready signal DAT_ACK transmitted through the DAT_ACK pin are respectively deactivated to a low level. That is, only the signal exchange between the microcomputer 230 and the digital signal processor 210 is performed in the register value write / read section of the microcomputer 230 with respect to the digital signal processor 210 illustrated in FIG. 4.

When the data / address confirmation signal (DAB) transmitted through the DAB pin is activated at the low level, an address value is transmitted through the commonly used MDAT0 / SDT0 pins to MDAT7 / SDT7 pins, and a data / address confirmation signal (DAB Is deactivated to a high level, data values are transmitted via the commonly used MDAT0 / SDT0 pins to MDAT7 / SDT7 pins. When the write control signal MWRB transmitted through the MWRB pin is activated at a low level, an 8-bit address value (Address [7: 0]) and an 8-bit data value (DAT [7: 0]) are digital signals. The registers of the processor 210 are written through the MDAT0 / SDT0 pins to the MDAT7 / SDT7 pins. When the read control signal MWRB transmitted through the MRDB pin is activated at a low level, the microcomputer 230 may set a predetermined address value (Address [7: 0]) of a register included in the digital signal processor 210. The data value (DAT [7: 0]) stored in the data is read out through the commonly used MDAT0 / SDT0 to MDAT7 / SDT7 pins.

In the meantime, the microcomputer 230 writes / reads an 8-bit address value Address [7: 0] and an 8-bit data value DAT [7: 0] to a register of the decoding unit 250. For the explanation, the microcomputer 230 writes / reads an 8-bit address value Address [7: 0] and an 8-bit data value DAT [7: 0] to a register of the digital signal processor 210. Since is similar to the description of the section, it is omitted herein for convenience of description. However, in the register value write / read section of the microcomputer 210 with respect to the decoder 250 illustrated in FIG. 4, the second chip select signal CSB1 is activated at a low level and the first chip select signal CSB0 is activated. The high level is inactivated and the data request signal DAT_REQ and the data transmission ready signal DAT_ACK are respectively inactivated to a low level, so that only the signal exchange between the microcomputer 210 and the decoding unit 250 is performed.

Lastly, a section in which parallel data is transmitted from the digital signal processor 210 to the decoder 250 through the MDAT0 / SDT0 pins to MDAT7 / SDT7 pins, which are commonly used, will be described below. When the data request signal DAT_REQ is activated at a high level, the decoding unit 250 requests the digital signal processing unit 210 to transmit data. Then, after receiving the data request signal DAT_REQ, the digital signal processor 210 activates the data transmission ready signal DAT_ACK to a high level and transmits data having a valid value to the decoder 250. At this time, the states of the first chip select signal CSB0 and the second chip select signal CSB1 are respectively deactivated to a high level. A signal DAT_ERR indicating that an error value is included in the data together with the data having the valid value is transmitted to the decoding unit 250 through the DAT_ERR pin. When the data transmission ready signal DAT_ACK is deactivated to a low level, data has an invalid value and data is not transmitted. The transmitted data value is changed in synchronization with the reference signal DAT_ST transmitted through the DAT_ST pin. On the other hand, the data head signal DAT_TOS indicating the head of the data is activated to a high level and informs the decoding unit 250 of the top of the transmitted data.

Accordingly, in the signal exchange between the microcomputer 230 and the digital signal processor 210 included in the optical disc reproducing system according to an embodiment of the present invention, the first chip select signal CSB0 is activated at a low level and the second The chip select signal CSB1 is deactivated to a high level and is performed when the data request signal DAT_REQ and the data transmission ready signal DAT_ACK are deactivated to a low level, respectively. In addition, in the signal exchange between the microcomputer 230 and the decoder 250, the first chip select signal CSB0 is deactivated to a high level, the second chip select signal CSB1 is activated to a low level, and the data request signal ( When the DAT_REQ and the data transmission ready signal DAT_ACK are respectively deactivated to a low level, they are performed. In the signal exchange between the digital signal processor 210 and the decoder 250, the first chip select signal CSB0 and the second chip select signal CSB1 are respectively deactivated to a high level and the data request signal DATA_REQ is deactivated. And when the data transmission ready signal DATA_ACK is activated to a high level, respectively.

Meanwhile, although the pin configuration of the optical disk reproducing system according to an embodiment of the present invention is implemented by transmitting 8 bits of data through the MDAT0 / SDT0 pin through the MDAT7 / SDT7 pin, the optical disk reproducing of 16 bits of data is transmitted. The present invention may be applied to the pin configuration of the system. Then the number of pins to be reduced will be increased further. In addition, although the optical disc reproducing system according to an embodiment of the present invention is implemented with three integrated circuits, when the present invention is applied even when one integrated circuit is implemented, the manufacturing cost of the integrated circuits is reduced because the number of pins to be interfaced is reduced. Can be saved and wiring on the printed circuit board can be facilitated.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the optical disc reproducing system according to the present invention, since the microcomputer register pins for interfacing between the microcomputer and the digital signal processing unit and between the microcomputer and the decoding unit and the data interface pins for interfacing the digital signal processing unit and the decoding unit are jointly used, The number of pins of the integrated circuit respectively corresponding to the signal processor and the decoder may be reduced. Therefore, the manufacturing cost of integrated circuits for implementing the optical disc reproducing system can be saved and the wiring for connecting the integrated circuits on the printed circuit board can be simplified.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a diagram schematically showing a conventional optical disc reproducing system.

FIG. 2 is a diagram schematically illustrating a pin configuration of integrated circuits (ICs) corresponding to the digital signal processor, the microcomputer, and the decoder of FIG. 1 according to the related art.

3 is a diagram schematically illustrating a pin configuration of integrated circuits (ICs) included in an optical disk reproducing system according to an exemplary embodiment of the present invention.

FIG. 4 is a timing diagram showing main signals transmitted through pins of integrated circuits included in the optical disk reproducing system shown in FIG. 3.

<Description of Symbols for Main Parts of Drawings>

210: digital signal processor 230: microcomputer

250: decoding unit

Claims (4)

An optical disc playback system for processing audio / video information picked up from an optical disc and transmitting output data to a speaker or a monitor, A digital signal processing unit which picks up audio / video information picked up from the optical disc, performs error correction, and prepares to transmit the error corrected data; A decoding unit which receives the data with the error corrected, decodes the received data to generate the output data; And A microcomputer for controlling the operation of the digital signal processing unit and the operation of the decoding unit; Microcomputer register pins used to write / read data related to data transmitted from the digital signal processor to the decoder in registers respectively included in the digital signal processor and the decoder, and from the digital signal processor to the decoder. The data interface pins used to transmit data are jointly used by activation / deactivation of predetermined signals exchanged between the digital signal processing unit, the decoding unit and the digital signal processing unit. . The method of claim 1, The signals include a first chip select signal indicating that the digital signal processing unit is selected by the micom, a second chip select signal indicating that the decoding unit is selected by the micom, and the decoding unit requests data from the digital signal processing unit. A data request signal for indicating that the digital signal processor and the data transmission ready signal for indicating that the data to be transmitted to the decoding unit is ready; In the case of activation of the first chip select signal, deactivation of the second chip select signal, deactivation of the data request signal, and deactivation of the data transmission ready signal, the commonly used microcomputer register pins and data interface pins. Through the exchange of data between the microcomputer and the register of the digital signal processing unit is performed, In the case of deactivation of the first chip select signal, activation of the second chip select signal, deactivation of the data request signal, and deactivation of the data transmission ready signal, the commonly used microcomputer register pins and data interface pins. Through the exchange of data between the microcomputer and the register register of the decoding unit is performed, In the case of deactivation of the first and second chip select signals, activation of the data request signal, and activation of the data transmission ready signal, the digital signal processor through the commonly used microcomputer register pins and data interface pins. And data transfer is performed from the decoding unit to the decoding unit. The method of claim 2, And the first and second chip select signals are activated at a low level, and the data request signal and the data transfer ready signal are activated at a high level, respectively. The method of claim 3, And the data transmitted from the digital signal processing unit to the decoding unit through the commonly used microcomputer interface pins and data interface pins is 8-bit data.