KR100490503B1 - Array chip - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked array chip in which a plurality of unit elements are arranged in parallel in a single chip. To provide that purpose. In order to achieve the object of the present invention, an array chip includes a plurality of unit elements having first and second external terminals formed at opposite ends thereof arranged in parallel in the longitudinal direction, and positioned in a direction intersecting the opposite end directions. An array chip having third external terminals serving as common terminals at different opposite ends thereof, wherein each of the unit elements includes a conductor pattern formed in the transverse direction, and the conductor pattern formed in one unit element includes an adjacent unit. It is disposed close to the conductor pattern formed in the element to form a pair, and these pairs are disposed with a predetermined distance therebetween.

Description

Array Chip {ARRAY CHIP}

The present invention relates to a stacked array chip in which a plurality of unit elements are arranged in parallel in a single chip, and more particularly, to a stacked array chip in which a spacing of a plurality of unit elements is adjusted.

Representative passive elements in electronic circuits include resistors (R), capacitors (C), and inductors (L), and their functions and roles vary widely. The resistive element plays a role of controlling current flow, dropping voltage, and impedance matching in an alternating current circuit in a circuit, and combining various passive components such as capacitors and inductors to implement various filters to remove high frequency noise as well as frequency selection. It is performing a function. Capacitors basically block direct current and pass alternating current signals, but they also form time constant circuits, time delay circuits, RC and LC filter circuits, and the capacitors themselves remove noise. The inductor performs high frequency noise elimination and impedance matching.

In addition, the varistor element is widely used as a protection element to protect important electronic components and circuits from overvoltage (surge voltage) and static electricity because the resistance changes according to the applied voltage. In other words, current does not flow to a varistor element disposed in a circuit, but if an overvoltage is applied to both ends of a varistor element due to an overvoltage or lightning strike over a certain voltage, the resistance of the varistor element is rapidly decreased, and almost all currents flow through the varistor element. No current flows in the circuit so that the circuit is protected from overvoltage. In addition, the varistor element acts as a capacitor in a steady state without overvoltage. Such a capacitor refers to a device having a property of passing a signal only when there is a change in current or voltage between disconnected metals. However, the capacitor has not only a capacitance value but a parasitic inductance value. Similarly, an inductor is a device having a property of preventing a change in current when a current flows through the wire, and the inductor has a parasitic capacitance value in addition to the inductance value. This changes the function of the device at a specific high frequency, which is called the self-resonant frequency.

Resistor-varistor composite chips that combine resistive and varistor components together in a single chip eliminate noise from high-frequency lines while protecting against overvoltage and static electricity. By combining the varistor element and the resistance element as described above, it is possible not only to effectively protect important electronic components, small motors and circuits from overvoltage, but also to ensure stable operation of electronic components or circuits by securing a stable power supply voltage and removing noise components. I can guarantee it.

The combination of the inductor-varistor can realize a pi (π) type filter made of an inductor capacitor with good high frequency noise rejection. Such a resistance-varistor coupling element or an inductor-varistor coupling element immediately exhibits the function of the varistor when an abnormal overvoltage flows in the circuit, thereby blocking the overcurrent as described above. In general, typical passive devices, such as resistors, inductors, and capacitors, can be properly combined with each other to perform impedance matching, high frequency and low frequency noise cancellation, or signal selection in a specific frequency band.

In this way, the resistor-varistor and inductor-varistor combination chips can protect electronic components or circuits from overvoltage and remove noise components, thereby ensuring stable operation of the electronic components or circuits. Coupling and coupling of inductor-varistor elements are often repeated. In particular, in recent years, in response to the miniaturization of electronic devices, demands for highly integrated circuit chip elements have increased. In view of this, arraying capable of accommodating several resistor-varistor-coupled chips and inductor-varistor-coupled chips in a single chip is essential for miniaturization of electronic devices.

As an example, FIG. 13A shows a configuration together with a manufacturing process of a stacked array chip in which four devices are made of one chip.

First, a desired molded sheet for a device is produced. If the varistor device is manufactured, a ball mill (ball ball) is used for 24 hours using water or alcohol in a desired composition using raw material powder of a commercially available varistor device or by adding an additive such as Bi ₂ O ₃ , CoO, MnO to ZnO powder. mill) to prepare the raw powder. After preparing PVB-based binder (binder) as an additive to the prepared varistor powder to prepare a molded sheet about 6wt% of the raw material powder, dissolved in toluene / alcohol (toluene / alcohol) -based solvent (solvent) A slurry is prepared by milling and mixing for about 24 hours with a small ball mill. This slurry is used to prepare molded sheets 1300 to 1304 of a desired thickness by a method such as a doctor blade. At this time, the raw material powder of the composition for the capacitor element, the raw material powder of the composition for the PTC (positive temperature coefficient) thermistor element, or the raw material powder of the composition for the negative temperature coefficient (NTC) thermistor element is also produced into a molded sheet having a desired thickness in the same manner. can do.

A conductive pattern, such as Ag, Pt, or Pd, is formed on the prepared sheet by a thin film manufacturing method such as screen printing or sputtering, evaporation, vapor chemical vapor deposition, sol-gel coating, and the like, as shown in FIG. 13A. This formed sheet is produced. That is, the first sheet 1301 is formed by forming a first conductor pattern 1310 across the two opposite ends of the sheet, and both sides in the longitudinal direction intersecting the first conductor pattern 1310. The second sheet 1302 is manufactured by forming a second conductor pattern 1311 across the end. A third conductor pattern 1312 is formed in the same transverse direction as the first conductor pattern 1310 to manufacture a third sheet 1303, and a fourth in the same direction as the first conductor pattern 1310. The conductor pattern 1313 is formed to manufacture the fourth sheet 1304. As described above, the first to fourth sheets 1301 to 1304 on which the conductor patterns are formed include the first sheet 1301, the third sheet 1303, the second sheet 1302, the fourth sheet 1304, and the first sheet. Two sheets 1302 are laminated in order, and the cover sheet 1300 is further laminated on the uppermost layer. After the laminate laminated as described above is pressed and fired, an external terminal is formed to complete the laminated chip.

In the first sheet 1301 of the laminated chip manufactured as described above, four first conductor patterns 1310 transversely opposite opposite sides of each unit element are formed in parallel along the longitudinal direction, one for each element. In the third and fourth sheets 1303 and 1304, the third and fourth conductor patterns 1312 and 1313 are disposed in the longitudinal direction in the same transverse direction as the first conductor pattern 1310. The two conductor pattern 1311 is formed. In addition, the first and second external terminals 1330a to 1330d and 1331a to 1331d respectively connected to both ends of the first conductor pattern 1310 are input / output terminals (signal electrodes), and the input / output terminals are third and fourth. Also connected to opposite ends of the conductor patterns 1312 and 1313, respectively. The third external terminals 1332a and 1332b connected to both ends of the second conductor pattern 1311 are common terminals (ground electrodes). At this time, the part divided by the virtual line (two-dot chain line) in the drawing is to operate as one element. The stacked array chip having such a structure has a structure in which current flow crosses 90 degrees, which is called a feedthrough type capacitor.

Thus, in an array chip in which four unit elements 1320a to 1320d are arranged in parallel on one chip, the frequency characteristics of each unit element are shown in FIG. 13B, for example, of the unit element 1320a and the unit element 1320b. As can be seen, they have different frequency characteristics (resonance point and insertion loss). In FIG. 13A, when a signal is input from one electrode of the terminal of the unit element 1320a, for example, the external terminal 1331a, the signal is output to the external terminal 1332a which is the shortest ground electrode. Similarly, the unit element 1320b also goes to the external terminal 1332a which is also the shortest distance. However, the unit element 1320b has a longer exit length than the unit element 1320a, so that the equivalent inductance increases, so that the resonance frequency decreases as shown in the frequency characteristic of FIG. 13B. In addition, since the unit elements adjacent to each other have an electrical effect on each other, the unit element 1320a receives a lot of electrical effects from the unit element 1320b, but the unit element 1320b includes two unit elements 1320a and 1320c. Due to the large electrical influence from the frequency characteristic difference between the unit element 1320a and the unit element 1320b becomes larger. Accordingly, the unit element 1320a has a frequency characteristic shown by reference numeral a in FIG. 13B, and the unit element 1320b has a frequency characteristic shown by reference numeral b in FIG. 13B.

An object of the present invention is to solve the problems of the prior art as described above, to provide a stacked array chip to reduce the difference in frequency characteristics of each unit device in a stacked array chip is a plurality of devices made of one chip will be.

Another object of the present invention is to provide a stacked array chip for protecting important electronic components such as semiconductor integrated circuits from overvoltage and static electricity.

It is still another object of the present invention to provide a stacked array chip that variously adjusts capacitance values, resistance values, and inductance values.

It is still another object of the present invention to provide a stacked array chip in which heterogeneous devices are combined according to the application to adjust desired device characteristics, for example, insertion loss, resonance frequency, or equivalent series resistance.

An array chip for achieving the above object of the present invention is a plurality of unit elements having a first and a second external terminal formed on both opposing ends are arranged in parallel along the longitudinal direction, and are positioned in a direction crossing the opposite opposing directions The third external terminal, which is a common terminal, is formed at two opposite ends. In the array chip, each of the unit elements includes a conductor pattern formed in the lateral direction, and a conductor pattern formed in one unit element is disposed close to a conductor pattern formed in an adjacent unit element to form a pair. These pairs are arranged with a predetermined distance from each other.

The plurality of unit devices may be symmetrically disposed with respect to a horizontal center line of the array chip. In particular, the plurality of unit elements is preferably four.

The array chip includes a first sheet in which a first conductor pattern is formed across both opposing ends in the lateral direction, and a second sheet in which a second conductor pattern is formed across both opposing ends in the longitudinal direction. The first sheet and the second sheet are stacked on each other, both opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are connected to a third external terminal. Can be connected. In this case, the third conductor pattern further includes a third sheet formed in a predetermined overlap region between the first conductor pattern and the second conductor pattern, and a third sheet is disposed between the first sheet and the second sheet. Can be stacked.

The array chip includes a first sheet in which a first conductor pattern is formed across two opposite ends in a lateral direction, and a second conductor pattern in which two areas having different areas in a longitudinal direction are formed across both opposite ends. A sheet, wherein the first sheet and the second sheet are stacked, and opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposing regions of the second conductor pattern, respectively. One end may be connected to each of the third external terminals.

In contrast, the array chip comprises first and second regions spaced apart from each other at opposite ends of the transverse direction, and a first region formed from a third region spaced apart from these regions and intersecting the longitudinal direction therebetween. A second conductor pattern including a first sheet having a sieve pattern and a fourth and fifth spaced apart region overlapping a portion of the first and third regions and overlapping a portion of the second and third regions; A second sheet formed, wherein the first sheet and the second sheet are stacked, one end of the first and second regions of the first conductor pattern is connected to first and second external terminals, respectively, Opposite ends of the third region may be connected to a third external terminal. In this case, the third conductor pattern includes a third sheet formed across the opposite ends in the lateral direction, and the fourth conductor pattern includes a fourth sheet formed across the opposite ends in the longitudinal direction, and the first sheet A fourth sheet is disposed between the second sheet and the third sheet, opposite ends of the third conductor pattern are connected to the first and second external terminals, respectively, and opposite ends of the fourth conductor pattern are respectively connected to the third outer Can be connected to the terminal.

The array chip includes a first sheet in which a first conductor pattern is formed across both opposing ends in the lateral direction, a second sheet in which a second conductor pattern is formed across both opposing ends in the longitudinal direction, and a third conductor pattern. A third sheet formed in the same direction as the first conductor pattern, and a fourth conductor pattern includes a fourth sheet formed in the same direction as the first conductor pattern, and the third sheet and the fourth sheet A second sheet is stacked between the sheets, and opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are connected to a third external terminal. And one opposite end of each of the third and fourth conductor patterns may extend to a corresponding one end of each sheet to be connected to the first and second external terminals, respectively.

The array chip includes a first sheet in which a first conductor pattern is formed across both opposing ends in the lateral direction, a second sheet in which a second conductor pattern is formed across both opposing ends in the longitudinal direction, and a third conductor pattern. And a third sheet formed in the same direction as the first conductor pattern, wherein a third sheet is laminated between the first sheet and the second sheet or between the second sheet and the second sheet, and the first sheet is laminated. Opposite ends of the conductor pattern are connected to first and second external terminals, respectively, opposing ends of the second conductor pattern are connected to third external terminals, and only one end of the third conductor pattern is seated. It can be connected to the first or second external terminal extending to one end of the.

The array chip includes a first sheet having a first conductor pattern transversely opposite opposite ends in a lateral direction, and a second sheet having a second conductor pattern spaced apart from both opposite ends in the same direction as the first conductor pattern. Wherein the first sheet and the second sheet are stacked, opposite ends of the first conductor pattern are connected to the first and second external terminals, and the second conductor pattern is connected to each other to form a third It can be connected to an external terminal. In this case, one end of the second conductor pattern is connected to each other and connected to a third external terminal, or an intermediate portion between both ends of the second conductor pattern is connected to each other and connected to a third external terminal, or the adjacent Opposite ends of the second conductor pattern may be connected to each other to be connected to the third external terminal.

The array chip comprises a first sheet having first and second conductor patterns spaced apart from each other on both opposite end sides in a lateral direction, and a second sheet having a third conductor pattern crossing both opposite ends in a longitudinal direction; The first sheet and the second sheet are stacked, one end of the first and second conductor patterns are connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are formed of a first sheet and a second sheet. 3 can be connected to each of the external terminals.

The array chip includes a first sheet having first and second conductor patterns spaced apart from each other on opposite sides of the transverse direction, and a third conductor pattern including first and second regions spaced apart from each other and formed in a longitudinal direction. A second sheet formed, wherein the first sheet and the second sheet are laminated, one end of the first and second conductor patterns is connected to first and second external terminals, respectively, and the third conductor One opposing end of the first and second regions of the pattern may be connected to each of two opposing third external terminals.

The array chip includes a first sheet in which a first conductor pattern is formed in a lateral direction, a second sheet in which a second conductor pattern is formed in a same direction as the first conductor pattern, and a third conductor pattern in a longitudinal direction. A third sheet formed across the opposite end, wherein a third sheet is laminated between the first sheet and the second sheet, and one end of the first conductor pattern is connected to any one of the first and second external terminals. And one end of the second conductor pattern is connected to the other of the first and second external terminals, and opposite ends of the third conductor pattern are connected to each of the third external terminals.

The array chip includes a first sheet having a first conductor pattern formed in a lateral direction, a second sheet having a second conductor pattern formed in the same direction as the first conductor pattern, and a third conductor pattern in a longitudinal direction. At least two third sheets formed across both opposing ends, wherein the third sheet is laminated between the first sheet and the second sheet and each opposite end of the first and second conductor patterns Is connected to the first and second external terminals extending to the corners of the corresponding one ends of each sheet, the one third conductor pattern has only one end connected to the third external terminals, and the other third Only one end of the conductor pattern may be connected to another third external terminal disposed to face the third external terminal.

The array chip includes a first sheet having a first conductor pattern formed in a lateral direction, a second sheet having a second conductor pattern formed in the same direction as the first conductor pattern, and a same direction as the first conductor pattern. A third sheet having a third conductor pattern spaced apart from corners at both opposite ends of the sheet, wherein the third sheet is disposed between the first sheet and the second sheet, and the first and second conductor patterns Each opposing one end of the sheet extends to the edge of the corresponding transverse one end of each sheet and is connected to the first and second external terminals, the third conductor pattern having one end connected to each other in longitudinal direction; At the end it can be connected to each of the third external terminals.

The array chip includes a first sheet having a first conductor pattern composed of first and second regions formed on the opposite sides of the transverse opposite sides, and a second conductor pattern overlapping a portion of the first and second regions. And a second sheet formed in the longitudinal direction, wherein the first sheet and the second sheet are laminated, and one end of the first and second regions of the first conductor pattern is connected to the first and second external terminals, respectively. The opposite ends of the second conductor pattern may be connected to each of the third external terminals. In this case, further comprising a third sheet having a first and a second through-hole formed to be spaced apart from each other in the transverse opposite end side, respectively, the third sheet is laminated on the laminated first sheet and the second sheet, A conductive paste may be filled in the first and second through holes to connect to the first and second regions, respectively, and the third sheet may overlap the first and second through holes to form a conductor pattern.

The array chip includes a first sheet having a first conductor pattern composed of first and second regions formed on the opposite sides of the transverse opposite sides, and a second conductor pattern overlapping a portion of the first and second regions. And a second sheet formed in the longitudinal direction and a third sheet in which the third conductor pattern is formed in the transverse direction, wherein the first, second and third sheets are laminated, and the first sheet of the first conductor pattern One end of the first and second regions is connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are connected to each of the third external terminals, and the amount of the third conductor pattern is Opposite ends may be connected to the first and second external terminals, respectively.

The array chip further includes a resistor sheet having a resistor pattern having both ends connected to the first and second external terminals of the corresponding unit device, respectively, or both ends of the first and second external devices of the corresponding unit device. The apparatus may further include an inductor sheet having an inductor pattern connected to the terminal.

The following describes a preferred embodiment of the present invention with reference to the drawings.

Example 1

In this embodiment, the equivalent inductance value can be freely produced to a desired value, and a plurality of unit elements having improved frequency characteristics such as noise removal and insertion loss are arranged in parallel to each unit for various stacked array chips made of one chip. Examples in which the present invention is applied to reduce the difference in frequency characteristics of the device are described. Hereinafter, a case in which four unit elements are manufactured by one chip will be described. The number of unit elements other than four will be discussed later.

1 shows a stacked array chip in which four capacitor elements are arranged in one chip and a manufacturing process thereof.

First, a desired molded sheet for a device is manufactured in the same manner as in the above-described conventional technique. This is also the same in the following examples. Referring to FIG. 1, in the first sheet 101, four first conductor patterns 110a to 110d are formed in parallel along the longitudinal direction, one for each device, and the first conductor patterns 110a to 110d that cross both opposite ends in the lateral direction. have. In this case, the first conductor patterns 110a to 110d are formed to be symmetrical with respect to the center line C-C in FIG. 1. In addition, the first conductor pattern 110a and the first conductor pattern 110b are formed close to each other, and the first conductor pattern 110c and the first conductor pattern 110d are formed close to each other. To this end, the first conductor patterns 110b and 110c are first conductor patterns 110a and 110c, respectively, rather than moving the first conductor patterns 110a and 110d toward the first conductor patterns 110b and 110c, respectively. It is preferable to move to 110d). That is, it is preferable that the first conductor pattern 110b and the first conductor pattern 110c disposed in the middle are disposed to be far from each other. Both ends of the first conductor patterns 110a to 110d of the first sheet 101 are connected to first and second external terminals 130 and 131 used as input / output terminals. A second outer conductor pattern 111 is formed in the second sheet 102 in the longitudinal direction intersecting the first conductor patterns 110a to 110d, and both ends thereof are used as a common terminal (ground). Is connected to the terminal 132. The laminate in which each sheet is laminated is cut after unnecessary parts, and as shown in FIG. 1B, the first and second conductor patterns 110a to 110d and 111 of the body are all formed. It is formed to be exposed to each end of the body. In order to remove all organic components such as various binders in the laminate, the laminate is heated at about 300 ° C. to bake out, and then the temperature is increased to obtain the laminate at an appropriate firing temperature (for example, about 1,100 ° C.). Fire. External terminals 130 to 132 connected to respective conductor patterns inside the laminate are formed outside the fired laminate to complete the stacked array chip. The external terminals are silver paste (Ag-paste) on a rubber disk (disc) grooved on the circumferential surface according to the number of electrodes to be formed (the number of external terminals printed on the side of the body, for example four) and the position thereof. It is formed by printing the electrode by closely rotating the disk to the body (dipping action) and then firing at an appropriate temperature (about 700 to 800 ℃).

At this time, the portion divided by the virtual line (two-dot chain line) in the drawing is to operate as one single element. The stacked array chip of this structure has a structure in which current flow crosses 90 degrees, which is called a feed-through capacitor. Such a three-terminal feedthrough capacitor has a higher self-resonant frequency than the conventional capacitor. In addition, the feed-through capacitor has a compact input / output terminal and a ground terminal in the same chip element, so that the insertion loss value for the high frequency noise can be increased. In fact, the 3-terminal feed-through stacked array chip is currently used in electronic circuits. have.

As such, in an array chip in which four plurality of unit elements 120a to 120d are arranged in parallel along the longitudinal direction in one element 120, since the array chip 120 is symmetrical with respect to the center line CC, The unit elements 120a and 120d on which the first conductor pattern 110a and the first conductor pattern 110d are formed have the same frequency characteristics. Furthermore, since the first conductor pattern 110a is formed close to each other with the first conductor pattern 110b and the first conductor pattern 110c is formed close to each other with the first conductor pattern 110d, The frequency characteristics of the unit elements 120a and 120b in which the first conductor pattern 110a and the first conductor pattern 110b are formed are similar, and the first conductor pattern 110c and the first conductor pattern 110d are similar. The difference in frequency characteristics between the formed unit elements 120c and 120d is reduced. In addition, since the unit element 120a is generally less affected by the unit element 120c than the unit element 120b, when the unit element 120b reduces the influence of the unit element 120c, The frequency characteristic difference between 120a) and unit element 120b is also reduced. Accordingly, as described above, the first conductor pattern 110b and the first conductor pattern 110c disposed in the middle are formed to be spaced apart from each other so that the frequency characteristic difference between the unit elements 120a and 120b is further increased. Will decrease.

2 is a structure in which two capacitors are connected in series by inserting a floating electrode between a signal electrode and a ground electrode of the device. On the sheet manufactured as described above, as shown in FIG. 2, a conductive pattern such as Ag, Pt, Pd or the like is printed by screen printing to form four unit elements 220a to 220d. This formed sheet is produced. That is, the first sheet 201 is formed by forming the first conductor patterns 210a to 210d crossing the opposite opposite ends of the sheet, and the longitudinal direction intersects the first conductor patterns 210a to 210d. To form a second conductor pattern 211 that crosses the sheet to form a second sheet 202, and to form a predetermined region between the first conductor patterns 210a to 210d and the second conductor pattern 211. The third sheet 203 is manufactured by forming third conductor patterns 212a to 212d as floating electrodes disposed and insulated from external terminals. In this case, the first conductor pattern 210b is formed closer to the first conductor pattern 210a and the first conductor pattern 210c is formed closer to the first conductor pattern 210d. In addition, the first conductor patterns 210a, 210b, 210c, and 210d are formed such that the unit elements 220a and 220b are symmetrical with the unit elements 220c and 220d. Similarly, in each of the third conductor patterns 212a to 212d, the third conductor pattern 212b is toward the third conductor pattern 212a and the third conductor pattern 212c is the third conductor pattern ( 212d), and the third conductor patterns 212a, 212b, 212c, and 212d are formed so that the unit elements 220a and 220b are symmetrical with the unit elements 220c and 220d.

As described above, the first to third sheets 201 to 203 on which the conductor patterns are formed are paired as many times as desired in the order of the first sheet 201, the third sheet 203, and the second sheet 202. The cover sheets 200 are stacked and stacked, that is, the number of sheets of the sheet is controlled to be stacked so as to have a desired capacitance value. After lamination, the laminate is crimped as described above, and cut, bake out, fire, and external terminal forming processes are performed to complete the laminated array chip.

In this case, the part divided by the virtual line in the drawing operates as one device. There is a region where the first conductor patterns 210a to 210d and the third conductor patterns 212a to 212d overlap, and the third conductor patterns 212a to 212d and the second conductor pattern 211 overlap. There is an area. Capacitance values are generated in the overlapped regions, respectively, to form a structure in which two capacitors are connected in series. Therefore, in the device shown in FIG. 2, since the first and third conductor patterns 210a to 210d and 212a to 212d are disposed up and down with the second conductor pattern 211 interposed therebetween, two capacitors may be provided on both sides. Becomes a structure connected in series.

In such an array chip, the unit elements 220a and 220d on which the first conductor pattern 210a and the first conductor pattern 210d are formed have the same frequency characteristics, and the unit on which the first conductor pattern 210a is formed. The frequency characteristics of the unit element 220b in which the element 220a and the first conductor pattern 210b are formed are similar, and the unit element 220c and the first conductor pattern 210d in which the first conductor pattern 210c is formed are similar. ), The difference in frequency characteristics between the unit elements 220d formed thereon is reduced.

3 is a structure in which a capacitance value can be variously changed by modifying a shape of a conductor pattern connected to a common terminal. On the sheet manufactured as described above, as shown in FIG. 3, a conductive pattern is formed by printing a conductive paste such that four unit elements 320a to 320d are formed. That is, the first sheet 301 is formed by forming a first conductor pattern 310 across both transverse opposite ends of the sheet, and the area in the transverse direction intersecting the first conductor patterns 310a to 310d. The second conductor pattern 311 formed of the first and second regions 311A and 311B different from each other is formed, and the first region 311A and the second region 311B are connected to each other at one end thereof so as to be connected to each other. The sheet 302 is manufactured. The first conductor pattern 310b is formed closer to the first conductor pattern 310a, and the first conductor pattern 310c is formed closer to the first conductor pattern 310d. In addition, the unit elements 320a and 320b in which the first conductor patterns 310a and 310b are formed are formed to be symmetrical with the unit elements 320c and 320d in which the first conductor patterns 310c and 310d are formed.

As described above, the first and second sheets 301 and 302 having the respective conductor patterns are alternately stacked in a desired number of pairs, and the cover sheets 300 are stacked thereon, that is, the desired capacitance values of the sheets are stacked. Lamination is carried out by adjusting the number of laminations. After lamination, the laminate is crimped as described above, and cut, bake out, fire, and external terminal forming processes are performed to complete the laminated array chip.

The first conductor patterns 310a to 310d and the second conductor pattern 311 overlap each other, and the second conductor pattern 311 is divided into first and second regions 311A and 311B having different areas. Therefore, the two overlapping regions overlapping the first conductor patterns 310a to 310d also have different areas. Therefore, the capacitance value is different in two overlapping areas having different areas. As described above, the chip device manufactured according to the process illustrated in FIG. 3A includes two capacitors having different capacitance values at the input terminal and the output terminal. Capacitors of this structure can be designed when capacitors with different capacities are required at the input and output terminals.

In such an array chip, the unit elements 320a and 320d on which the first conductor pattern 310a and the first conductor pattern 310d are formed have the same frequency characteristics, and the unit on which the first conductor pattern 310a is formed. The difference in frequency characteristics between the device 320a and the unit device 320b on which the first conductor pattern 310b is formed is reduced, and the unit device 320c and the first conductor pattern on which the first conductor pattern 310c is formed are reduced. The difference in frequency characteristics between the unit elements 320d in which the 310d is formed is also reduced.

Meanwhile, in the drawings and the specification so far, a, b, c, and d at the end of the reference numerals of the conductor patterns formed on the respective sheets represent four unit elements disposed in one array chip, respectively. c and d respectively correspond to the unit elements arranged in order on the left side of the drawing. After that, in order to simplify the drawings, the unit elements are distinguished by attaching a, b, c, and d only at the end of the reference numerals of the unit elements, and a, b, c, and d are not attached to the conductor patterns. . However, it should be noted that a, b, c, and d at the end of the reference numerals in the following description indicate each unit element even if not shown in the drawings.

FIG. 4A illustrates a structure in which a capacitance value can be variously changed by forming a conductor pattern connected to a signal input / output terminal and a conductor pattern connected to a common terminal on a same sheet, and forming a floating electrode conductor pattern on an upper portion or a lower portion. to be. On the sheet manufactured as described above, as illustrated in FIG. 4A, a conductive pattern is formed by printing a conductive paste such that four unit elements 420a to 420d are formed. That is, the first region 414 and the second region 415 formed to be spaced apart from each other in the transverse opposite ends of the manufactured sheet, respectively, and the directions that are spaced apart from these regions and connect the opposite ends therebetween. The first sheet 401 is manufactured by forming the first conductor pattern 410 including the third regions 416 that cross each other in the longitudinal direction. At this time, one end of the sheet end of the first region 414 and the second region 415 is connected to the first and second external terminals 430 and 431 which are input / output terminals, and the amount of the third region 416 The end portion is connected to a third external terminal 432 which is a common terminal. In addition, a fourth region 417 overlapping a portion of the first region 414 and the third region 416 of the first conductor pattern 410 of the first sheet 401, and the first sheet 401. The second conductor pattern 410 includes a third region 416 of the first conductor pattern 410 and a fifth region 418 overlapping a portion of the second region 415 and insulated from external terminals. 411 is formed to manufacture second sheet 402. A third conductor pattern 412 is formed across both opposing ends of the sheet to form a third sheet 403, and a fourth conductive layer crosses the sheet in a direction crossing the third conductor pattern 412. The sieve pattern 413 is formed to manufacture the fourth sheet 404.

In each sheet, the conductor patterns are formed such that the unit elements 420a and 420b are symmetrical with the unit elements 420c and 420d. In addition, the first and second regions 414b and 415b and the second and third conductor patterns 411b and 412b of the first conductor pattern formed in the unit element 420b are formed of the first element formed in the unit element 420a. The conductor patterns formed on the first and second regions 414a and 415a and the second and third conductor patterns 411a and 412a of the conductor pattern, and formed on the unit element 420c are also unit elements 420d. Is formed closer to the side of the conductor patterns formed.

As described above, the first to fourth sheets 401 to 404 and the cover sheets 400 having the respective conductive patterns are stacked as shown in FIG. 4A, and after the lamination, the laminate is compressed as described above. Cutting, bake-out, firing, and external terminal forming processes are performed to complete the stacked array chip.

At this time, unlike the above, the first to fourth sheets 401 to 404 having the respective conductor patterns formed thereon may be stacked in various combinations, and various stacked chips may be manufactured by stacking the cover sheet 400 on the top. have. For example, only the first and second sheets 401 and 402 are stacked one by one, the second sheet 402 is laminated up and down with respect to the first sheet 401, or the second sheet 402 is centered. The first sheet 401 may be stacked up and down, or the first and second sheets 401 and 402 may be alternately repeatedly stacked as many times as desired. These various lamination methods can achieve the desired capacitance value.

In such an array chip, the unit element 420a has the same frequency characteristic as that of the unit element 420d, and the unit element 420b has the same frequency characteristic as the unit element 420c, and the unit element 420a and the unit element ( The frequency characteristic difference between 420b is reduced, and the frequency characteristic difference between the unit element 420c and the unit element 420d is reduced.

In the first embodiment, the sheet is a varistor sheet, and when a part of the conductor pattern is replaced with a resistor pattern or a resistor sheet on which the resistor pattern is formed is further stacked, the resistor-varistor multilayer array chip in which the resistor and the varistor are combined is formed. When an abnormal voltage is applied between the devices, current flows directly to the common terminal to protect the devices.

An example of additionally forming a resistor pattern 452 on top of a body after stacking some sheets of the stacked array chip illustrated in FIG. 4A is illustrated in FIG. 4B. That is, in the stacked array chip 450 illustrated in FIG. 4B, the cover sheet 400, the first sheet 401, the second sheet 402, and the first sheet 401 are stacked in this order, and then pressed and cut. The baking is carried out and a baking process is performed to form a body. In the top cover sheet 400 of the calcined body, metal pads 451 are formed respectively at positions corresponding to the first and second external terminals 530 and 531, respectively, and the metal pads 451. A resistive paste such as Ni-Cr or RuO ₂ is printed in a direction connecting the metal pads 451 at both ends to form a resistive pattern 452 rather than a conductor pattern. Next, an insulator pattern 453 is formed to protect the pattern in a direction crossing the resistor pattern 452, and external terminals 430, 431, and 432 are formed to complete a stacked array chip. In the stacked array chip manufactured as described above, when the metal pads 451 are formed at both ends of the resistor pattern 452 to precisely adjust the distance between the metal pads 451, the resistance value may also be accurately adjusted. When the device is formed in a single chip, the resistance value of each unit device can be manufactured uniformly. In this case, as shown in FIG. 4B, in the array chip 450, the resistor patterns 452 may be disposed at the same positions as the conductor patterns formed in the unit device to be symmetrical to each other and close to each other to form external terminals. Can be. However, since the resistor pattern 452 does not significantly affect the difference in frequency characteristics between the unit elements, the resistor pattern 452 may be arranged at regular intervals. As described above, an example of forming a resistor pattern (or an inductor pattern) on the body is described as another example in the third embodiment.

In the above example, when the sheet is a PTC thermistor sheet or an NTC thermistor sheet, the stacked chip becomes a resistor-thermistor stacked chip to protect the device in the event of an overcurrent or sudden temperature change. Part of the conductor pattern may include a metal pattern such as Ag, Pt, or Pd to increase conductivity. This makes it possible to freely match the impedance of the circuit. On the other hand, as described above, the technology for manufacturing a stacked array chip may be fabricated as a stacked chip component device by changing the internal conductor pattern and the stacking order in addition to the above-described devices.

Example 2

In the second embodiment, examples in which the present invention is applied to various stacked array chips in which a plurality of unit devices capable of freely producing equivalent inductance values to a desired value are arranged in parallel and manufactured as one chip are described.

5 to 7 illustrate a stacked array chip capable of changing a value of an equivalent inductance according to a direction of a current applied to an input / output terminal, and a manufacturing process thereof. 5 to 7, the conductive pattern is formed by printing a conductive paste such that four unit elements 520a to 520d, 620a to 620d, and 720a to 720d are formed on the sheet manufactured as described above. To prepare. That is, the first sheet 501 having the first conductor pattern 510 formed to cross both opposite ends of the sheet, and the same transverse direction as the first conductor pattern 510 and spaced apart from both ends of the sheet. Second sheets 502, 602, and 702 on which second conductor patterns 511, 611, and 711 are formed are manufactured. Both ends of the first conductor pattern 510 are connected to first and second external terminals 530, 531, 630, 631, 730, and 731 which are input / output terminals.

As shown in FIG. 5, one end of the second conductor pattern 511 is divided into two parts in the unit chip, or as shown in FIG. 6, the center of the second conductor pattern 611 is two parts. Branched to the third external terminal 532 or 632 which is a common terminal (ground). In addition, as shown in FIG. 7, both ends of the second conductor pattern 711 are connected to the third external terminal 732 which is a common terminal (ground). In general, when a plurality of devices are manufactured in a single chip by forming a plurality of first and second conductor patterns in parallel on each sheet, each of the first conductor patterns 510 is a unit that is independent of each other. Although the element (indicated by a dotted line) is formed, the second conductor patterns 511, 611, and 711 are preferably connected to each other and to a common electrode (ground). That is, in the array chip 520 of FIG. 5, the second conductor pattern 511 formed in the same direction as the first conductor pattern 510 may be connected to each other at one end of the third conductor terminal 511. 532, and in the array chip 620 shown in FIG. 6, the second conductor pattern 611 is connected to the third external terminal 632 with the centers of the patterns connected to each other, and the array shown in FIG. 7. In the chip 720, one end of the second conductor pattern 711 opposite to each other is connected to the third external terminal 732.

In this case, for example, in the case of the array chip 520 illustrated in FIG. 5, the conductor patterns in each sheet are formed such that the unit elements 520a and 520b are symmetrical with the unit elements 520c and 520d. The conductor patterns 510b and 511b formed in the unit element 520b are formed closer to the conductor patterns 510a and 511a formed in the unit element 520a, and the conductor patterns formed in the unit element 520c are also unit elements. It is formed closer to the side of the conductor pattern formed at 520d. In the case of the array chips 620 and 720 illustrated in FIGS. 6 and 7, the conductor patterns in each unit element are arranged similarly to the above.

As described above, two first sheets and two second sheets on which each conductor pattern is formed are stacked on each other, and the cover sheet 500 is stacked thereon, and the sheets are pressed, pressed, cut, baked, baked, and external terminal forming. To complete the stacked array chip.

In the stacked array chip illustrated in FIG. 5, when current flows from the external terminal 530 toward the external terminal 531, the equivalent inductance becomes maximum because the direction of the current flowing in the signal line and the ground line is the same, and the external terminal ( When the current flows toward the external terminal 530 at 531, the equivalent inductance is minimized because the direction of the current flowing in the signal line and the ground line is reversed. The signal line refers to the conductor pattern 510 connected to the external terminals 530 and 531 which are input / output terminals (signal electrodes), and the ground line is connected to the external terminal 532 which is a common terminal (ground). It refers to a sieve pattern 511. In the multilayer array chip illustrated in FIG. 6, since the center of the second conductor pattern 611, which is a ground line, is connected to ground, current flows always toward the center of the second conductor pattern 611. Therefore, no matter how the current flows in the signal line, the maximum and minimum equivalent inductances are generated in one conductor pattern and cancel each other so that only the inductance of the center line of the second conductor pattern 611 exists. The multilayer array chip illustrated in FIG. 7 is designed such that the direction of the current flowing through the ground line is the same as the direction of the current flowing through the input / output terminal irrespective of the direction of the current applied to the input / output terminal, thereby increasing the value of the equivalent inductance, thereby inserting a loss. It has a low resonant frequency while maintaining the noise removal characteristics.

As described above, in the array chip illustrated in FIG. 5, the unit elements 520a and 520d have the same frequency characteristics, and the unit elements 520b and 520c have the same frequency characteristics, and the unit elements 520a and 520b have the same frequency characteristics. The difference in frequency characteristics between the units decreases, and the difference in frequency characteristics between the unit elements 520c and 520d decreases. This property is the same in the array chip shown in FIGS. 6 and 7.

In the second embodiment, the sheet is a varistor sheet, and the first conductor patterns 510, 610, and 710 may include a metal pattern such as Ag, Pt, or Pd to increase conductivity. In particular, in the present embodiment, when the first conductor pattern is replaced with a resistor pattern formed of Ni-Cr or RuO ₂ , the resistor-varistor stacked array chip may be used to freely match the impedance of the circuit. Of course, if the sheet is a PTC thermistor sheet or an NTC thermistor sheet, the chip becomes a resistor-thermistor stacked chip to protect the device in case of overcurrent or sudden temperature change.

Example 3

8A is an example of applying the present invention to a feedthrough capacitor described in the prior art.

On the sheet manufactured as described above, as shown in FIG. 8A, a conductive pattern is formed by printing a conductive paste such that four unit elements 820a to 820d are formed. That is, the first sheet 801 is formed by forming a first conductor pattern 810 that crosses the opposite ends of the sheet in the opposite direction, and both sides in the longitudinal direction that intersect the first conductor pattern 810. A second sheet 802 is formed by forming a second conductor pattern 811 across the end. The third conductor pattern 812 is formed in the same direction as the first conductor pattern 810, thereby manufacturing the third sheet 803, and the fourth conductor in the same direction as the first conductor pattern 810. The sieve pattern 813 is formed to manufacture the fourth sheet 804. As described above, the first to fourth sheets 801 to 804 having the respective conductor patterns are formed of the first sheet 801, the third sheet 803, the second sheet 802, the fourth sheet 804, and the first sheet. After stacking the two sheets 802 in this order, the sheets are pressed and then cut, baked, baked, and externally formed to form a stacked array chip. In this case, the conductor patterns in each sheet are formed so that the unit elements 820a and 820b are symmetrical with the unit elements 820c and 820d, and the conductor patterns 810b, 812b and 813b formed in the unit element 820b. The silver is formed closer to the conductor patterns 810a, 812a, and 813a formed on the unit elements 820a, and the conductor patterns formed on the unit elements 820c and 820d are formed to be close to each other. Accordingly, even in the array chip illustrated in FIG. 8A, the unit elements 820a and 820d have the same frequency characteristic, and the unit elements 820b and 820c have the same frequency characteristic, and the unit element 820a and the unit element 820b are the same. The frequency characteristic difference between the unit elements 820c and the unit element 820d is reduced.

Unlike those illustrated in FIG. 8A, the first to fourth sheets 801 to 804 on which the conductor patterns are formed have a desired capacitance value, for example, the first sheet 801 and the third sheet 803 as shown in FIG. 6. ), The second sheet 802, the third sheet 803, and the second sheet 802 may be stacked in this order. That is, the stacked array chip may be a chip device in which any one of the first and second sheets 801 and 802 and the third and fourth sheets 803 and 804 are stacked. It may be stacked in pieces to form a single chip. In this way, the capacitance value of the device may be adjusted by adjusting the number of stacked layers of the sheet.

In FIG. 8A, instead of forming a conductor pattern on the first sheet 801, a resistor pattern or an inductor pattern may be formed. In particular, when the firing temperature of the laminated sheet and the firing temperature of the resistor are different, in order to stably bake each element at an individual firing temperature, the laminate obtained by laminating the sheet having the conductor pattern formed thereon without laminating the sheet having the resistor pattern formed thereon is fired. And a resistor pattern is formed on the cover sheet, and then firing may be performed again at the firing temperature of the resistor.

As an example of this, FIGS. 8B to 8H show a desired number of first to third sheets 806 to 808 having conductor patterns similar to those of the second to fourth conductor patterns 817 to 816 illustrated in FIG. 8A. And a modification in which a resistive pattern (FIGS. 8B and 8C) or an inductor pattern (FIGS. 8E to 8H) is formed on the cover sheet 800 after laminating in a desired order, further stacking the cover sheet 800.

On the sheet manufactured as described above, a first conductor pattern 815 is formed in a direction crossing both opposite transverse ends of the sheet to produce a first sheet 805, and the first conductor pattern 815. The second sheet 806 is manufactured by forming the second conductor pattern 816 in the same direction. The third sheet 807 is manufactured by forming a third conductor pattern 817 crossing both opposing ends in the longitudinal direction crossing the first conductor pattern 815.

In the stacked array chip 840 illustrated in FIG. 8B, the cover sheet 800, the first sheet 805, the third sheet 807, and the second sheet 806 are stacked in this order, compressed, cut, and baked. Out and baking process is performed, and a body is formed. In the top cover sheet 800 of the calcined body, metal pads 841 which occupy a predetermined area are formed at positions corresponding to the first and second external terminals 830 and 831, respectively, and on the metal pads 841. The resistive pattern 842 is formed by printing a resistive paste such as RuO _{2 in} the direction connecting the metal pads 841 at both ends thereof. Next, an insulator pattern 843 is formed to protect the pattern in a direction crossing the resistor pattern 842, and external terminals 830, 831, and 832 are formed to complete a stacked array chip. In the stacked array chip manufactured as described above, when the metal pads 841 are formed at both ends of the resistor pattern 842 to precisely adjust the distance between the metal pads 841, the resistance value may also be accurately adjusted. When the device is formed in a single chip, the resistance value of each unit device can be manufactured uniformly.

The stacked array chip 850 illustrated in FIG. 8C includes a cover sheet 800, a first sheet 805, a modified third sheet 807A, a modified third sheet 807B, a second sheet 806, The second sheet 806, the deformed third sheet 807B, the deformed third sheet 807A, and the first sheet 805 are laminated in this order, and then pressed, cut, baked out, and baked. Form the body. The deformed third sheets 807A and 807B extend to the edge of the sheet so that only one end thereof is connected to only one of the external terminals 832, which are two ground terminals, and the other end is spaced apart from the edge of the sheet. The third conductor patterns 817A and 817B are formed. In the cover sheet 800 of the top of the calcined body, a metal pad 851 is formed in the same manner as in FIG. 8B and a resistor pattern 852 is formed to connect them. An insulator pattern 853 is then formed, and external terminals 830, 831, and 832 are formed to complete the stacked array chip.

The stacked array chip 860 illustrated in FIG. 8D is an example in which a conductor pattern used as a common terminal in the stacked array chip 850 illustrated in FIG. 8C is modified. That is, the stacked array chip 860 illustrated in FIG. 8D may include a cover sheet 800, a first sheet 805, a modified third sheet 807, a first sheet 805, a second sheet 806, The deformed third sheet 807C and the second sheet 806 are laminated in this order, and then pressed, and the cut, bake out, and calcining processes are performed to form a body. Here, the third conductor patterns 817 and 817C are formed in the deformed third sheets 807 and 807C in the same transverse direction as the first and second conductor patterns 815 and 816. The third conductor patterns 817 and 817C are spaced apart from both ends of the sheet and have one end branched into two parts to be connected to the third external terminal 832, which is a common terminal. In the cover sheet 800 of the top of the calcined body, a metal pad 861 is formed in the same manner as in FIG. 8B and a resistor pattern 862 is formed to connect them. Next, an insulator pattern 863 is formed, and external terminals 830, 831, and 832 are formed to complete a stacked array chip. At this time, since the conductor patterns formed on the upper first and third sheets 805 and 807 have a wider width than the lower second and third sheets 806 and 807C, the upper first sheet 805 When the formed conductor pattern, that is, the conductor pattern connected to the external terminal 831, is used as the input terminal, the capacitance and the equivalent inductance value of the input terminal capacitor are larger than the output terminal capacitor, so that the magnetic pattern appears twice by two capacitance values. The spacing between the resonant frequencies is wider, which makes the noise rejection frequency band even wider.

In the stacked array chip 870 illustrated in FIG. 8E, the cover sheet 800, the first sheet 805, the third sheet 807, and the second sheet 806 are stacked in this order, compressed, cut, and baked. Out and baking process is performed, and a body is formed. The ferrite pattern 871 is printed on the top cover sheet 800 of the fired body, and then the inductor pattern 872 is formed. The inductor pattern 872 may be a helical pattern, and after forming an insulator paste 873 connecting the end of the sheet at the center axis end to extend the center axis end outward, and then on the insulator paste 873. The crosslinking pattern 874 may be formed on the substrate. After forming the insulator pattern 875 to protect the inductor pattern 872 on the inductor pattern layer as described above, external terminals 830, 831, and 832 connected to the inductor pattern 872 and the conductor pattern. ) To form a stacked array chip.

The stacked array chip 880 illustrated in FIG. 8F sequentially laminates the first sheet 805, the third sheet 807, and the second sheet 806, and then inductor pattern 818A on the first sheet 805. To 818C), the inductor sheets 808A to 808C such as the ferrite sheet are formed, and the cover sheet 800 is laminated again. The laminate is completed into a stacked array chip through compression, cutting, bake out, firing, and external terminal forming processes as described above. At this time, both ends of the inductor pattern 818A extend to the formed perforation hole 818E of the sheet and one end edge of the sheet, and are formed in a predetermined shape, for example, a "c" shape. The inductor pattern 818C extends to the formed perforation hole 818E of the sheet and the other end edge of the sheet, and is formed in a "c" shape in the opposite direction to the inductor pattern 818A. The inductor pattern 818B is formed in a "c" shape so that both ends extend into the two formed perforation holes 818E of the sheet. When the perforation holes of each inductor sheet are filled with a conductor, the inductor patterns 818A to 818C become one inductor pattern connected to each other, one for each unit element. At this time, the desired inductance value can be easily obtained by adjusting the number of inductor sheets. Although the inductor pattern is manufactured in the winding type, the inductor pattern may be modified in various ways such as the linear inductor patterns 818F to 818H as illustrated in FIG. 8G.

In this case, as shown in FIGS. 8B to 8G, when the resistor pattern or the inductor pattern is disposed in the same position as the conductor pattern formed in the unit device, the conductor pattern and the resistor pattern or the inductor pattern are exposed to the body side. The parts may be aligned in a straight line to easily form the first and second external terminals. However, such a resistor pattern or an inductor pattern may be formed at equal intervals because they do not significantly affect the difference in frequency characteristics between unit elements.

The stacked array chip 890 illustrated in FIG. 8H is an example in which an inductor pattern is added in a manner different from that described above, and the first sheet 805, the third sheet 807, and the second sheet 806 are sequentially formed. After stacking, the inductor sheets 809A to 809D, such as ferrite sheets, are stacked on the first sheet 805 by the number corresponding to the number of unit elements, and the cover sheet 800 is stacked again. The laminate is completed into a stacked array chip through compression, cutting, bake out, firing, and external terminal forming processes as described above. At this time, the inductor patterns 819A to 819D are formed on the inductor sheets 809A to 809D. That is, the first inductor sheet 809A configured to form a meander inductor pattern 819A on the sheet and both ends of the inductor pattern are located in the unit element 890a. In the same manner as above, the meander inductor patterns 819B to 819D are formed. At this time, both ends of each inductor pattern are spaced apart from each other so as to be individually located in each unit element. Since the stacked array chip 890 illustrated in FIG. 8H uses an inductor pattern for the entire sheet, the inductance value can be increased and the desired inductance value can be easily obtained. In addition, in the present exemplary embodiment, one inductor pattern is formed in one inductor sheet. However, if necessary, one or more inductor patterns may be formed in one inductor sheet. It can be laminated on the top and bottom can also be laminated. In the above, the inductor pattern is manufactured in a meander type, but the inductor pattern may be modified in various ways such as a spiral straight line.

Example 4

In the present embodiment, a plurality of unit elements capable of freely producing capacitance, resistance, and inductance to a desired value are arranged in parallel to reduce the difference in frequency characteristics between each unit element for various stacked array chips made of one chip. Examples of applying the present invention are described.

First, in order to manufacture the array chip shown in FIG. 10 as an example thereof, a conductive pattern is printed by printing a conductive paste such that four unit elements 1020a to 1020d are formed on a sheet manufactured as in Example 1 described above. The formed sheet is prepared. That is, the first sheet 1001 is manufactured by forming the first and second conductor patterns 1010 and 1011 spaced apart from the opposite sides of the sheet, respectively, and intersect with the directions connecting the opposite ends. The second sheet 1002 is manufactured by forming the third conductor pattern 1012 in the longitudinal direction. In this case, the widths of the first and second conductor patterns 1010 and 1011 may be formed differently as shown in FIG. 10A. In this case, the conductor patterns in each sheet are formed so that the unit elements 1020a and 1020b are symmetrical with the unit elements 1020c and 1020d, and the conductor patterns 1010b and 1011b formed in the unit element 1020b are united. The conductive patterns 1010a and 1011a formed in the element 1020a are formed closer to each other, and the conductive patterns formed in the unit element 1020c are also formed closer to the conductive patterns formed in the unit element 1020d.

As described above, the first and second sheets 1001 and 1002 having the respective conductor patterns are alternately stacked, as shown in FIG. 10, and the cover sheet 1000 is stacked thereon. In addition, in the present embodiment, the first and second sheets 1001 and 1002 are stacked one by one in order to have a desired capacitance value, but the sheets may be stacked in plural in various combinations to form a single chip to adjust the capacitance value. These laminates are compressed, then cut, baked out, and fired. In this case, a device may be manufactured by forming an external terminal connected to each conductor pattern in the stack, and further, a resistance component may be further coupled as described below.

In the cover sheet 1000 of the uppermost body of the calcined body, metal pads 1040 are formed respectively at positions corresponding to the first and second external terminals 1030 and 1031, respectively, and the metal pads 1040 are formed. A resistive pattern 1050 is formed by printing a resistive paste such as RuO _{2 in} a direction connecting the metal pads 1040 at both ends thereof. Next, an insulator pattern 1060 is formed to protect the pattern in a direction crossing the resistor pattern 1050, and external terminals 1030, 1031, and 1032 are formed to complete a stacked array chip. In the stacked array chip manufactured as described above, when the metal pads 1040 are formed at both ends of the resistor pattern 1050 to precisely adjust the distance between the metal pads 1040, the resistance value may also be accurately adjusted. When the device is formed in a single chip, the resistance value of each unit device can be manufactured uniformly. In this case, the resistor pattern 1050 of FIG. 10 may be disposed at the same position as the conductor pattern formed in the unit element or at equal intervals.

Meanwhile, as illustrated in FIG. 11, the second sheet 1002 includes a first region 1112A and a second region 1112B which are spaced apart from each other and formed in a direction intersecting with a direction connecting the opposite ends. The second sheet 1102 having the conductor pattern 1112 may be replaced with the second sheet 1102. In this case, opposing one ends of the first and second regions 1112A and 1112B of the third conductor pattern 1112 are exposed to the outside so that the third external terminal 1133 and the third external terminal ( 1132 is formed to be connected. At this time, the chip element of the present embodiment has a similar characteristic to that of the stacked array chip illustrated in FIG. 10 in that the capacitors having the values of C1 and C2 are connected to common terminals at both ends of the resistor pattern 1150, but the first conductor pattern is shown in FIG. By separating the common terminal pattern used by the 1010 and the common terminal pattern used by the second conductor pattern 1011, C1 and C2 may implement frequency characteristics without mutual interference.

As described above, in the array chip illustrated in FIG. 10, the unit element 1020a and the unit element 1020d have the same frequency characteristic, and the unit element 1020b and the unit element 1020c have the same frequency characteristic, The frequency characteristic difference between the 1020a and the unit element 1020b is reduced, and the frequency characteristic difference between the unit element 1020c and the unit element 1020d is reduced. This characteristic is the same in the array chip shown in FIG.

Example 5

In this embodiment, examples of applying the present invention to various stacked array chips manufactured by combining various electronic elements such as a plurality of resistance components and varistor components in a single chip will be described. In particular, various resistor pattern forming methods are described in this embodiment.

12A illustrates a through-hole electrode type resistive varistor composite array chip device and a manufacturing process thereof. A varistor sheet is manufactured in the same manner as in Example 1 described above, and a sheet on which the conductor pattern is formed is printed by printing a conductive paste such that four unit elements 1220a to 1220d are formed thereon. That is, the first sheet 1201 is formed with first conductor patterns 1208 and 1209, which are connected to the outer side terminals and spaced apart from each other, respectively, and the second sheet 1202 is connected between the respective unit elements and both ends thereof. On the long side of the unit element, a second conductor pattern 1210 is formed which is connected to the external terminal for the common terminal. At this time, the first varistor is composed of the first conductor pattern 1208 and the second conductor pattern 1210 at one end, and the first conductor pattern 1209 and the second conductor pattern 1210 at the other end. The second varistor is constructed. A plurality of such first and second varistors are arranged side by side, for example, four by one to form an array. In addition, the through-hole 1211 is formed in a predetermined molded sheet manufactured as described above using a perforator, and a conductive paste such as Ag metal is printed and filled in the formed through-hole to manufacture a third sheet 1203. In this case, the conductor patterns and the through-holes in each sheet are formed so that the unit elements 1220a and 1220b are symmetrical with the unit elements 1220c and 1220d, and the conductor patterns 1209b and 1210b formed in the unit element 1220b. ) And through-holes 1211b are formed close to the conductor patterns 1209a and 1210a and through-holes 1211a formed in the unit element 1220a, and the conductor patterns and through-holes formed in the unit element 1220c are also unit elements. It is formed closer to the conductor pattern and through hole formed in 1220d.

The first and second sheets 1201 and 1202 manufactured as described above are alternately stacked as many times as desired, and the third sheet 1203 having a through electrode formed thereon is stacked as many as desired, and then compressed and cut. The chips cut as described above are baked and baked out at a suitable temperature to remove all of the various binder and organic components in the chip. At this time, debinder is performed at around 300 ° C. using an electric oven of hot air type for effective bake out. As described above, the chips from which the binder and the organic material are removed are fired using an electric furnace of 1100 ° C. or higher to manufacture a varistor array chip body.

The resistive pattern 1221 is printed for each unit element by using a resistive paste such as RuO ₂ on the calcined body as described above. In this case, the resistor patterns 1221 are also arranged at positions corresponding to the conductor patterns 1209 and 1210 in the drawing. Alternatively, the resistor patterns 1221 may be arranged at equal intervals. This resistor is connected to the conductor pattern through a paste filled in the through hole. The resistor printed as described above is fired at a temperature of about 800 to 900 ° C. and forms external terminals 1230 to 1232. A plurality of side external terminals formed at both ends of the unit element corresponding to each unit element are formed by applying a silver paste to the grooved rubber disc and rotating the disc. The external terminal electrode formed as described above is heat-treated at a temperature of about 700 to 800 ° C., and a protective layer 1222 such as epoxy or glass is applied to protect the surface of the resistor from an external environment such as moisture, and then heat-treated at an appropriate temperature. A varistor composite array chip is manufactured.

Such a composite array chip is a typical π-type RC (resistance-capacitor) filter structure, and the varistor has a characteristic of acting as a capacitor (C) when a rated voltage is applied, which is a normal operating voltage instead of an overvoltage. The π-type filter serves to remove various high frequency noises included in the signal source. In addition, when an overvoltage including static electricity is applied instead of the normal operating voltage, the varistor immediately acts as an overvoltage blocking function, which is the original function of the varistor, thereby protecting semiconductor ICs and various electronic components connected to the output terminal. In particular, symmetry is performed between the unit elements so that the unit element 1220a has the same frequency characteristic as that of the unit element 1220d, and the unit element 1220b has the same frequency characteristic as the unit element 1220c. In addition, the unit elements disposed in the middle are disposed close to both end side unit elements, so that the difference in frequency characteristics between the unit element 1220a and the unit element 1220b is reduced, and between the unit element 1220c and the unit element 1220d. The difference in frequency characteristics of is also reduced.

Fig. 12B shows a resistor varistor composite array chip device of a resistor direct printing method. A plurality of varistor-forming sheets are produced in the same manner as in the above example, and then the first and second sheets are manufactured. The first and second sheets 1201 and 1202 manufactured are alternately stacked as many times as desired, and then the cover sheet 1200 is covered thereon and pressed, and a cutting, baking out, and baking process is performed.

In the top cover sheet 1200 of the calcined body, metal pads 1241 are respectively formed at predetermined positions at positions corresponding to the first and second external terminals 1230 and 1231, respectively, and the metal pads 1241 are formed. A resistive pattern 1242 is formed by printing a resistive paste such as RuO _{2 in} a direction connecting the metal pads 1241 at both ends thereof. Next, an insulator pattern 1243 is formed to protect the pattern in a direction crossing the resistor pattern 1242, and external terminals 1230, 1231, and 1232 are formed to complete the stacked array chip.

12A and 12B, the method of manufacturing a composite chip by firing the varistor element and then printing the resistor is more complicated than the simultaneous firing method of simultaneously firing the resistor and the varistor (example below), but the firing of the varistor is performed. If the temperature and the firing temperature of the resistor is different, there is an advantage that each element can be stably fired at an individual firing temperature.

Fig. 12C shows a resistive varistor array type composite chip device in a cofired manner. In the same manner as described above, the first and second sheets 1201 and 1202 are manufactured. In addition, by using a resistive paste having a high firing temperature using a resistive paste having RuO ₂ or RuO ₂ as a basic component on the manufactured predetermined sheet, a resistor pattern 1211 is printed for each unit element by a screen printing method to form a third sheet 1204. To prepare. In this case, the resistor pattern 1211 is formed to be connected to side external terminals at both ends of the unit element.

The first, second, and third sheets 1201, 1202, and 1204 manufactured as described above are laminated as many as desired, and then the cover sheet 1200 is covered thereon and pressed, cut, bake out, fired, and external terminals. A formation process is performed. At this time, by controlling the number of the laminated sheet of each device portion, it is possible to implement a variety of desired characteristics, that is, capacitance or resistance. At this time, the varistor and the resistor are simultaneously fired using the electric furnace having the binder and the organic material removed as described above by using an electric furnace of 1100 ° C. or higher to manufacture a resistive varistor array chip. In this case, the firing temperature of the varistor and the resistor should be controlled. That is, by using a resistor paste baked at 1100 ° C. or higher, which is the firing temperature of a general varistor composition, the varistor and the resistor are simultaneously baked near 1100 ° C., or a varistor composition is baked at 850 ° C., which is a firing temperature of a RuO ₂ resistor. The varistor and the resistor should be fired at the same time near 850 ℃. Simultaneous firing of the resistive varistor as described above has the advantage that the manufacturing method is simple compared to the method of manufacturing a composite chip by printing the resistor after firing the varistor laminated body presented in the example of this embodiment.

The technique for manufacturing each resistive varistor composite array chip manufactured as described above is applied to a capacitor, an NTC thermistor, a PTC element, and the like in addition to the above-described elements. That is, instead of laminating the varistor elements, the capacitors, NTC thermistors, and PTC elements are laminated. This is produced by forming a sheet having a conductive pattern for each conductive pattern is formed into a sheet for the device, and then using a conductive paste in the sheet for each device in the same manner as in the above embodiment.

Until now, an array chip in which four unit elements are arranged side by side in one chip has been described. In an array chip in which four or more unit elements are arranged, when the conductor pattern is formed such that each unit element is symmetrical with respect to the center of the array chip, the unit elements arranged on the left and right sides from the center have the same frequency characteristic. In addition, when unit elements are arranged in pairs closer to each other and they are disposed at a greater distance from other pairs, the frequency characteristic difference between the unit elements in each pair is reduced while being not electrically affected by other pairs of unit elements. . Therefore, although the above embodiments have been described with respect to an array chip in which four unit elements are arranged side by side in one chip, the present invention is not limited thereto, and the present invention may be applied to an array chip in which four or more unit elements are arranged. Of course.

As described above, in an array chip in which a plurality of unit elements are arranged in parallel in one element, since each unit element is symmetrical with respect to the center of the array chip, the unit elements arranged on both sides from the center have the same frequency characteristics. . Furthermore, the conductor patterns in the paired unit elements are arranged adjacent to each other so that the difference in frequency characteristics between these unit elements is reduced. In particular, since these pairs are spaced apart from each other at regular intervals and do not electrically influence each other, the frequency characteristic difference between the unit elements of each pair is further reduced.

1 to 6 are manufacturing process diagrams of various stacked array chips according to Embodiment 1 of the present invention.

7A to 9 are manufacturing process diagrams of various stacked array chips according to Embodiment 3 of the present invention.

10 to 19 are manufacturing process diagrams of various stacked array chips according to Embodiment 4 of the present invention.

12A to 12C are manufacturing process diagrams of various stacked array chips according to Embodiment 3 of the present invention.

13A is a manufacturing process diagram of a conventional stacked array chip.

13B is a graph showing the frequency characteristics of the conventional stacked array chip shown in FIG. 13A.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 400, 500: cover sheet

101, 201, 301, 401, 501: first sheet

102, 202, 302, 402, 502, 602: second sheet

203, 403, 503: third sheet

404, 504: fourth sheet

110, 210, 310, 410, and 510: first conductor pattern

111, 211, 311, 411, and 511: second conductor pattern

212a to 212d, 412, and 512: third conductor pattern

413, 513: fourth conductor pattern

120, 220, 320, 420, 520: body

130, 130, 330, 430, 530: first external terminal

131, 131, 331, 431, 531: second external terminal

132, 132, 332, 432, 532: third external terminal

Claims (24)

A third external terminal that is a common terminal to the other opposite opposing ends disposed in parallel along the longitudinal direction, a plurality of unit elements having a first and a second external terminal formed at both opposite ends in parallel to the opposite direction of the opposite ends In the array chip is formed, Each of the unit elements includes a conductor pattern formed in the transverse direction, And the conductor patterns formed on one unit element are arranged close to the conductor patterns formed on adjacent unit elements to form a pair, and the pairs are arranged with a predetermined distance therebetween. The array chip of claim 1, wherein the plurality of unit elements are disposed symmetrically with respect to a transverse centerline of the array chip. The array chip of claim 2, wherein the plurality of unit devices is four. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern formed transversely across both opposing ends, The second conductor pattern comprises a second sheet formed across the opposite ends in the longitudinal direction, The first sheet and the second sheet are stacked on each other, both opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are third external. Array chip, characterized in that connected to the terminal. The method according to claim 4, The third conductor pattern further includes a third sheet formed in a predetermined overlapping region between the first conductor pattern and the second conductor pattern, And a third sheet stacked between the first sheet and the second sheet. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern formed across both opposite transverse ends, A second conductor pattern consisting of two regions having different areas in the longitudinal direction comprising a second sheet formed across both opposing ends, The first sheet and the second sheet are stacked, and opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposite ends of each region of the second conductor pattern are formed of a first sheet and a second sheet. Array chip, characterized in that connected to each of the three external terminals. The method according to any one of claims 1 to 3, A first conductor pattern having a first conductor pattern comprising first and second regions spaced apart from each other on opposite sides of the transverse direction, and a third region spaced apart from these regions and formed in a direction crossing the longitudinal direction therebetween With sheets, A second sheet having a second conductor pattern formed of spaced apart fourth and fifth regions overlapping portions of the first and third regions and overlapping portions of the second and third regions, The first sheet and the second sheet are laminated, one ends of the first and second regions of the first conductor pattern are connected to the first and second external terminals, respectively, and opposite ends of the third region are And an array chip connected to the third external terminal. The method according to claim 7, wherein the third conductor pattern is formed with the third sheet formed across the opposite ends in the transverse direction, The fourth conductor pattern comprises a fourth sheet formed across the opposite ends in the longitudinal direction, A fourth sheet is disposed between the first sheet and the third sheet, and opposite ends of the third conductor pattern are connected to the first and second external terminals, respectively, and opposite ends of the fourth conductor pattern are respectively And an array chip connected to the third external terminal. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern formed transversely across both opposing ends, A second sheet in which a second conductor pattern is formed across both opposing ends in the longitudinal direction; The third conductor pattern comprises a third sheet formed in the same direction as the first conductor pattern, A fourth conductor pattern includes a fourth sheet formed in the same direction as the first conductor pattern, A second sheet is stacked between the third sheet and the fourth sheet, and opposite ends of the first conductor pattern are connected to first and second external terminals, respectively, and opposite to the second conductor pattern. An end is connected to a third external terminal, and each opposite end of the third and fourth conductor patterns extends to a corresponding one end of each sheet and is connected to the first and second external terminals, respectively. Array chip made. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern formed transversely across both opposing ends, A second sheet in which a second conductor pattern is formed across both opposing ends in the longitudinal direction; The third conductor pattern comprises a third sheet formed in the same direction as the first conductor pattern, A third sheet is laminated between the first sheet and the second sheet or between the second sheet and the second sheet, and opposite ends of the first conductor pattern are connected to the first and second external terminals, respectively. And opposite ends of the second conductor pattern are connected to a third external terminal, and only one end of the third conductor pattern extends to one end of the sheet and is connected to the first or second external terminal. Array chip. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern formed transversely across both opposing ends, A second sheet having a second conductor pattern spaced apart from both opposing ends in the same direction as the first conductor pattern, The first sheet and the second sheet are stacked, opposite ends of the first conductor pattern are connected to the first and second external terminals, and the second conductor pattern is connected to each other and connected to the third external terminal. Array chip, characterized in that. The array chip of claim 11, wherein one end of the second conductor pattern is connected to each other to be connected to a third external terminal. The array chip of claim 11, wherein an intermediate portion between both ends of the second conductor pattern is connected to each other to be connected to a third external terminal. The array chip of claim 11, wherein opposite ends of the adjacent second conductor pattern are connected to each other and to a third external terminal. The method according to any one of claims 1 to 3, A first sheet having first and second conductor patterns spaced apart from each other on opposite sides of the transverse direction; A third conductor pattern in the longitudinal direction comprising a second sheet formed across both opposing ends, The first sheet and the second sheet are stacked, one end of the first and second conductor patterns are connected to first and second external terminals, respectively, and opposite ends of the second conductor pattern are third Array chip, characterized in that connected to each of the external terminals. The method according to any one of claims 1 to 3, A first sheet having first and second conductor patterns spaced apart from each other on opposite sides of the transverse direction; A second sheet spaced from each other and having a third conductor pattern composed of a first region and a second region formed in a longitudinal direction, The first sheet and the second sheet are stacked, one end of the first and second conductor patterns are connected to first and second external terminals, respectively, and the first and second regions of the third conductor pattern. And one opposite end of the array chip is connected to each of two third external terminals disposed opposite. The method according to any one of claims 1 to 3, A first sheet in which a first conductor pattern is formed in a transverse direction, A second sheet in which a second conductor pattern is formed in the same direction as the first conductor pattern; A third conductor pattern in the longitudinal direction comprising a third sheet formed across both opposing ends, A third sheet is stacked between the first sheet and the second sheet, one end of the first conductor pattern is connected to one of the first and second external terminals, and one end of the second conductor pattern is And an opposite end of the third conductor pattern is connected to each of the third external terminals, the second chip being connected to the other of the first and second external terminals. The method according to any one of claims 1 to 3, A first sheet on which a first conductor pattern formed in a lateral direction is formed; A second sheet in which a second conductor pattern is formed in the same direction as the first conductor pattern; A third conductor pattern in the longitudinal direction comprising at least two third sheets formed across both opposing ends, The third sheet is laminated between the first sheet and the second sheet, and each opposite end of the first and second conductor patterns extends to the corner of the corresponding one end of each sheet so as to extend the first and second sheets. 2 external terminals, the one third conductor pattern having only one end connected to the third external terminal, and the other third conductor pattern having only one end disposed opposite the third external terminal. And an array chip connected to another third external terminal. The method according to any one of claims 1 to 3, A first sheet in which a first conductor pattern is formed in a transverse direction, A second sheet in which a second conductor pattern is formed in the same direction as the first conductor pattern; A third sheet having a third conductor pattern spaced apart from corners of opposite ends of the sheet in the same direction as the first conductor pattern, The third sheet is disposed between the first sheet and the second sheet, and each opposite end of the first and second conductor patterns extends to an edge of a corresponding transverse one end of each sheet. And a third conductor pattern, one end of which is connected to each other and connected to each of the third external terminal at both ends in the longitudinal direction. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern composed of first and second regions spaced apart from each other in opposite transverse ends, respectively; A second conductor pattern overlapping a portion of the first and second regions comprises a second sheet formed longitudinally,  The first sheet and the second sheet are stacked, one ends of the first and second regions of the first conductor pattern are connected to the first and second external terminals, respectively, and opposite to the second conductor pattern. And the end is connected to each of the third external terminals. The method of claim 20, A third sheet having first and second through-holes spaced apart from each other in opposite transverse ends, respectively; A third sheet is stacked on top of the stacked first sheet and the second sheet, and a conductive paste is filled in the first and second through holes to connect with the first and second regions, respectively. An array chip, wherein the conductor pattern is formed by overlapping the first and second through holes. The method according to any one of claims 1 to 3, A first sheet having a first conductor pattern composed of first and second regions spaced apart from each other in opposite transverse ends, respectively; A second sheet having a second conductor pattern overlapping a portion of the first and second regions in a longitudinal direction, Further comprising a third sheet in which the third conductor pattern is formed in the transverse direction, The first, second and third sheets are stacked, one ends of the first and second regions of the first conductor pattern are connected to first and second external terminals, respectively, and the second conductor patterns Both opposing ends are connected to each of the third external terminals, and both opposing ends of the third conductor pattern are respectively connected to the first and second external terminals. The method according to any one of claims 1 to 3, And a resistor sheet having resistive patterns formed at both ends thereof to be connected to the first and second external terminals of the corresponding unit elements, respectively. The method according to any one of claims 1 to 3, And an inductor sheet having an inductor pattern having both ends connected to first and second external terminals of corresponding unit elements, respectively.