KR100487632B1 - Inspection method of multiple faults of DRAM - Google Patents

Abstract

The present invention relates to a multi-failure inspection method of a DRAM, and in the conventional technique, the binary inspection method includes a double failure in a memory array and a double failure in a memory array and a peripheral circuit as shown in FIG. 2. There was a problem that a pass judgment was received instead of a failure judgment.

Accordingly, the present invention has been made to solve the above-mentioned conventional problem, and provides a method for detecting a double failure by recording different data (repair value) in a memory cell, whereby the detection in the binary inspection method is prevented. It is possible to detect impossible double faults and multiple faults, and there is an effect of simply inspecting by an operation of an inspection program in an external inspection apparatus without any change of a conventional inspection circuit.

Description

Multi-Fault Inspection Method of DRAM

The present invention relates to a multi-failure inspection method of a DRAM, and more particularly, to a multi-failure detection test method for a multi-failure detection of a DRAM for detecting double and multi-failures that may occur in a dynamic RAM (DRAM) circuit.

FIG. 1 is a circuit diagram showing an embodiment of a conventional test circuit configuration. As shown therein, a memory array 10, a plurality of sense amplifiers 11 and 12, a plurality of main amplifiers 13 and 14, An inspection unit 15; It is composed of the input / output buffer 16. The binary test method used in the DRAM is as follows.

The same data ('1' or '0') is written to all memory cells, and data of two or more selected addresses are read and compared in the memory cells.

In this case, the output of the main amplifier 13 is not directly connected to the input / output buffer 16, but is compared with two or more main amplifiers 14 and then connected to the input / output buffer 16.

If the data read and compared are equal to each other, the output value becomes high ('1'), and the input / output buffer 16 outputs a high state (pass: pass), and if the data are different from each other, the output value is low ('0'). ') The Ip pull force buffer 16 outputs a low state (failure: FAIL).

2A and 2B are diagrams for describing a case where a pass decision is generated instead of a fault determination even when a double failure in a memory array and a double failure occurs in a memory array and a peripheral circuit, respectively.

As is well known, a fail test of a memory device is performed by comparing and checking whether the data is normally output after applying the same data, and the binary check method described herein is substantially the same. Thus, for example, a double failure (FIG. 2A) in a memory array is a memory cell in which all data (high level (or all low level)) is applied to the memory cell array, and then data is read and compared at different positions. If all are changed to low level (or all high level) in the array, even if they are read out and compared, they cannot be checked because they are all compared at the same level. Because). The same is true for Figure 2b, which describes double faults in the memory array and the peripheral circuits.

As described above, in the conventional technique, the binary inspection method receives a pass determination instead of a failure determination even when a double failure in the memory array and a double failure in the memory array and the peripheral circuit occur as shown in FIG. There was this.

Accordingly, an object of the present invention is to provide a method for detecting a double failure by writing different data (repair value) in a memory cell.

In order to achieve the above object, the multi-failure inspection method of the present invention includes a first step of writing the same data in all memory cells, and reading and comparing data of a plurality of selected addresses from the memory cells; A second step of determining that a failure occurs when the data compared in the first step is different from each other and ending the inspection; A third step of writing different data again in a memory cell to be compared if the data compared in the first step are the same, and reading and comparing data of a plurality of selected addresses in the memory cell; If the data compared in the third step is different from each other, it is determined as a pass, on the contrary it is characterized in that the fourth step of determining the failure, and ends the inspection.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 3 is a test sequence table for detecting a double failure by using the multi-failure inspection method of the present invention DRAM, Figure 4 is a schematic diagram showing a double failure to detect using the multi-failure inspection method of the present invention DRAM As shown in the drawing, first, a test for detecting a single failure is performed in the same manner as the conventional method, and if no failure is detected, the same data ('1' or '0') is applied to all memory cells in order to detect a double failure. Write, read and compare data of a plurality of selected addresses in a memory cell, and if the compared data is different from each other, the output of the main amplifier goes low to determine a failure, terminates the inspection, and compares the data If the data are identical to each other, different data is written to the memory cells to be compared again, and the plurality of selected addresses are stored in the memory cells. The data is read again and compared. If the data is different from each other, the output of the main amplifier goes low. In this case, the output of the main amplifier is determined to be a pass because the output is normal. The inspection is concluded as a failure.

As described above, the multi-failure inspection method of the present invention enables the detection of double and multi-failures that cannot be detected by the binary inspection method, and the operation of the inspection program from an external inspection device without changing the conventional inspection circuit. Simple test is effective.

1 is a circuit diagram showing an embodiment of a conventional test circuit configuration.

Figure 2 is an exemplary view briefly showing a double failure not detectable in the conventional inspection circuit.

Figure 3 is a test sequence table for detecting a double failure using the multi-failure inspection method of the present invention DRAM.

Figure 4 is an exemplary view showing a double failure to detect using the multi-failure inspection method of the present invention DRAM.

*** Description of the symbols for the main parts of the drawings ***

10: memory array 11, 12: sense amplifier

13, 14: main amplifier 15: inspection unit

16: I / O buffer

Claims (1)

A first step of writing the same data in all the memory cells, and reading and comparing data of a plurality of selected addresses in the memory cells; A second step of determining that a failure occurs when the data compared in the first step is different from each other and ending the inspection; A third step of writing different data again in a memory cell to be compared if the data compared in the first step are the same, and reading and comparing data of a plurality of selected addresses in the memory cell; And a fourth step of determining a pass if the data compared in the third step is different, and a failure if the same is the same, and terminating the test.

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