KR100482461B1 - Method for manufacturing polysilicon thin film transistor - Google Patents
Method for manufacturing polysilicon thin film transistor Download PDFInfo
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- KR100482461B1 KR100482461B1 KR10-1998-0045462A KR19980045462A KR100482461B1 KR 100482461 B1 KR100482461 B1 KR 100482461B1 KR 19980045462 A KR19980045462 A KR 19980045462A KR 100482461 B1 KR100482461 B1 KR 100482461B1
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- polysilicon
- thin film
- film transistor
- laser beam
- manufacturing
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- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title abstract description 21
- 239000010408 film Substances 0.000 claims abstract description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 239000012297 crystallization seed Substances 0.000 claims abstract description 14
- 238000005224 laser annealing Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
Abstract
본 발명은 폴리 실리콘 채널을 형성하기 위한 레이져 어닐링 공정시, 균일한 그레인 사이즈를 갖으면서 그레인간 돌출부가 없은 채널을 갖는 폴리실리콘-박막 트랜지스터의 제조방법을 개시한다. 개시된 본 발명은 비정질 실리콘막을 레이져 어닐링하여 폴리실리콘화하는 단계를 포함하는 폴리실리콘-박막 트랜지스터의 제조방법에 있어서, 상기 박막 트랜지스터가 형성되는 비정질 실리콘막의 양끝단 내부, 하부 또는 상부에 결정화시드를 형성하고, 레이져 빔을 인가하되, 레이져 빔인가시, 레이져 빔을 중첩시키지 않고, 레이져 빔 폭만큼 쉬프트하여 조사하는 것을 특징으로 한다.The present invention discloses a method for producing a polysilicon-thin film transistor having a channel having a uniform grain size and no inter-grain protrusions in a laser annealing process for forming a polysilicon channel. Disclosed is a method of manufacturing a polysilicon-thin film transistor comprising laser annealing an amorphous silicon film to form polysilicon, wherein a crystallization seed is formed on both ends, bottom, or top of an amorphous silicon film on which the thin film transistor is formed. The laser beam is applied, but when the laser beam is applied, the laser beam is shifted and irradiated by the laser beam width without overlapping the laser beam.
Description
본 발명은 폴리실리콘-박막 트랜지스터의 제조방법에 관한 것으로, 보다 구체적으로는, 폴리실리콘-박막트랜지스터의 채널층 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a polysilicon thin film transistor, and more particularly, to a method for manufacturing a channel layer of a polysilicon thin film transistor.
일반적으로 폴리실리콘을 채널층으로 이용하는 폴리실리콘-박막 트랜지스터는 비정질 실리콘을 채널층으로 하는 박막 트랜지스터와 비교하였을 때, 소형화가 가능하고, 빠른 구동 능력을 가진다.In general, a polysilicon-thin film transistor using polysilicon as a channel layer can be miniaturized and has a fast driving capability as compared with a thin film transistor using amorphous silicon as a channel layer.
또한, 액정 표시 장치에 적용하였을 경우에는, 얇고 작은 모듈을 형성하여, 컴팩트한 디스플레이 장치를 구현할 수 있고, 드라이브 IC와 박막 트랜지스터가 동시에 형성되므로써, 비용도 감축된다.In addition, when applied to a liquid crystal display device, a thin and small module can be formed to implement a compact display device, and the cost is reduced by forming a drive IC and a thin film transistor at the same time.
여기서, 폴리실리콘-박막 트랜지스터를 제조하는데 있어서 중요한 공정은 증착시 비정질 실리콘막이었던 채널층을 폴리실리콘막으로 변형시키기 위한 결정화 공정이다. Here, an important process in manufacturing a polysilicon-thin film transistor is a crystallization process for transforming a channel layer, which was an amorphous silicon film during deposition, into a polysilicon film.
종래에는 이러한 결정화 기술로 고상 결정화법과 레이져 어닐링법이 있는데, 그중 레이져 어닐링법이 일반적으로 이용되었다.Conventionally, such crystallization techniques include a solid phase crystallization method and a laser annealing method, among which a laser annealing method is generally used.
그러나, 상기와 같은 레이져 어닐링 방법에 의하여 폴리실리콘화하는 방법은 대면적 패널에 적용할 경우 여러 샷(shot)의 레이져 빔이 인가되므로, 균일한 그레인 사이즈를 갖는 폴리실리콘을 형성하기 어렵다.However, in the method of polysilicon by the laser annealing method as described above, it is difficult to form polysilicon having a uniform grain size since the laser beam of several shots is applied when applied to a large area panel.
이러한 문제점을 해결하기 위하여 종래의 다른 방법으로는 레이져 빔을 호모지니어(homogenier)에 의하여 확장시키어 기판에 스캐닝하는 기술이 제안되었다.In order to solve this problem, as another conventional method, a technique of expanding a laser beam by a homogenier and scanning it on a substrate has been proposed.
그러나, 상기 방법은 레이져 빔이 길어지게 되므로써 중첩 부분이 발생되는데, 이 부분에서 그레인간 경계면에 공기가 들어가서 돌출부가 발생된다. However, in this method, the overlapping portion is generated as the laser beam is lengthened, in which air enters the interface between the grains and the protrusion is generated.
따라서, 본 발명의 목적은, 폴리 실리콘 채널을 형성하기 위한 레이져 어닐링 공정시, 균일한 그레인 사이즈를 갖으면서 그레인간 돌출부가 없은 채널을 갖는 폴리실리콘-박막 트랜지스터의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for manufacturing a polysilicon-thin film transistor having a channel having a uniform grain size and no inter-grain protrusions in a laser annealing process for forming a polysilicon channel.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 견지에 따르면, 비정질 실리콘막을 레이져 어닐링하여 폴리실리콘화하는 단계를 포함하는 폴리실리콘-박막 트랜지스터의 제조방법에 있어서, 상기 박막 트랜지스터가 형성되는 비정질 실리콘막의 양끝단 내부, 하부 또는 상부에 결정화 시드를 형성하고, 레이져 빔을 인가하되, 레이져 빔인가시, 레이져 빔을 중첩시키지 않고, 레이져 빔 폭만큼 쉬프트하여 조사하는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to one aspect of the present invention, in the method of manufacturing a polysilicon-thin film transistor comprising the step of laser annealing an amorphous silicon film polysilicon, wherein the thin film transistor is formed Crystallization seeds are formed inside, under, or on both ends of the amorphous silicon film, and the laser beam is applied. When the laser beam is applied, the laser beam is shifted and irradiated by the laser beam width without overlapping the laser beam.
이때, 상기 결정화 시드는 금속막으로 형성됨이 바람직하다. In this case, the crystallization seed is preferably formed of a metal film.
본 발명에 의하면, 폴리실리콘-박막 트랜지스터의 폴리실리콘 채널층 제조 공정을 위한 레이져 어닐링 공정시, 박막 트랜지스터 예정 영역 양 끝에 결정화 시드를 형성한다음, 레이져 빔을 중첩시키지 않고 한 샷의 레이져 빔을 결정화 시드 사이에 인가하여 준다. 이에따라, 균일한 그레인 사이즈를 갖으며, 그레인간 돌출부가 없는 폴리실리콘 채널을 형성하게 된다. According to the present invention, in the laser annealing process for the polysilicon channel layer manufacturing process of the polysilicon thin film transistor, crystallization seeds are formed at both ends of the predetermined region of the thin film transistor, and then one shot of the laser beam is crystallized without overlapping the laser beam. Apply between seeds. This results in the formation of polysilicon channels with uniform grain size and no intergrain projections.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 1a 내지 도 1d는 본 발명의 일실시예에 따른 폴리실리콘-박막 트랜지스터의 채널층 제조방법을 설명하기 위한 각 공정별 단면도이고, 도 2은 본 발명에 따른 결정화 시드가 배치된 평면도이다. 또한, 도 3 및 도 4는 본 발명에 따른 다른 실시예를 설명하기 위한 단면도이다.1A to 1D are cross-sectional views of respective processes for explaining a method of manufacturing a channel layer of a polysilicon thin film transistor according to an embodiment of the present invention, and FIG. 2 is a plan view of a crystallization seed according to the present invention. to be. 3 and 4 are cross-sectional views illustrating another embodiment according to the present invention.
도 1a를 참조하여, 기판 보호용 절연막(2)을 포함하는 글래스 기판(1) 상부에 수소화된 비정질 실리콘막(3: a-si:H)을 예정된 두께만큼 증착한다. Referring to FIG. 1A, a hydrogenated amorphous silicon film 3: a-si: H is deposited on the glass substrate 1 including the insulating film 2 for protecting the substrate by a predetermined thickness.
그리고나서, 도 1b에 도시된 바와 같이, 비정질 실리콘막(3) 상부에 결정화 시드용 금속막을 수십 Å 두께로 증착한다. 이어, 이 금속막을 폴리실리콘-트랜지스터로 한정된 영역 양 끝단에만 존재하도록 패터닝하여, 금속 패턴(4a,4b)을 형성한다. 이때, 금속 패턴(4a,4b)이 배열된 형태가 도 2에 나타내져 있다. 도 2에서와 같이 소정 간격 이격된 한 쌍의 금속 패턴(4a,4b)이 일정한 규칙을 가지고 배열되어 있다. Then, as shown in FIG. 1B, a metal film for crystallization seed is deposited on the amorphous silicon film 3 to a thickness of several tens of micrometers. Subsequently, the metal film is patterned to exist only at both ends of the region defined by the polysilicon transistor, thereby forming the metal patterns 4a and 4b. At this time, the form in which the metal patterns 4a and 4b are arranged is shown in FIG. As shown in Fig. 2, the pair of metal patterns 4a and 4b spaced by a predetermined interval are arranged with a certain rule.
그후, 도 1c에 도시된 바와 같이, 금속 패턴(4a,4b)을 마스크로 하여 레이져 빔을 인가하여 어닐링한다. 여기서, 상기 어닐링 공정시, 레이져 빔을 중첩시키지 않고, 레이져 빔 폭만큼 쉬프트하여 조사하면, 박막 트랜지스터 영역 양 끝단의 금속 패턴(4a,4b)이 결정화 시드로 작용하게 되어, 균일한 그레인을 갖도록 결정화시키게 된다. 즉, 레이져 빔을 중첩시키지 않고, 하나의 박막 트랜지스터 영역의 한 샷의 레이져 빔이 인가되도록 하여, 중첩 부위에서 발생되는 돌출부를 없애면서, 균일한 사이즈의 그레인을 갖는 채널층을 형성하게 된다. 또한, 금속 패턴(4a,4b)이 박막 트랜지스터 예정 영역의 양 끝단에 존재하므로, 실제적으로 채널 부위만 폴리실리콘화 된다. Thereafter, as shown in FIG. 1C, the laser beam is applied and annealed using the metal patterns 4a and 4b as masks. Here, in the annealing process, if the laser beam is shifted and irradiated by the laser beam width without overlapping, the metal patterns 4a and 4b at both ends of the thin film transistor region act as crystallization seeds to crystallize to have uniform grain. Let's go. That is, the laser beam of one shot of one thin film transistor region is applied without overlapping the laser beam, thereby forming a channel layer having grains of uniform size while eliminating protrusions generated at the overlapping portion. In addition, since the metal patterns 4a and 4b exist at both ends of the thin film transistor predetermined region, only the channel portion is actually polysiliconized.
그후, 도 1d에 도시된 바와 같이 금속 패턴(4a,4b)를 공지의 방식으로 제거하여, 균일한 그레인을 갖으며 돌출부가 없는 결정화된 폴리실리콘막(3a)을 얻는다.Thereafter, as shown in FIG. 1D, the metal patterns 4a and 4b are removed in a known manner to obtain a crystallized polysilicon film 3a having uniform grains and no protrusions.
또한, 본 발명은 상기 일 실시예에 국한되지 않고, 도 3과 같이, 비정질 실리콘막(3)내부에 도핑법을 이용하여 결정화 시드용 금속 패턴(4a,4b)을 형성하거나, 또는 도 4와 같이, 비정질 실리콘막(3)을 형성하기 전에 절연막(2) 표면에 금속 패턴(4a,4b)을 형성하여도 동일한 효과를 거둘수 있다.In addition, the present invention is not limited to the above embodiment, and as shown in FIG. 3, the crystallization seed metal patterns 4a and 4b are formed in the amorphous silicon film 3 by using a doping method, or as shown in FIG. 4. Likewise, the same effect can be achieved by forming the metal patterns 4a and 4b on the surface of the insulating film 2 before the amorphous silicon film 3 is formed.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 폴리실리콘-박막 트랜지스터의 폴리실리콘 채널층 제조 공정을 위한 레이져 어닐링 공정시, 박막 트랜지스터 예정 영역 양 끝에 결정화 시드를 형성한다음, 레이져 빔을 중첩시키지 않고 한 샷의 레이져 빔을 결정화 시드 사이에 인가하여 준다. 이에따라, 균일한 그레인 사이즈를 갖으며, 그레인간 돌출부가 없는 폴리실리콘 채널을 형성하게 된다. As described in detail above, according to the present invention, in the laser annealing process for the polysilicon channel layer manufacturing process of the polysilicon-thin film transistor, crystallization seeds are formed at both ends of the thin film transistor predetermined region, and the laser beam is not overlapped. A laser beam of one shot is applied between the crystallization seeds. This results in the formation of polysilicon channels with uniform grain size and no intergrain projections.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1d는 본 발명에 따른 폴리실리콘-박막 트랜지스터의 채널층 제조방법을 설명하기 위한 각 공정별 단면도.1A to 1D are cross-sectional views of respective processes for explaining a method of manufacturing a channel layer of a polysilicon thin film transistor according to the present invention.
도 2은 본 발명에 따른 결정화 시드가 배치된 평면도.2 is a plan view in which a crystallization seed according to the present invention is disposed;
도 3 및 도 4는 본 발명에 따른 다른 실시예를 설명하기 위한 단면도.3 and 4 are cross-sectional views for explaining another embodiment according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 - 기판 2 - 기판 보호용 절연막1-Substrate 2-Insulation layer for substrate protection
3 - 비정질 실리콘막 3a - 폴리실리콘막 3-amorphous silicon film 3a-polysilicon film
4a,4b - 금속 패턴4a, 4b-metal pattern
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221017A (en) * | 1994-02-03 | 1995-08-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method |
| JPH09232584A (en) * | 1996-02-28 | 1997-09-05 | Sharp Corp | Method of manufacturing semiconductor device |
| KR19980017448A (en) * | 1996-08-30 | 1998-06-05 | 김광호 | Crystallization Method of Silicon Thin Film |
| KR19980031001A (en) * | 1996-10-30 | 1998-07-25 | 김광호 | Crystallization Method of Silicon Thin Film |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221017A (en) * | 1994-02-03 | 1995-08-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and manufacturing method |
| JPH09232584A (en) * | 1996-02-28 | 1997-09-05 | Sharp Corp | Method of manufacturing semiconductor device |
| KR19980017448A (en) * | 1996-08-30 | 1998-06-05 | 김광호 | Crystallization Method of Silicon Thin Film |
| KR19980031001A (en) * | 1996-10-30 | 1998-07-25 | 김광호 | Crystallization Method of Silicon Thin Film |
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