KR100480604B1 - Method for fabricating shallow well of semiconductor device by low energy implantation - Google Patents
Method for fabricating shallow well of semiconductor device by low energy implantation Download PDFInfo
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- KR100480604B1 KR100480604B1 KR10-2002-0043698A KR20020043698A KR100480604B1 KR 100480604 B1 KR100480604 B1 KR 100480604B1 KR 20020043698 A KR20020043698 A KR 20020043698A KR 100480604 B1 KR100480604 B1 KR 100480604B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000002513 implantation Methods 0.000 title description 2
- 238000005468 ion implantation Methods 0.000 claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 150000004767 nitrides Chemical class 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 27
- 239000012535 impurity Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Abstract
저에너지 이온주입을 이용한 반도체 소자의 쉘로우 웰 형성방법을 개시한다. 본 발명에 따른 웰 형성방법에서는, 웰 이온주입시 저에너지 높은 도우즈(low energy high dose)를 사용하여 웰 영역의 깊이를 트렌치형 소자분리막 정도의 깊이에 형성한다. 이로써, 웰 영역의 수직적 스케일링(scaling)을 통하여 웰간 마진을 확보하고 웰 저항을 감소시킬 수 있다. A shallow well forming method of a semiconductor device using low energy ion implantation is disclosed. In the well forming method according to the present invention, the depth of the well region is formed at the depth of the trench type isolation layer using low energy high dose during well ion implantation. As a result, the inter-well margin may be secured and the well resistance may be reduced through vertical scaling of the well region.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 반도체 소자의 웰을 고집적화에 유리하게 형성하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for advantageously integrating wells of semiconductor devices.
반도체 제품에서의 웰은 실제 동작하는 MOS 소자에 몸체 전압(body voltage)을 전달해주며 충돌 이온화(impact ionization)에 의해 생성된 캐리어들을 빼주는 역할을 한다. 웰이 이러한 역할을 수행하도록 하기 위해서는 웰 이온주입시 많은 양의 도우즈를 투입해서 낮은 저항을 유지하도록 하여야 한다. 특히 랫치업(latch-up)과 같은 신뢰성 테스트 항목에서는 낮은 웰 저항이 절대적으로 중요한 역할을 하게 된다. 따라서, 낮은 저항을 유지하기 위해 고에너지 이온주입을 이용하여 깊은 웰을 형성하고 있다. 그러나, 고에너지 이온주입은 웰간의 마진을 줄이게 된다. Wells in semiconductor products deliver the body voltage to the MOS devices in operation and subtract the carriers generated by impact ionization. In order for the well to perform this role, a large amount of dose should be added during well ion implantation to maintain low resistance. Especially in reliability test items such as latch-up, low well resistance plays an important role. Therefore, in order to maintain low resistance, high energy ion implantation is used to form a deep well. However, high energy ion implantation reduces the margin between wells.
한편, 반도체 제품의 집적화에 따라 게이트 길이 및 활성영역의 폭 등은 수평방향으로 스케일링(scaling)이 이루어져 왔다. 그러나 이러한 수평방향으로의 스케일링에 대한 웰 구조의 수직적인 스케일링은 상대적으로 적었으며 이로 인해 웰간의 마진 부족은 더욱 심각해져 칩 크기 감소에 제약을 받게 되었다. Meanwhile, according to the integration of semiconductor products, the gate length, the width of the active region, and the like have been scaled in the horizontal direction. However, the vertical scaling of the well structure relative to this horizontal scaling is relatively small, which makes the margin gap between the wells more severe and constrained by chip size reduction.
그러나, 종래의 고에너지 이온주입 방법을 그대로 이용하면서 웰 깊이를 얕게 형성할 경우 저항 증가가 우려되며, 이러한 증가는 소자 구동시 래치업과 같은 오동작을 유발하게 된다. 또한 셀 어레이 영역에서의 웰 깊이는 SER(soft error rate)과도 밀접한 관련이 있음은 잘 알려진 사실이다. However, if the well depth is formed shallowly while using the conventional high energy ion implantation method as it is, an increase in resistance is concerned, and this increase causes a malfunction such as latch-up when driving the device. It is also well known that the well depth in the cell array region is closely related to the soft error rate (SER).
본 발명이 이루고자 하는 기술적 과제는 웰 영역의 수직적 스케일링을 통하여 웰간의 마진을 확보할 수 있고 저저항을 가지는 웰 형성방법을 제공하는 것이다. SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a well forming method capable of securing a margin between wells through vertical scaling of a well region and having a low resistance.
상기 기술적 과제를 달성하기 위하여 본 발명에서는 저에너지 이온주입을 이용하여 저저항의 웰을 형성하는 방법을 제안하고자 한다. 저에너지 이온주입을 통한 웰 형성은 불순물 확산에 의한 웰 마진 손실 및 두꺼운 감광막의 수축(shrinkage)에 의한 웰 마진 손실을 최소화할 수 있다. In order to achieve the above technical problem, the present invention proposes a method for forming a low resistance well using low energy ion implantation. Well formation through low energy ion implantation can minimize well margin loss due to impurity diffusion and well margin loss due to shrinkage of the thick photoresist layer.
이상적인 웰 구조는 웰 깊이는 가능한 얕게 형성하면서 웰 저항 측면에서는 고에너지 높은 도우즈의 웰과 같은 정도의 저항을 확보하여야 한다. 따라서, 본 발명에 따른 웰 형성방법에서는, 반도체 기판 내에 소자분리용 트렌치를 형성한 다음, 상기 트렌치의 바닥에 저에너지 높은 도우즈(low energy high dose)의 이온주입을 실시하여 고농도 웰을 형성한다. 상기 트렌치를 절연막으로 매립하여 상기 고농도 웰 위로 소자분리막을 형성하고, 상기 소자분리막을 포함한 반도체 기판 전면에 저에너지의 이온주입을 실시하여 상기 고농도 웰의 상부와 오버랩되는 깊이까지 저농도 웰을 형성한다.The ideal well structure should be as shallow as possible, while ensuring the same resistance as the wells of high energy doses in terms of well resistance. Therefore, in the well forming method according to the present invention, a device isolation trench is formed in a semiconductor substrate, and low energy high dose ions are implanted into the bottom of the trench to form a high concentration well. The trench is filled with an insulating layer to form a device isolation layer over the high concentration well, and low energy ion implantation is performed on the entire surface of the semiconductor substrate including the device isolation layer to form a low concentration well to a depth overlapping the upper portion of the high concentration well.
본 발명의 일 실시예에 따르면, 반도체 기판에 패드 질화막을 형성한 다음, 상기 패드 질화막을 식각마스크로 사용하여 상기 반도체 기판을 식각함으로써 상기 반도체 기판 내에 소자분리용 트렌치를 형성한다. 상기 트렌치의 내벽에 질화막 스페이서를 형성하고, 상기 패드 질화막과 질화막 스페이서를 이온주입 마스크로 사용하는 저에너지 높은 도우즈의 이온주입을 실시하여 상기 트렌치의 바닥에 고농도 웰을 형성한다. 상기 고농도 웰 위로 절연물질을 덮고 상면을 평탄화한 다음 상기 패드 질화막을 제거하여, 상기 트렌치를 매립하는 소자분리막을 형성한다. 이어서, 상기 반도체 기판 전면에 저에너지의 이온주입을 실시하여 상기 고농도 웰의 상부와 오버랩되는 깊이까지 저농도 웰을 형성한다. 고농도 웰과 저농도 웰을 합친 전체 웰의 깊이는 트렌치형 소자분리막 정도의 깊이에 해당되고, 따라서 쉘로우 웰이라 칭할 만 한다. 특히 소자분리막 바로 아래에 고농도 웰이 형성된다. 이상과 같은 실시예에 따라, 웰 영역의 수직적 스케일링을 통하여 웰간 마진을 확보하고 웰 저항을 감소시킬 수 있다. According to an embodiment of the present invention, after forming a pad nitride film on the semiconductor substrate, the trench for device isolation is formed in the semiconductor substrate by etching the semiconductor substrate using the pad nitride film as an etching mask. A nitride spacer is formed on the inner wall of the trench, and a low energy high dose ion implantation using the pad nitride layer and the nitride spacer as an ion implantation mask is performed to form a high concentration well at the bottom of the trench. An insulating material is covered over the high concentration well, the top surface is planarized, and the pad nitride layer is removed to form an isolation layer filling the trench. Subsequently, low energy ion implantation is performed on the entire surface of the semiconductor substrate to form a low concentration well up to a depth overlapping the upper portion of the high concentration well. The depth of the entire well combined with the high concentration well and the low concentration well corresponds to the depth of the trench type isolation layer, and thus may be called a shallow well. In particular, a high concentration well is formed directly under the device isolation film. According to the exemplary embodiment as described above, the inter-well margin may be secured and the well resistance may be reduced by vertical scaling of the well region.
본 발명의 다른 실시예에서는 CMOS용 웰을 형성한다. 이를 위해서, 반도체 기판을 PMOS 영역과 NMOS 영역으로 나눈 다음, 상기 반도체 기판에 패드 질화막을 형성한다. 상기 패드 질화막을 식각마스크로 사용하여 상기 반도체 기판을 식각함으로써 상기 반도체 기판의 PMOS 영역과 NMOS 영역 내에 소자분리용 트렌치들을 형성한다. 상기 트렌치들의 내벽에 질화막 스페이서를 형성한다. 상기 NMOS 영역쪽만 노출시키는 1차 감광막을 형성한 다음, 상기 패드 질화막과 질화막 스페이서를 이온주입 마스크로 사용하는 저에너지 높은 도우즈의 이온주입을 실시하여 상기 NMOS 영역의 트렌치 바닥에 P+ 웰을 형성한다. 상기 1차 감광막을 제거한 다음, 상기 PMOS 영역쪽만 노출시키는 2차 감광막을 형성하고, 상기 패드 질화막과 상기 질화막 스페이서를 이온주입 마스크로 사용하는 저에너지 높은 도우즈의 이온주입을 실시하여 상기 PMOS 영역의 트렌치 바닥에 N+ 웰을 형성한다. 상기 2차 감광막을 제거한 다음, 상기 P+ 웰과 N+ 웰 위로 절연물질을 덮고 상면을 평탄화한 후 상기 패드 질화막을 제거하여, 상기 트렌치를 매립하는 소자분리막을 형성한다. 상기 NMOS 영역쪽만 노출시키는 3차 감광막을 형성한 후, 상기 소자분리막을 포함한 반도체 기판 전면에 저에너지의 이온주입을 실시하여 상기 NMOS 영역에 상기 P+ 웰의 상부와 오버랩되는 깊이까지 P 웰을 형성한다. 상기 3차 감광막을 제거한 다음, 상기 PMOS 영역쪽만 노출시키는 4차 감광막을 형성하고, 상기 소자분리막을 포함한 반도체 기판 전면에 저에너지의 이온주입을 실시하여 상기 PMOS 영역에 N+ 웰의 상부와 오버랩되는 깊이까지 N 웰을 형성한다. 끝으로, 상기 4차 감광막을 제거한다. 본 실시예에 따르면, 저에너지 이온주입을 실시하므로 상기 1차 내지 4차 감광막은 웰 마진을 확보할 수 있는 정도의 얇은 두께로 형성할 수 있다. In another embodiment of the present invention, a well for CMOS is formed. To this end, the semiconductor substrate is divided into a PMOS region and an NMOS region, and then a pad nitride film is formed on the semiconductor substrate. The semiconductor substrate is etched using the pad nitride layer as an etching mask to form trenches for device isolation in the PMOS region and the NMOS region of the semiconductor substrate. Nitride spacers are formed on inner walls of the trenches. After forming a primary photoresist film exposing only the NMOS region, P + wells are formed in the trench bottom of the NMOS region by performing ion implantation of a low energy high dose using the pad nitride layer and the nitride spacer as an ion implantation mask. . After removing the primary photoresist film, a secondary photoresist film is formed to expose only the PMOS region side, and a low energy high dose ion implantation using the pad nitride film and the nitride film spacer as an ion implantation mask is performed to perform the implantation of the PMOS region. Form N + wells in the bottom of the trench. After removing the secondary photoresist layer, an insulating material is covered on the P + well and the N + well, the top surface is planarized, and the pad nitride layer is removed to form an isolation layer filling the trench. After forming a tertiary photoresist film exposing only the NMOS region, low energy ion implantation is performed on the entire surface of the semiconductor substrate including the device isolation layer to form a P well in the NMOS region to a depth overlapping the upper portion of the P + well. . After removing the tertiary photoresist film, a fourth photoresist film is formed to expose only the PMOS region, and low energy ion implantation is performed on the entire surface of the semiconductor substrate including the device isolation layer to overlap the upper portion of the N + well in the PMOS region. Form N wells up. Finally, the fourth photosensitive film is removed. According to the present embodiment, since the low energy ion implantation is performed, the first to fourth photosensitive films may be formed to have a thin thickness enough to secure a well margin.
이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예들을 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 따라서, 도면에서의 요소의 형상 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면 상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.
(제1 실시예)(First embodiment)
도 1 내지 도 6은 본 발명의 제1 실시예에 따른 쉘로우 웰 형성방법을 설명하기 위한 공정단면도들이다. 1 to 6 are process cross-sectional views illustrating a shallow well forming method according to a first embodiment of the present invention.
도 1을 참조하면, 반도체 기판(100)에 패드 질화막(110)을 형성한 다음, 이를 식각마스크로 사용하여 반도체 기판(100)을 2500 내지 3000Å 정도 식각하여 반도체 기판(100) 내에 소자분리용 쉘로우 트렌치(120)를 형성한다. 경우에 따라서는, 패드 질화막(110)과 반도체 기판(100) 상에 버퍼 산화막(미도시)을 열산화법으로 형성하여 개재시킬 수도 있다. Referring to FIG. 1, a pad nitride film 110 is formed on a semiconductor substrate 100, and then the semiconductor substrate 100 is etched by about 2500 to 3000Å by using the pad nitride film 110 as an etching mask. Form the trench 120. In some cases, a buffer oxide film (not shown) may be formed and thermally interposed on the pad nitride film 110 and the semiconductor substrate 100.
다음에 도 2에 도시한 것처럼, 트렌치(120)의 내벽과 바닥에 50Å ~ 100Å 정도 두께의 산화막 라이너(130)를 형성한다. 산화막 라이너(130)는 트렌치(120)가 형성된 반도체 기판(100)을 열산화시켜 형성한다. 열산화에 의해, 트렌치(120)를 형성하려고 반도체 기판(100)을 식각하는 동안 가해졌던 데미지가 제거된다. 이어서, 트렌치(120)의 내벽에 질화막 스페이서(140)를 형성한다. 이를 위해서, 산화막 라이너(130)가 형성된 반도체 기판(100) 전면에 50Å ~ 200Å 정도 두께의 질화막을 증착한 다음, 트렌치(120)의 바닥이 노출될 때까지 이를 이방성 식각한다. Next, as shown in FIG. 2, an oxide film liner 130 having a thickness of about 50 μs to about 100 μs is formed on the inner wall and the bottom of the trench 120. The oxide film liner 130 is formed by thermally oxidizing the semiconductor substrate 100 on which the trench 120 is formed. By thermal oxidation, the damage inflicted during the etching of the semiconductor substrate 100 to form the trench 120 is removed. Next, the nitride film spacer 140 is formed on the inner wall of the trench 120. To this end, a nitride film having a thickness of about 50 μs to 200 μs is deposited on the entire surface of the semiconductor substrate 100 on which the oxide liner 130 is formed, and then anisotropically etched until the bottom of the trench 120 is exposed.
다음에 도 3을 참조하면, 도 2의 결과물에 저에너지 높은 도우즈(low energy high dose)의 이온주입(150)을 실시하여 트렌치(120)의 바닥에 고농도 웰(160)을 형성한다. 이 때에, 패드 질화막(110)과 질화막 스페이서(140)가 이온주입 마스크로 사용되어, 트렌치(120)의 바닥 이외에는 이온주입이 되지 않는다. 저에너지 높은 도우즈의 이온주입(150) 에너지와 도우즈는 각기 10 keV 내지 30 keV의 범위, 1×1015 내지 5×1015 ions/cm2의 범위를 갖도록 한다.Next, referring to FIG. 3, low energy high dose ion implantation 150 is performed on the resultant of FIG. 2 to form a high concentration well 160 at the bottom of the trench 120. At this time, the pad nitride film 110 and the nitride film spacer 140 are used as an ion implantation mask so that the ion implantation is not performed except for the bottom of the trench 120. Low energy high dose ion implantation 150 energy and dose are each in the range of 10 keV to 30 keV and in the range of 1 × 10 15 to 5 × 10 15 ions / cm 2 .
이제, 트렌치(120)를 도 4에서와 같이 절연물질(165)로 매립한다. 절연물질(165)로는 예를 들어, MTO(Middle Temperature Oxide), USG(Undoped Silicate Glass) 또는 HDP-CVD(High Density Plasma-Chemical Vapor Deposition)법을 이용하여 형성한 산화막, 또는 이들의 적절한 조합을 이용할 수 있다. The trench 120 is now filled with insulating material 165 as shown in FIG. 4. As the insulating material 165, for example, an oxide film formed by using a middle temperature oxide (MTO), an undoped silicate glass (USG), or a high density plasma-chemical vapor deposition (HDP-CVD) method, or a suitable combination thereof. It is available.
다음에 도 5에서와 같이, 도 4의 결과물 상면을 평탄화하여 패드 질화막(110)이 드러나게 한 다음, 패드 질화막(110)까지 제거하여 반도체 기판(100)의 상면을 드러나게 함으로써 소자분리막(170)을 형성한다. 여기서, 평탄화하는 단계는 패드 질화막(110)을 종료점으로 하는 CMP(Chemical Mechanical Polishing) 공정에 의할 수 있다. 남아 있는 패드 질화막(110)은 잘 알려진 바와 같이 인산 스트립으로 제거할 수 있는데, 그 전에 CMP 단계에서 많이 제거하여야 소자분리막(170)과 반도체 기판(100)간에 단차가 작아진다. 도 1을 참조하여 설명한 단계에서 버퍼 산화막을 형성한 경우라면, 패드 질화막(110) 제거 후, 버퍼 산화막도 HF 희석액 등으로 제거한다. 일반적으로 소자분리막(170)이 반도체 기판(100)에 대하여 위로 약간 솟게 되지만, 도 5에서는 소자분리막(170)과 반도체 기판(100)간의 단차를 무시하고 도시하였다. Next, as shown in FIG. 5, the top surface of the resultant substrate of FIG. 4 is planarized to expose the pad nitride film 110, and then the pad nitride film 110 is removed to expose the top surface of the semiconductor substrate 100 to expose the device isolation film 170. Form. The planarization may be performed by a chemical mechanical polishing (CMP) process having the pad nitride layer 110 as an end point. The remaining pad nitride film 110 can be removed with a phosphate strip, as is well known. Before the removal, the pad nitride film 110 needs to be removed in a large amount from the CMP step so that the step difference between the device isolation film 170 and the semiconductor substrate 100 is reduced. If the buffer oxide film is formed in the step described with reference to FIG. 1, after the pad nitride film 110 is removed, the buffer oxide film is also removed with an HF diluent. In general, although the device isolation film 170 rises slightly upward with respect to the semiconductor substrate 100, the device isolation film 170 is illustrated in FIG. 5, ignoring the step between the device isolation film 170 and the semiconductor substrate 100.
도 6을 참조하면, 소자분리막(170)을 포함한 반도체 기판(100) 전면에 저에너지의 이온주입(180)을 실시하여 고농도 웰(160)의 상부와 오버랩되는 깊이(D)까지 저농도 웰(190)을 형성한다. 저에너지의 이온주입(180)은 20 keV 내지 30 keV의 에너지 범위와 1×1012 내지 1×1013 ions/cm2의 도우즈로 불순물을 주입하는 것이다. 저농도 웰(190)을 형성할 때에는 반도체 기판(100)의 표면으로부터 소자분리막(170) 깊이까지 이온주입이 되어야 하므로, 도 3을 참조하여 설명한 단계에서 노출된 트렌치(120)의 바닥에 이온주입하여 고농도 웰(160)을 형성하는 경우보다 높은 에너지로 주입하는 것이 좋다. 이렇게 하여 형성된 고농도 웰(160)과 저농도 웰(190)을 합친 전체 웰의 깊이는 소자분리막(170) 정도의 깊이가 됨을 알 수 있다.Referring to FIG. 6, the low concentration well 190 is formed to a depth D overlapping with the upper portion of the high concentration well 160 by performing ion implantation 180 of low energy on the entire surface of the semiconductor substrate 100 including the isolation layer 170. To form. The low energy ion implantation 180 implants impurities in an energy range of 20 keV to 30 keV and a dose of 1 × 10 12 to 1 × 10 13 ions / cm 2 . When the low concentration well 190 is formed, ion implantation must be performed from the surface of the semiconductor substrate 100 to the depth of the device isolation layer 170. Thus, by implanting ions into the bottom of the trench 120 exposed in the step described with reference to FIG. 3. It is preferable to inject at a higher energy than to form the high concentration well 160. It can be seen that the depth of the entire well in which the well-concentrated well 160 and the low-concentration well 190 are formed is about the depth of the device isolation layer 170.
이상의 실시예에 의하면, 웰 이온주입시 저에너지 높은 도우즈를 사용하여 웰 영역의 깊이를 트렌치형 소자분리막 정도의 깊이에 형성한다. 이로써, 저저항을 가진 쉘로우 웰이 제어가능하게 형성된다. 웰 영역의 수직적 스케일링을 통하여 웰간 마진을 확보하고, 웰 저항을 감소시킬 수 있다. According to the above embodiments, the depth of the well region is formed at the depth of the trench type isolation layer using a low energy high dose during well ion implantation. As a result, a shallow well having low resistance is controllably formed. By vertical scaling of the well region, an inter well margin may be secured and well resistance may be reduced.
(제2 실시예)(2nd Example)
도 7 내지 도 13은 본 발명의 제2 실시예에 따른 쉘로우 웰 형성방법을 설명하기 위한 공정단면도들이다. 본 실시예에서는 CMOS용 웰을 형성한다. 반도체 집적회로의 동작속도가 빨라지고 집적도가 높아짐에 따라 칩당 소비전력이 현저하게 증가되면서, 저소비전력의 CMOS 소자에 대한 요구는 지속적으로 높아져서, 거의 모든 집적회로가 CMOS화되고 있다. CMOS 소자는 저소비전력이라는 장점 외에도 동작 영역이 넓고, 노이즈 마진(noise margin)이 크다는 장점도 가지고 있다. 7 to 13 are cross-sectional views illustrating a method of forming a shallow well according to a second embodiment of the present invention. In this embodiment, a CMOS well is formed. As the operation speed of semiconductor integrated circuits increases and the degree of integration increases, the power consumption per chip significantly increases, and the demand for low power consumption of CMOS devices continues to increase, and almost all integrated circuits are becoming CMOS. In addition to the low power consumption, CMOS devices also have the advantages of wide operating range and high noise margin.
먼저 도 7을 참조하면, 우선 반도체 기판(200)을 NMOS 영역(a)과 PMOS 영역(b)으로 나눈다. 그리고, 반도체 기판(200)에 형성한 패드 질화막(210)을 식각마스크로 사용하여 반도체 기판(200)을 2500 내지 3000Å 정도 식각함으로써, 반도체 기판의 NMOS 영역(a)과 PMOS 영역(b) 내에 소자분리용 쉘로우 트렌치(220)들을 형성한다. 다음에, 트렌치(220)의 내벽과 바닥에 산화막 라이너(230)를 형성하고, 트렌치(220)의 내벽을 덮는 질화막 스페이서(240)를 형성한다. First, referring to FIG. 7, the semiconductor substrate 200 is first divided into an NMOS region a and a PMOS region b. Then, the semiconductor substrate 200 is etched by about 2500 to 3000 Pa using the pad nitride film 210 formed on the semiconductor substrate 200 as an etching mask, thereby forming elements in the NMOS region a and the PMOS region b of the semiconductor substrate. Separation shallow trenches 220 are formed. Next, an oxide film liner 230 is formed on the inner wall and the bottom of the trench 220, and a nitride film spacer 240 covering the inner wall of the trench 220 is formed.
도 8을 참조하면, NMOS 영역(a)쪽만 노출시키는 1차 감광막(245)을 형성한 다음, 패드 질화막(210)과 질화막 스페이서(240)를 이온주입 마스크로 사용하는 저에너지 높은 도우즈의 이온주입(250)을 실시하여 NMOS 영역(a)의 트렌치(220) 바닥에 P+ 웰(260)을 형성한다. 이 때에 불순물 소스로서 BF2를 이용할 수 있다. 본 실시예에서 저에너지 높은 도우즈란 10 keV 내지 30 keV의 에너지 범위와 1×1015 내지 5×1015 ions/cm2 도우즈를 말한다. 저에너지 이온주입을 실시하므로, 1차 감광막(245)은 1㎛ 내지 1.5㎛의 얇은 두께로 형성할 수 있다. 종래의 감광막 두께가 2.5㎛ 내지 3㎛의 수준인 것을 감안하면, 1차 감광막(245)의 두께는 웰 마진을 확보할 수 있는 정도로 얇은 두께라는 것을 알 수 있다.Referring to FIG. 8, after forming the primary photoresist film 245 exposing only the NMOS region a side, ion implantation of low energy high dose using the pad nitride film 210 and the nitride spacer 240 as an ion implantation mask. 250 is formed to form P + well 260 at the bottom of trench 220 in NMOS region a. At this time, BF 2 can be used as an impurity source. Low energy high doses in this embodiment refer to an energy range of 10 keV to 30 keV and 1 × 10 15 to 5 × 10 15 ions / cm 2 doses. Since low energy ion implantation is performed, the primary photosensitive film 245 can be formed to a thin thickness of 1 μm to 1.5 μm. Considering that the thickness of the conventional photoresist film is 2.5 µm to 3 µm, it can be seen that the thickness of the primary photoresist film 245 is thin enough to secure a well margin.
다음에 도 9에 도시한 바와 같이, 1차 감광막(245)을 제거한 다음, PMOS 영역(b)쪽만 노출시키는 2차 감광막(247)을 형성하고, 패드 질화막(210)과 질화막 스페이서(240)를 이온주입 마스크로 사용하는 저에너지 높은 도우즈의 이온주입(252)을 실시하여, PMOS 영역(b)의 트렌치(220) 바닥에 N+ 웰(262)을 형성한다. 이 때에는 불순물 소스로서 AsH3을 이용할 수 있다. 1차 감광막(245)과 마찬가지로 2차 감광막(247)도 1㎛ 내지 1.5㎛의 얇은 두께를 갖도록 형성할 수 있다.Next, as shown in FIG. 9, after removing the primary photoresist film 245, the secondary photoresist film 247 exposing only the PMOS region b side is formed, and the pad nitride film 210 and the nitride film spacer 240 are formed. A low energy high dose ion implantation 252 used as an ion implantation mask is performed to form an N + well 262 at the bottom of the trench 220 in the PMOS region b. In this case, AsH 3 can be used as an impurity source. Similar to the primary photosensitive film 245, the secondary photosensitive film 247 may be formed to have a thin thickness of 1 μm to 1.5 μm.
도 10을 참조하면, 2차 감광막(247)을 제거한 다음, P+ 웰(260)과 N+ 웰(262) 위로 절연물질(265)을 덮고 상면을 평탄화한 다음 패드 질화막(210)을 제거하여, 트렌치(220)를 매립하는 소자분리막(270)을 형성한다. Referring to FIG. 10, after removing the secondary photoresist layer 247, the insulating material 265 is covered over the P + well 260 and the N + well 262, the top surface is planarized, and the pad nitride layer 210 is removed. An isolation layer 270 is formed to fill the 220.
다음에 도 11에 도시한 바와 같이, NMOS 영역(a)쪽만 노출시키는 3차 감광막(275)을 형성한 다음, 소자분리막(270)을 포함한 반도체 기판(200) 전면에 BF2 등의 저에너지의 이온주입(280)을 실시하여 NMOS 영역(a)에 P+ 웰(260)의 상부와 오버랩되는 깊이까지 P 웰(290)을 형성한다. 본 실시예에서, 저에너지의 이온주입(280)은 20 keV 내지 30 keV의 에너지 범위로 1× 1012 내지 1× 1013 ions/cm 2의 도우즈로 불순물을 주입하는 것이다. 저에너지 이온주입을 실시하므로, 3차 감광막(275)도 1㎛ 내지 1.5㎛의 얇은 두께로 형성할 수 있다.Next, as shown in FIG. 11, a third photosensitive film 275 exposing only the NMOS region a side is formed, and then low energy ions such as BF 2 are formed on the entire surface of the semiconductor substrate 200 including the device isolation film 270. Implant 280 is performed to form P well 290 in NMOS region a to a depth that overlaps with top of P + well 260. In this embodiment, the low energy ion implantation 280 is to inject impurities into doses of 1 × 10 12 to 1 × 10 13 ions / cm 2 in an energy range of 20 keV to 30 keV. Since low energy ion implantation is performed, the tertiary photosensitive film 275 can also be formed with a thin thickness of 1 µm to 1.5 µm.
도 12를 참조하면, 3차 감광막(275)을 제거한 다음, PMOS 영역(b)쪽만 노출시키는 4차 감광막(277)을 형성한다. 이어서, 소자분리막(270)을 포함한 반도체 기판(200) 전면에 저에너지의 이온주입(282)을 실시하여 PMOS 영역(b)에 N+ 웰(262)의 상부와 오버랩되는 깊이까지 N 웰(292)을 형성한다. 저에너지의 이온주입(282)은 20 keV 내지 30 keV의 에너지 범위로 1× 1012 내지 1× 1013 ions/cm2 의 도우즈로 불순물을 주입하는 것이다. 저에너지 이온주입을 실시하므로, 4차 감광막(277)도 1㎛ 내지 1.5㎛의 얇은 두께로 형성할 수 있다. 도 12에 나타내었듯이, N+ 웰(262)과 N 웰(292)을 합친 쉘로우 N 웰의 깊이는 트렌치 소자분리막(270) 정도의 깊이이다. 마찬가지로, P+ 웰(260)과 P 웰(290)을 합친 쉘로우 P 웰의 깊이도 트렌치 소자분리막(270) 정도의 깊이임을 알 수 있다.Referring to FIG. 12, after removing the tertiary photosensitive film 275, a quaternary photosensitive film 277 exposing only the PMOS region b is formed. Subsequently, a low energy ion implantation 282 is applied to the entire surface of the semiconductor substrate 200 including the device isolation layer 270 to form the N well 292 in the PMOS region b to a depth overlapping the top of the N + well 262. Form. Low energy ion implantation 282 is to implant impurities into doses of 1 × 10 12 to 1 × 10 13 ions / cm 2 in an energy range of 20 keV to 30 keV. Since the low energy ion implantation is performed, the quaternary photosensitive film 277 can also be formed with a thin thickness of 1 µm to 1.5 µm. As shown in FIG. 12, the depth of the shallow N well in which the N + well 262 and the N well 292 are combined is about the depth of the trench isolation layer 270. Similarly, it can be seen that the depth of the shallow P well combining the P + well 260 and the P well 290 is about the same as that of the trench isolation layer 270.
도 13을 참조하면, 4차 감광막(277)을 제거하여 웰 형성공정을 완료한다. 본 실시예에 따라 웰이 형성된 반도체 기판(200)에 후속적으로 원하는 CMOS 소자를 형성하게 된다. 예컨대, NMOS 영역(a)과 PMOS 영역(b)에 각각 게이트 절연막(310a, 310b)과 게이트 전극(320a, 320b)으로 구성되는 게이트들을 형성한 다음, 이온주입을 실시하여 소스/드레인(330a, 330b)을 형성한다. 그 위로 층간절연막(미도시)을 형성한 다음, 이를 관통하여 각 소스/드레인(330a, 330b)과 접하는 콘택플러그(340)를 형성한다. Referring to FIG. 13, the well forming process is completed by removing the fourth photosensitive film 277. According to the present exemplary embodiment, a desired CMOS device is subsequently formed on the semiconductor substrate 200 on which the well is formed. For example, gates formed of the gate insulating layers 310a and 310b and the gate electrodes 320a and 320b are formed in the NMOS region a and the PMOS region b, respectively, and then ion implanted to perform source / drain 330a, 330b). An interlayer insulating film (not shown) is formed thereon, and then contact plugs 340 are formed to penetrate through the interlayer insulating film (not shown) and contact each source / drain 330a and 330b.
이상, 본 발명을 바람직한 실시예들을 들어 상세하게 설명하였으나, 본 발명은 상기 실시예들에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 많은 변형이 가능함은 명백하다.As mentioned above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical idea of the present invention. It is obvious.
상술한 본 발명에 의하면, 저저항을 가진 쉘로우 웰이 제어가능하게 형성된다. 본 발명에 따라 형성되는 쉘로우 웰의 장점은 다음과 같다.According to the present invention described above, a shallow well having low resistance is formed to be controllable. Advantages of the shallow well formed in accordance with the present invention are as follows.
첫째, 웰 저항이 종래보다 70 ~ 90% 감소된다. 트리거 전압(trigger voltage)이 증가하고 홀딩 전압(holding voltage)이 감소하기 때문에 랫치업이 억제된다. 저항 감소에 따라, 웰 바이어싱(biasing)을 위한 콘택 수를 감소하는 것이 용이하므로, 웰 바이어스를 안정화할 수 있다.First, the well resistance is reduced by 70 to 90% compared to the conventional. The latchup is suppressed because the trigger voltage increases and the holding voltage decreases. As the resistance decreases, it is easy to reduce the number of contacts for well biasing, so that the well bias can be stabilized.
둘째, 저에너지 이온주입을 사용하므로 이온주입시의 데미지(damage)를 감소시킨다. 따라서, 본 발명에 따라 형성한 웰에 DRAM 등의 메모리 소자를 형성하게 되면, 메모리 소자의 데이타 리텐션 타임(data retention time) 즉, 리프레쉬 타임(refresh time) 특성이 향상된다. Second, since low energy ion implantation is used, damage during ion implantation is reduced. Therefore, when a memory device such as a DRAM is formed in a well formed according to the present invention, the data retention time, that is, the refresh time characteristic of the memory device is improved.
셋째, 저에너지 이온주입을 실시하므로 마스킹이 필요한 경우에 감광막의 두께를 충분히 얇게 형성할 수 있다. 종래에는 마스킹용 감광막이 2.5㎛ 내지 3㎛의 두께 수준으로 두꺼워서 웰간의 마진이 감소하였던 것에 비하여 본 발명에서는 1㎛ 내지 1.5㎛의 두께로 얇게 형성할 수 있다. 따라서, 웰간의 마진을 증가시킬 수 있게 되므로 소자의 고집적화에 유리하게 적용될 수 있다.Third, since the low energy ion implantation is performed, the thickness of the photosensitive film can be sufficiently thin when masking is required. Conventionally, since the masking photoresist film is thick at a thickness level of 2.5 μm to 3 μm, the margin between the wells may be reduced, and thus, the present invention may be thinly formed to have a thickness of 1 μm to 1.5 μm. Therefore, it is possible to increase the margin between the wells can be advantageously applied to the high integration of the device.
넷째, 고농도 웰과 저농도 웰을 합친 전체 쉘로우 웰의 깊이는 2500 내지 3000Å 깊이로 형성되는 소자분리막의 깊이 수준이다. 웰 깊이가 깊지 않으므로 SER 특성을 개선할 수 있다. Fourth, the depth of the whole shallow well combined with the high concentration well and the low concentration well is the depth level of the device isolation film formed to be 2500 to 3000 microns deep. Since the well depth is not deep, SER characteristics can be improved.
도 1 내지 도 6은 본 발명의 일 실시예에 따른 쉘로우 웰 형성방법을 설명하기 위한 공정단면도들이다. 1 to 6 are process cross-sectional views illustrating a shallow well forming method according to an embodiment of the present invention.
도 7 내지 도 13은 본 발명의 다른 실시예에 따른 쉘로우 웰 형성방법을 설명하기 위한 공정단면도들이다. 7 to 13 are process cross-sectional views illustrating a shallow well forming method according to another exemplary embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
110, 210 : 패드 질화막 120, 220 : 소자분리용 트렌치110, 210: pad nitride film 120, 220: trench for device isolation
130, 230 : 산화막 라이너 140, 240 : 질화막 스페이서130, 230: oxide film liner 140, 240: nitride film spacer
150, 250, 252 : 저에너지 높은 도우즈의 이온주입150, 250, 252: Ion implantation of low energy high dose
160 : 고농도 웰 170, 270 : 소자분리막160: high concentration well 170, 270: device isolation membrane
180, 280, 282 : 저에너지의 이온주입 190 : 저농도 웰 180, 280, 282: Low energy ion implantation 190: Low concentration well
245, 247, 275, 277 : 감광막 260 : P+ 웰 245, 247, 275, 277: photoresist 260: P + well
262 : N+ 웰 290 : P 웰 262: N + well 290: P well
292 : N 웰 292: N well
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| US10/626,248 US6844239B2 (en) | 2002-07-24 | 2003-07-23 | Method for forming shallow well of semiconductor device using low-energy ion implantation |
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| JPH0682755B2 (en) * | 1989-06-19 | 1994-10-19 | 猛英 白土 | Semiconductor device |
| JPH03101147A (en) * | 1989-09-13 | 1991-04-25 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0468564A (en) * | 1990-07-10 | 1992-03-04 | Sony Corp | Manufacture of semiconductor device |
| KR960014448B1 (en) * | 1993-12-14 | 1996-10-15 | 금성일렉트론 주식회사 | Method of isolation of a semiconductor device |
| JPH09213786A (en) * | 1996-02-07 | 1997-08-15 | Sony Corp | Method of isolating element of semiconductor device, and cmos device |
| US6144086A (en) * | 1999-04-30 | 2000-11-07 | International Business Machines Corporation | Structure for improved latch-up using dual depth STI with impurity implant |
| US20020086499A1 (en) * | 2000-12-31 | 2002-07-04 | Seetharaman Sridhar | Process to improve Nwell-Nwell isolation with a blanket low dose high energy implant |
-
2002
- 2002-07-24 KR KR10-2002-0043698A patent/KR100480604B1/en active IP Right Grant
-
2003
- 2003-07-22 JP JP2003277861A patent/JP2004064085A/en active Pending
- 2003-07-23 US US10/626,248 patent/US6844239B2/en not_active Expired - Lifetime
- 2003-07-24 CN CNB031328628A patent/CN100359665C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10261766A (en) * | 1997-03-17 | 1998-09-29 | Internatl Business Mach Corp <Ibm> | Method and device for enhancing latch-up resistance in cmos device |
| JPH11340461A (en) * | 1998-05-28 | 1999-12-10 | Toshiba Corp | Semiconductor device and fabrication thereof |
| KR20010064965A (en) * | 1999-12-20 | 2001-07-11 | 박종섭 | Method for manufacturing of semiconductor device |
| US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| US6844239B2 (en) | 2005-01-18 |
| CN1485895A (en) | 2004-03-31 |
| CN100359665C (en) | 2008-01-02 |
| JP2004064085A (en) | 2004-02-26 |
| US20040132263A1 (en) | 2004-07-08 |
| KR20040009681A (en) | 2004-01-31 |
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