KR100480562B1 - Circuit for adjusting full-scale current in digital-analog converter - Google Patents

Abstract

A full scale current regulation circuit of a digital to analog converter is disclosed. A current switching means for generating a first current in response to an output voltage of an amplifier having a negative input terminal connected to a predetermined reference voltage, and outputting a second current proportional to the first current as a full scale current in response to a digital signal; In a digital-to-analog converter comprising: a full-scale current adjustment circuit for adjusting a full-scale current, the reference current source for supplying a predetermined reference current; A current mirror that generates a third current that is proportional to the input reference current and is an initial value of the first current; And current adjusting means for generating N (N is a natural number) fourth currents proportional to the third current in response to the N gain control signals, wherein the first current is the third current and the N fourth currents. It is characterized by the sum. Therefore, there is an advantage that the full scale current can be easily changed to a predetermined desired value by a gain control signal without requiring an external adjustment terminal.

Description

Circuit for adjusting full-scale current in digital-analog converter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter, and more particularly to a full-scale current adjustment circuit of a digital-to-analog converter that adjusts the magnitude of an analog full-scale output from the digital-to-analog converter in accordance with a digital signal. It is about.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of a conventional digital-analog converter are described as follows.

FIG. 1 is a circuit diagram illustrating a conventional digital-analog converter, and includes a reference current source 100 and a current switching unit 120. Here, if M (M is a natural number) digital signal to be converted into an analog signal, 2 ^M current switching units are used, but only one current switching unit is considered for simplicity.

The reference current source 100 includes an operational amplifier 102 having a negative input terminal connected to a predetermined reference voltage VREF, a gate having a gate connected to an output terminal of the operational amplifier 102, and a source connected to a supply power supply VDDA. (MP1), a transistor (MP2) having a gate connected to a predetermined reference voltage (VREF), a source connected to the drain of the transistor (MP1) and one side of the positive input terminal of the operational amplifier 102 and the drain of the transistor (MP2) It is composed of a resistor (R1) connected in common to the other side and connected to the reference potential VSSA.

The current switching unit 120 includes a gate connected to the output terminal of the operational amplifier 102, a transistor MP3 having a source connected to the supply power supply VDDA, a gate connected to a predetermined reference voltage VREF, and a transistor MP3. A transistor MP4 having a source and a drain connected between a drain and an output terminal OUT of the gate and a gate connected to the input terminal IN, and a transistor MP5 having a source and a drain connected between the drain and the reference potential VSSA of the transistor MP3. It is composed of

When a predetermined reference voltage VREF is applied to the negative input terminal of the operational amplifier 102 shown in FIG. 1, the voltage equal to the resistor R1 connected to the positive input terminal of the operational amplifier 102 is characteristic of the ideal operational amplifier. This takes The current I1 flowing in the resistor R1 has a value of VREF / R1, which is supplied from the transistor MP1 in response to the voltage output from the operational amplifier 102. The operational amplifier 102 automatically adjusts the gate voltage of the transistor MP1 until the current I1 of VREF / R1 is supplied from the transistor MP1, and when the current I1 of VREF / R1 flows, the transistor A constant gate voltage is applied to (MP1).

The transistor MP3 of the current switching unit 120 generates a current I2 in response to the voltage output from the operational amplifier 102, similarly to the transistor MP1, and this current I2 is connected to the transistor MP1. It is a current proportional to the current I1 corresponding to the channel length ratio of the transistor MP3. Here, the channel widths of the transistors MP1 and MP3 are the same.

Therefore, when a constant current I1 flows in response to a constant gate voltage output from the operational amplifier 102, a current I2 proportional to the current I1 also flows constantly, and the current I2 is a current switching unit. It serves as a reference current of 120.

Each of the transistors MP5 and MP4 of the current switching unit 120 switches in response to a digital signal input through the input terminal IN and a predetermined reference voltage VREF. That is, when the digital signal is high level, the transistor MP4 is turned on so that the current I2 flows through the transistor MP4 to the output terminal OUT. When the digital signal is low level, the transistor MP5 is turned on and the current I2 is turned on. It flows to the reference potential VSSA through the transistor MP5. Here, when the digital signal is high level, the current flowing to the output terminal OUT is the full scale current.

In the above-described conventional digital-to-analog converter, the full scale current depends on the current I2 of the current switching unit 120, and the current I2 is a current proportional to the current I1 from the reference current source 100. When the current I1 flows constantly, the current I2 and the full scale current also flow constantly. As a method of adjusting the full scale current, there is a method of changing the resistance value by an external adjusting terminal by configuring the resistance R1 of the reference current source 100 as a variable resistor. There is a problem of a narrow adjustment range. That is, the full scale current has a problem that it is not easy to readjust once it is determined at the time of designing and processing the circuit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a full scale current regulation circuit of a digital-to-analog converter that changes a full scale current without requiring an external adjustment terminal.

In order to achieve the above object, a first current is generated in response to an output voltage of an amplifier having a negative input terminal connected to a predetermined reference voltage, and a second current proportional to the first current is used as a full scale current in response to a digital signal. In a digital-to-analog converter including a current switching means for outputting, a full-scale current adjustment circuit according to a preferred embodiment of the present invention for adjusting the full-scale current, the reference current source for supplying a predetermined reference current; A current mirror that generates a third current that is proportional to the input reference current and is an initial value of the first current; And current adjusting means for generating N (N is a natural number) fourth currents proportional to the third current in response to the N gain control signals, wherein the first current is the third current and N Is the sum of four fourth currents.

Further, in order to achieve the above object, a first current is generated in response to an output voltage of an amplifier having a negative input terminal connected to a predetermined reference voltage, and a second current proportional to the first current is full scale in response to a digital signal. In a digital-to-analog converter including current switching means for outputting as a current, the full-scale current adjusting circuit according to another preferred embodiment of the present invention for adjusting the full-scale current supplies a predetermined reference current and initializes the reference current. A reference current source for generating a first current that is a value; And current adjusting means for generating N (N is a natural number) third currents proportional to the first current in response to the N gain control signals, wherein the first current is the N current at the reference current. It is the value which subtracted 3rd electric currents.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the full-scale current adjustment circuit of the digital-to-analog converter according to an embodiment of the present invention will be described as follows.

FIG. 2 is a circuit diagram illustrating a full scale current adjustment circuit according to an exemplary embodiment of the present invention, and includes a reference current source 200, a current mirror 220, a current switching unit 240, and a current adjustment unit 260. do.

The reference current source 200 has an operational amplifier 202 having a negative input terminal connected to a predetermined reference voltage VREF, a gate connected to an output terminal of the operational amplifier 202, and a source connected to a supply power supply VDDA, respectively. Transistors M2 and M4 each having transistors M1 and M3, a gate connected to a predetermined reference voltage VREF, a source connected to the drain of the transistors of the transistors M1 and M3, and one side thereof are operational amplifiers ( The resistor R2 is connected to the positive input terminal of the positive electrode 202 and the drain of the transistor MP2 in common, and the other side thereof is connected to the reference potential VSSA.

The current mirror 220 includes a transistor M5 having a gate connected to the supply power supply VDDA, a drain connected to the drain of the transistor M4, a drain and a gate connected to the source of the transistor M5, and a reference potential VSSA. A transistor M6 having a source connected to the gate, a transistor M7 having a gate connected to the supply power supply VDDA, a gate connected to the gate of the transistor M6, a drain connected to the source of the transistor M7, and a reference potential ( It consists of a transistor M8 having a source connected to VSSA.

The current switching unit 240 includes an operational amplifier 242 having a negative input terminal connected to a predetermined reference voltage VREF, and a gate connected to an output terminal of the operational amplifier 242. Transistors M9 and M11, each having a source connected to the supply power supply VDDA, a gate connected to a predetermined reference voltage VREF, a source connected to the drain of the transistor M9, and a positive input of the operational amplifier 242. A transistor M10 having a drain commonly connected to the terminal and the drain of the transistor M7, a gate connected to a predetermined reference voltage VREF, and a source and a drain connected between the drain and the output terminal OUT of the transistor MP11, respectively. And a transistor M13 having a gate connected to the transistor M12 and the input terminal IN, and a source and a drain connected between the drain and the reference potential VSSA of the transistor M11, respectively.

The current adjusting unit 260 may include a gate connected to a corresponding gain control signal among N gain control signals C1, C2... CN, and a positive input terminal of the operational amplifier 242 and a transistor M10. N transistors M17, M27 ... MN7 and a gate connected to the gate of transistor M6, each of which has a drain connected in common to the drain of N1, and N transistors M17, M27 ... MN7. N transistors M18, M28, MN8 each having a drain connected to the source of the corresponding transistor and a source connected to the reference potential VSSA.

When a predetermined reference voltage VREF is applied to the negative input terminal of the operational amplifier 202 of the reference current source 200 shown in FIG. 2, the same as that of the resistor R2 connected to the positive input terminal of the operational amplifier 202. Voltage is applied. The current I3 flowing in the resistor R2 has a value of VREF / R2 and is supplied from the transistor M1 in response to the voltage output from the operational amplifier 202. The operational amplifier 202 automatically adjusts the gate voltage of the transistor M1 until the current I3 of VREF / R2 is supplied from the transistor M1, and when the current I3 of VREF / R2 flows, the transistor A constant gate voltage is applied to M1. In addition, the transistor M3 generates a current I4 in response to the voltage output from the operational amplifier 202, similarly to the transistor M1, and this current I4 is a channel of the transistors M1 and M3. It is a current proportional to the current I3 corresponding to the length ratio. Here, the channel widths of the transistors M1 and M3 are the same.

Therefore, when a constant current I3 flows in response to a constant gate voltage output from the operational amplifier 202, a current I4 proportional to the current I3 also flows constantly.

The constant current I4 from the reference current source 200 described above flows to the current mirror 220. Since the transistor M5 of the current mirror 220 is always turned on when the supply power supply VDDA is applied to the gate, the current I4 may flow to the transistor M6. Since the transistor M6 is a drain-feedback bias and is always in conduction state, the current I4 flows to the reference potential VSSA. In addition, since the transistor M7 receives the supply power supply VDDA to the gate in the same manner as the transistor M5 and is always turned on, the current I5 from the current switching unit 240, which will be described later, is the transistor M8. Flows into. This current I5 is a current proportional to the current I4 corresponding to the channel length ratio of the transistors M6 and M8. Here, the channel widths of the transistors M6 and M8 are the same.

When a predetermined reference voltage VREF is applied to the negative input terminal of the operational amplifier 242 of the current switching unit 240, the same voltage is applied to a node connected to the positive input terminal of the operational amplifier 242. The operational amplifier 242 responds to the output voltage until the current I6 supplied from the transistor M9 is equal to the current I5 described above, except that the gain control signals C1, C2 ... CN) are all low level) Automatically adjust the output voltage. When the operational amplifier 242 is automatically adjusted so that the current I6 as much as the current I5 flows, the operational amplifier 242 applies a constant gate voltage to the transistor M9.

In addition, the transistor M11 of the current switching unit 240 generates a current I7 in response to the output voltage of the operational amplifier 242, similarly to the transistor M9, and the current I7 is the transistor M9. And a current proportional to the current I6 corresponding to the channel length ratio of the transistor M11. Here, the channel widths of the transistors M9 and M11 are the same. The transistors M13 and M12 of the current switching unit 240 switch in response to the digital signal input through the input terminal IN and the predetermined reference voltage VREF. That is, when the digital signal is high level, the transistor M12 is turned on so that the current I7 flows to the output terminal OUT as a full-scale current. When the digital signal is low level, the transistor M13 is turned on and the current I7 is turned to the reference potential. (VSSA).

The operation of the reference current source 200, the current mirror 220, and the current switching unit 240 described above is performed when the gain control signals C1, C2. This is necessary when setting the value.

Hereinafter, the current adjusting unit 260 for substantially adjusting the full scale current will be described.

The transistors M17, M27... MN7 of the current adjuster 260 switch in response to gain control signals C1, C2... CN from a control unit 280 such as a microcomputer. As described above, when the gain control signals C1, C2 ... CN are all at low level, the transistors M17, M27 ... MN7 are all turned off, so that the current I6 is equal to the current I5. same.

However, when the gain control signals C1, C2 ... CN are all at the high level, the transistors M17, M27 ... MN7 are all turned on, so that the current I5 proportional to the current I4 is the transistor ( As in the case of M8, currents I15, I25 ... IN5 proportional to the current I4 flow through the transistors M18, M28, MN8, respectively. Here, the channel widths of the transistors M8, M18, M28 ... MN8 are the same.

Thus, the current I6 is adjusted to the sum of the currents I5, I15, I25 ... IN5, and the current I7 proportional to the current I6 as the current I6 is adjusted by the gain control signals. ) Is adjusted and eventually the full-scale current flowing to the output terminal OUT is adjusted.

That is, according to the level combination of the gain control signals C1, C2 ... CN of the current adjusting unit 260, the full scale current is low when the gain control signals C1, C2 ... CN are all low level. It can be increased to a predetermined value from the value of the basic full scale current determined by.

Hereinafter, the configuration and operation of a full-scale current adjustment circuit according to another preferred embodiment of the present invention will be described as follows with reference to the accompanying drawings.

FIG. 3 is a circuit diagram illustrating a full scale current adjustment circuit according to another exemplary embodiment of the present invention, and includes a reference current source 300, a current adjuster 320, and a current switch 340.

The reference current source 300 includes an operational amplifier 302 having a negative input terminal connected to a predetermined reference voltage VREF, a gate having a gate connected to an output terminal of the operational amplifier 302, and a source connected to a supply power supply VDDA. M1, a transistor M2 having a gate connected to the reference potential VSSA, a source connected to the drain of the transistor M1, and one side thereof connected to the positive input terminal of the operational amplifier 102 and the drain of the transistor M2. The resistor R3 is connected in common and the other side is connected to the reference potential VSSA.

The current adjuster 320 has N (N is a natural number) transistors M11, M21... MN1 and N each having a gate connected to the output terminal of the operational amplifier 302 and a source connected to the supply power supply VDDA. A gate connected to the corresponding gain control signal among the one gain control signals C1, C2 ... CN, a source connected to the drain of the corresponding transistor among the N transistors M11, M21 ... MN1, and a resistor R3. N transistors (M12, M22, ... MN2) each having a drain connected to one side thereof.

The current switching unit 340 may include a transistor M3 having a gate connected to the output terminal of the operational amplifier 302, a source connected to the supply power supply VDDA, a gate connected to the input terminal IN, and a drain of the transistor M3. A transistor M4 having a source and a drain connected between the reference potential VSSA and a gate connected to the input terminal INB, and a transistor M5 having a source and a drain connected between the drain and the output terminal OUT of the transistor M3. do.

When a predetermined reference voltage VREF, for example, 1.235 V is applied to the negative input terminal of the operational amplifier 302 of the reference current source 300 illustrated in FIG. 3, a resistor connected to the positive input terminal due to the characteristics of the operational amplifier 302 The same voltage is applied to (R3). At this time, the gain of the operational amplifier 302 is large enough, and its offset is ignored. The current IT flowing through the resistor R3 has a value of VREF / R3 and is supplied from the transistor M1 in response to the voltage output from the operational amplifier 302. The operational amplifier 302 automatically adjusts the gate voltage of the transistor M1 until the current IT of VREF / R3 is supplied from the transistor M1, and when the current IT of VREF / R3 flows, the transistor A constant gate voltage is applied to M1.

The above-described current IT is specifically the current I0 flowing through the transistor M2 connected in series with the transistor M1 (however, the gain control signals C1, C2 ... CN to be described in detail later). All of them are at the high level). The transistor M2 is always in a conductive state because the reference potential VSSA is applied as the gate voltage.

However, when the current adjuster 320 supplies the currents I1, I2 ... IN in response to the gain control signals C1, C2 ... CN, the current IT having a value of VREF / R3. ) Is the sum of the current I0 and the currents I1, I2 ... IN. That is, it can be expressed as IT = I0 + I1 + I2 + ... IN.

Specifically, the N transistors M11, M21,... MN1 of the current adjuster 320 illustrated in FIG. 3 are the same as the above-described transistor M1. Supply current in response to the voltage output from

That is, the transistor M1 and the N transistors M11, M21, MN1 form a current mirror. The current I1 supplied from the transistor M11 is a current proportional to the current I0 corresponding to the channel length ratio of the transistor M1 and the transistor M11, and the current I2 supplied from the transistor M21 is It is a current proportional to the current I0 corresponding to the channel length ratio of the transistors M1 and M21, and likewise, the current IN supplied from the transistor MN1 is equal to that of the transistors M1 and MN1. The current is proportional to the current IO corresponding to the channel length ratio, where the channel widths of the transistors M1 and the N transistors M11, M21, MN1 are the same.

The currents I1, I2 ... IN flowing through the N transistors M11, M21 ... MN1 are connected in series to N transistors M11, M21 ... MN1. It is controlled by transistors M12, M22 ... MN2. That is, each of the N transistors M12, M22, MN2 switches in response to a corresponding gain control signal among the gain control signals C1, C2, CN generated from the control unit 360 such as a microcomputer. Therefore, the current among the currents I1, I2, ... IN is turned on / off.

As described above, when the gain control signals C1, C2, ... CN are all at the high level, since the N transistors M12, M22, MN2 are all turned off, the current IT is the current I0. Same as). However, when any of the transistors M12, M22 ... MN2 is turned on in response to the level combination of the gain control signals C1, C2 ... CN, the current IT is the current I0. ) And the currents I1, I2..., IN become the sum of any of the currents, the current I0 may eventually be reduced from the maximum value IT to a predetermined value. That is, I0 = IT-I1-I2 -... IN can be represented.

Now, the full scale current output from the current switching unit 340 by the above-described current adjusting unit 320 will be described.

The transistor M3 of the current switching unit 340 is a current source for supplying current in response to the output voltage of the operational amplifier 302 in the same manner as the transistor M1 described above. The transistors M4 and M5 operate in response to the digital signal and the inverted digital signal input through the input terminals IN and INB. That is, when the digital signal is high level, the transistor M5 is turned on so that the current supplied from the transistor M3 flows to the output terminal OUT as a full scale current. When the digital signal is low level, the transistor M4 is turned on and the transistor M3 is turned on. The current supplied from) flows to the reference potential VSSA.

Here, the full scale current IL flowing through the output terminal OUT to the external resistor RL is proportional to the current I0. That is, the full scale current IL is a current proportional to the current I0 corresponding to the channel length ratio of the transistors M1 and M3, where the channel widths of the transistors M1 and M3 are equal. Do. As described above, the current I0 can be represented by I0 = IT-I1-I2 -... IN, so that the full scale current IL is adjusted accordingly.

As a result, according to the level combination of the gain control signals C1, C2, ... CN of the current adjuster 320, the full scale current IL is low when the gain control signals C1, C2, ... CN are all low. It can be reduced from the value of the full scale current determined in the case of the level to a predetermined value.

As described above, the full-scale current adjustment circuit of the digital-to-analog converter according to the present invention has an advantage that the full-scale current can be easily changed to a desired value by a gain control signal.

1 is a schematic circuit diagram of a conventional digital-analog converter.

2 is a circuit diagram illustrating a full-scale current adjustment circuit according to an embodiment of the present invention.

3 is a circuit diagram for explaining a full scale current adjustment circuit according to another preferred embodiment of the present invention.

Claims (6)

Current switching means for generating a first current in response to an output voltage of an amplifier having a negative input terminal connected to a predetermined reference voltage, and outputting a second current proportional to the first current as a full scale current in response to a digital signal; In the full-scale current adjustment circuit of the digital-to-analog converter comprising: A reference current source for supplying a predetermined reference current; A current mirror configured to generate a third current that is proportional to the input reference current and is an initial value of the first current; And And current adjusting means for generating N fourth currents proportional to the third current in response to N gain control signals, And the first current is a sum of the third current and the N fourth currents. The method of claim 1, wherein the current mirror, A first transistor having a gate connected to a supply power source, and a drain and a source connected between the reference current and the reference potential, respectively; A second transistor having a gate and a drain connected to the source of the first transistor and a source connected to the reference potential; A third transistor having a gate connected to the power supply, and a drain and a source connected between the first current and the reference potential, respectively; And A fourth transistor having a gate connected to a gate of the second transistor, and a drain and a source connected between the source of the third transistor and the reference potential, respectively; And the third current flowing through the fourth transistor is the third current. The method of claim 2, wherein the current adjusting means, N fifth transistors; And N sixth transistors, A gate of each of the fifth transistors is connected to the gain control signal, and a drain and a source of each of the fifth transistors are respectively connected between the first current and the reference potential, A gate of each of the sixth transistors is connected to a gate of the fourth transistor, and each drain and source are connected between a source of the fifth transistor and the reference potential, respectively. . 4. The full scale current adjustment circuit of claim 1, wherein the gain control signals are generated from a microcomputer. Current switching means for generating a first current in response to an output voltage of an amplifier having a negative input terminal connected to a predetermined reference voltage, and outputting a second current proportional to the first current as a full scale current in response to a digital signal; In the full-scale current adjustment circuit of the digital-to-analog converter comprising: A reference current source for supplying a predetermined reference current and generating the first current which is an initial value of the reference current; And And current adjusting means for generating N (N is a natural number) third currents proportional to the first current in response to N gain control signals, The first current is a value obtained by subtracting the N third currents from the reference current. The reference current source is An operational amplifier having a negative input terminal connected to the predetermined reference voltage; A first transistor having a gate connected to an output terminal of the operational amplifier, a source connected to a supply power supply, and a drain configured to output the first current; A second transistor having a gate connected to a reference potential, a source connected to a drain of the first transistor, and a drain connected to a positive input terminal of the operational amplifier; And One side is commonly connected to the drain of the second transistor and the positive input terminal of the operational amplifier, and the other side has a resistor connected to the reference potential, The current flowing through the resistor is the reference current, The current adjusting means includes N third transistors; And N fourth transistors, A gate of each of the third transistors is connected to an output terminal of the operational amplifier, a respective source is connected to the supply power supply, a gate of each of the fourth transistors is connected to a corresponding gain control signal, A source and a drain are respectively connected between the drain and the reference current of the third transistor. 6. The full-scale current adjustment circuit of claim 5, wherein the gain control signals are generated from a microcomputer.

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