KR100479823B1 - Decoupling capacitor of semiconductor device and forming method thereof - Google Patents

Abstract

The present invention relates to a decoupling capacitor of a semiconductor device and a method of forming the same. The present invention provides a decoupling capacitor for storing DRAM internal voltages using an NMOS transistor, and then removes a predetermined thickness of a mask insulating film pattern on the gate electrode of the NMOS transistor. After the trench is formed, the conductive layer is embedded to form a landing plug, and Vss is connected to the landing plug to increase the capacitance of the decoupling capacitor without any additional process, thereby improving cell efficiency, and thus operating characteristics of the device and It is a technology that can improve high integration.

Description

Decoupling capacitor of semiconductor device and forming method

The present invention relates to a decoupling capacitor of a semiconductor device and a method of forming the same. More specifically, a decoupling capacitor of a semiconductor device capable of securing electrical operation characteristics of a DRAM by forming a decoupling capacitor having improved capacitance from an NMOS transistor and a method of forming the same. It is about.

DRAM is characterized by generating an internal voltage (internal voltage) to use in operation.

When the internal voltage is used during DRAM operation and current consumption is high, the level becomes unstable. To prevent this, a method of sufficiently storing a charge source using a decoupling capacitor in the form of an NMOS transistor is used.

However, as DRAM devices become more integrated and higher in speed, they face a situation in which a large amount of current must be consumed in a short time.

Therefore, a decoupling capacitor is formed in the peripheral circuit region of the DRAM device to sufficiently store the internal voltage.

Hereinafter, with reference to the accompanying drawings will be described in the prior art.

FIG. 1 is a schematic diagram illustrating a peripheral circuit portion of a general DDR double data rate dynamic random access memory (DRAM), and includes decoupling capacitors 13 and 15 for a Vpp operating voltage and a Vcc driving voltage than a driving circuit portion 11 for DRAM operation. It can be seen that occupies a wider area.

2A and 2B are a plan view and a cross-sectional view of a decoupling capacitor according to the prior art, and FIG. 2C is a circuit diagram of a decoupling capacitor formed by the prior art, and includes a gate insulating film 23 and a gate electrode 24 on the semiconductor substrate 21. And a first insulating layer spacer 26 and a second insulating layer spacer 27 on sidewalls of the stacked structure of the mask insulating layer pattern 25 and source / drain regions on the semiconductor substrate 21 on both sides of the gate electrode 24. 22 shows a decoupling capacitor of an NMOS transistor structure provided.

In this structure, a contact plug 29 for connecting power (Vpower) is provided at the edge of the gate electrode 24, and a contact plug 29 for connecting to Vss is provided at the source / drain region 22. It consists of one capacitor.

However, as described above, the decoupling capacitor and the method of forming the semiconductor device according to the prior art form a decoupling capacitor capable of sufficiently storing the internal voltage in the peripheral circuit region of the DRAM device, but as the semiconductor device becomes faster, it is limited. There is a problem that it is difficult to secure a noise margin due to the demand of a high speed device within an area.

In order to solve the above problems of the prior art, the first decoupling capacitor is formed by using the NMOS transistor when the decoupling capacitor is formed after the decoupling capacitor is formed of the NMOS transistor and stores the internal voltage of the DRAM constituting the NMOS transistor. After that, a landing plug is formed on a mask insulating film pattern stacked on the gate electrode of the NMOS transistor to form a second decoupling capacitor connected in parallel to the first decoupling capacitor, thereby storing sufficient internal voltage without increasing the area. SUMMARY OF THE INVENTION An object of the present invention is to provide a decoupling capacitor of a semiconductor device and a method of forming the decoupling capacitor to stabilize the DC bias level of a DRAM.

Decoupling capacitor of the semiconductor device according to the present invention for achieving the above object,

A first decoupling capacitor comprising a gate insulating film used as a dielectric film of a capacitor on a semiconductor substrate, a gate electrode on which a mask insulating film pattern is stacked on the gate insulating film;

The gate electrode, the mask insulating film pattern, and a second decoupling capacitor including a landing plug included in the mask insulating film pattern may be connected in parallel with each other.

A method of forming a decoupling capacitor of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate electrode on which a gate insulating film, a mask insulating film pattern is laminated on a semiconductor substrate comprising a cell region, an NMOS region and a PMOS region; Forming a first insulating film and a second insulating film on the entire surface including the gate electrode, and etching the portion where the decoupling capacitor of the NMOS region is to be formed and the first and second insulating films of the PMOS region, wherein the PMOS region is etched. Forming a spacer on a sidewall of the gate electrode, etching the first and second insulating layers of the NMOS region to form a spacer on the sidewall of the NMOS region gate electrode, and forming a mask insulating layer of a portion where the decoupling capacitor is to be formed. Etching to form a trench, and etching the second insulating layer of the cell region Forming a first interlayer insulating film on an entire surface of the semiconductor substrate including the gate electrode, and forming a landing plug contact hole exposing a portion of the cell region and a portion where a decoupling capacitor of the NMOS region is to be formed. And forming a polycrystalline silicon layer filling the landing plug contact hole, forming a landing plug by planarizing etching to expose the mask insulating layer, and forming a second interlayer insulating layer on the entire surface of the semiconductor substrate. And etching the second interlayer insulating layer to form first bit line contact holes in the cell region and the NMOS region, and etching the first and second interlayer insulating layers to form a second bit line contact in the PMOS region. Forming holes

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Hereinafter, a decoupling capacitor of a semiconductor device and a method of manufacturing the same will be described with reference to the accompanying drawings.

3A to 3J are cross-sectional views illustrating a semiconductor device manufacturing process according to the present invention. FIGS. 4A and 4B are plan and cross-sectional views of a decoupling capacitor according to the present invention, and FIG. 4C is a view of a decoupling capacitor formed by the prior art. As a circuit diagram, it demonstrates in association with each other.

First, a gate insulating film (not shown), a gate electrode conductive layer (not shown), and a mask insulating film (not shown) are formed over the semiconductor substrate 31 including the cell region I, the NMOS region II, and the PMOS region III. A laminate structure of) is formed.

Next, the stacked structure is etched by a photolithography process using a gate electrode mask to form a gate insulating film pattern (not shown), a gate electrode 33, and a mask insulating film pattern 35.

Next, a first insulating film 37 and a second insulating film 39 are formed over the entire surface including the gate electrode 33. (See Figure 3A)

Next, a first photoresist pattern 41 is formed on the entire surface of the NMOS region II to expose the portion where the decoupling capacitor is to be formed and the PMOS region III.

Subsequently, the second insulating layer 39 and the first insulating layer 37 are etched using the first photoresist layer pattern 41 as an etch mask to form a mask insulating layer pattern formed on the gate electrode 33 of the NMOS region II. The first insulating film spacer 38 and the second insulating film spacer 40 are formed on sidewalls of the gate electrode 33 and the mask insulating film pattern 35 of the PMOS region III at the same time as exposing the 35.

Thereafter, p + impurities are implanted into the semiconductor substrate 31 on both sides of the second insulating film spacer 40 of the PMOS region III to form a source / drain region (not shown). (See Figure 3b)

Thereafter, the first photoresist pattern 41 is removed.

Next, a second photoresist pattern 43 exposing the NMOS region II is formed over the entire surface.

Next, the second insulating layer 39 and the first insulating layer 37 are etched by using the second photoresist layer pattern 43 as an etch mask to form a first sidewall of the gate electrode 33 and the mask insulating layer pattern 35. The insulating film spacers 38 and the second insulating film spacers 40 are formed, and the trench 45 is formed by etching the mask insulating film pattern 35 in the portion where the decoupling capacitor is to be formed.

Thereafter, an n + impurity is ion-implanted into the semiconductor substrate 31 on both sides of the second insulating film spacer 40 to form a source / drain region (not shown).

Next, the second photoresist pattern 43 is removed.

Next, a third photoresist pattern 47 for exposing the cell region I is formed on the entire surface.

Next, the second photoresist pattern 47 is removed using an etch mask, and then a low concentration of impurities are ion implanted to form a source / drain region (not shown). In this case, the second insulating layer 39 is removed by a wet etching process. (See FIG. 3D)

Next, the third photoresist pattern 47 is removed.

Next, a first interlayer insulating film 49 is formed on the entire surface of the semiconductor substrate including the gate electrode 33.

Next, a fourth photoresist pattern 51 is formed on the first interlayer insulating layer 49 to expose a predetermined region of the cell region I and a portion of the decoupling capacitor of the NMOS region II. (See Figure 3E)

Next, the first interlayer insulating layer 49 and the first insulating layer 37 of the cell region I are etched using the fourth photoresist pattern 51 as an etch mask to form the gate electrode 33 and the mask insulating layer pattern 35. The first insulating film spacer 38 is formed on the sidewalls of the Ns, and the first interlayer insulating film 49 of the NMOS region II and the mask insulating film pattern 35 having a predetermined thickness are etched to form a landing plug contact hole. (See Figure 3f)

Next, the fourth photoresist pattern 51 is removed.

Next, a conductive layer 53 filling the landing plug contact hole is formed. In this case, the conductive layer 53 is formed of a polycrystalline silicon layer. (See Figure 3g)

Next, the conductive layer 53 is planarized to form landing plugs 54 and 55 in the cell region I and the NMOS region II. In this case, the planarization etching process is performed by a chemical mechanical polishing (hereinafter referred to as CMP) process using the mask insulating film pattern 35 as a polishing barrier. (See Figure 3h)

Next, a second interlayer insulating film 57 is formed over the entire surface.

Next, a fifth portion exposing a portion intended as a bit line contact in the cell region I and a portion intended as a contact for connecting Vss in the NMOS region II above the second interlayer insulating layer 57. The photosensitive film pattern 59 is formed.

Next, the second interlayer dielectric layer 57 is etched using the fifth photoresist pattern 59 as an etch mask to contact the bit line contact hole 60 in the cell region I and the Vss contact hole in the NMOS region II. Form 61. (See Figure 3i)

Next, the fifth photoresist pattern 59 is removed.

Thereafter, a sixth photoresist pattern 67 is formed on the entire surface of the PMOS region III to expose a portion intended for bit line contact.

Next, the second bit line contact hole is formed by removing the second interlayer insulating layer 57 and the first interlayer insulating layer 49 using the sixth photoresist pattern 67 as an etch mask. (See Figure 3j)

4A and 4B are a plan view and a cross-sectional view showing a decoupling capacitor formed in the NMOS region II. A contact plug 63 for power connection is provided at both edges of the gate electrode 33, and the semiconductor substrate 31 is provided. A contact plug 65 for connecting Vss is provided in the source / drain region 32 of the.

In this case, the semiconductor substrate 31 and the gate electrode 33 are used as electrodes, and the gate insulating film pattern 34 is used as a dielectric film to form a first decoupling capacitor, and the gate electrode 33 and the landing plug ( 54 is used as an electrode, and the mask insulating film pattern 35 is used as a dielectric film to form a second decoupling capacitor.

 The above structure has the effect that two capacitors are connected in parallel as shown in FIG. 4C.

The source / drain region 32 and the landing plug 54 of the decoupling capacitor formed by the above method are connected to Vss, and the gate electrode 33 is connected to power.

As described above, the decoupling capacitor and the method of forming the semiconductor device according to the present invention are formed by using a NMOS transistor to form a decoupling capacitor for storing the internal voltage of the DRAM, and then forming a mask insulating film pattern on the gate electrode of the NMOS transistor. After forming a trench by removing a predetermined thickness to form a landing plug by embedding a conductive layer, and connecting Vss to the landing plug to increase cell capacitance without additional processing, thereby improving cell efficiency, and thus device There is an advantage to improve the operating characteristics and high integration of.

1 is a schematic diagram showing a peripheral circuit portion of a typical double data rate dynamic random access memory (DDR DRAM).

2A and 2B are a plan view and a cross-sectional view of a decoupling capacitor according to the prior art.

2C is a circuit diagram of a decoupling capacitor formed by the prior art.

3A to 3J are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.

4A and 4B are a plan view and a cross-sectional view of a decoupling capacitor according to the present invention.

4C is a circuit diagram of a decoupling capacitor formed by the prior art.

<Description of Symbols for Major Parts of Drawings>

11: drive circuit part 13, 15: decoupling capacitor

21 and 31: semiconductor substrates 22 and 32: source / drain regions

23, 34: gate insulating film 24, 33: gate electrode

25, 35: mask insulating film pattern 26, 38: first insulating film spacer

27, 40: second insulating film spacer 28, 65: contact plug for connecting Vss

29, 63: contact plug for gate power connection 37: first insulating film

39: second insulating film 41: first photosensitive film pattern

43: second photosensitive film pattern 45: trench

47: third photosensitive film pattern 49: first interlayer insulating film

51: fourth photosensitive film pattern 53: conductive layer

54, 55: landing plug 57: second interlayer insulating film

59: fifth photoresist pattern 60: bit line contact hole

61: contact hole for connecting Vss 67: sixth photosensitive film pattern

Claims (2)

A first decoupling capacitor comprising a gate insulating film used as a dielectric film of a capacitor on a semiconductor substrate, a gate electrode on which a mask insulating film pattern is stacked on the gate insulating film; And a second decoupling capacitor comprising the gate electrode, the mask insulating film pattern, and a landing plug included in the mask insulating film pattern. Forming a gate electrode having a gate insulating film and a mask insulating film pattern stacked on the semiconductor substrate including a cell region, an NMOS region, and a PMOS region; Forming a first insulating film and a second insulating film on an entire surface including the gate electrode; Etching portions of the NMOS region where the decoupling capacitor is to be formed and first and second insulating layers of the PMOS region, and forming spacers on sidewalls of the PMOS region gate electrode; Etching the first and second insulating layers of the NMOS region to form a spacer on sidewalls of the NMOS region gate electrode, and forming a trench by etching a mask insulating layer of a portion where the decoupling capacitor is to be formed to a predetermined depth; Etching a second insulating film of the cell region; Forming a first interlayer insulating film on an entire surface of the semiconductor substrate including the gate electrode; Forming a landing plug contact hole exposing a portion where a decoupling capacitor of a predetermined region of the cell region and an NMOS region is to be formed; Forming a polycrystalline silicon layer filling the landing plug contact hole; Forming a landing plug by planar etching to expose the mask insulating layer; Forming a second interlayer insulating film on an entire surface of the semiconductor substrate; Etching the second interlayer insulating layer to form first bit line contact holes in the cell region and the NMOS region; And Etching the first and second interlayer insulating layers to form second bit line contact holes in the PMOS region; Decoupling capacitor forming method of a semiconductor device comprising a.