KR100478485B1 - Method for adjusting ion injection angle in semiconductor device - Google Patents
Method for adjusting ion injection angle in semiconductor device Download PDFInfo
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- KR100478485B1 KR100478485B1 KR10-2002-0060308A KR20020060308A KR100478485B1 KR 100478485 B1 KR100478485 B1 KR 100478485B1 KR 20020060308 A KR20020060308 A KR 20020060308A KR 100478485 B1 KR100478485 B1 KR 100478485B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
본 발명은 이온 주입 장비의 이온 주입 각도의 모니터링을 손쉽고 정확하게 수행하여 비대칭적인 소자 구조를 미연에 방지할 수 있도록 한 이온 주입 각도의 모니터링방법을 제공하는 것으로, 이에 따른 조정방법은, 폴리실리콘이 증착된 실리콘 웨이퍼의 위에 포토레지스트 패턴을 형성하는 단계; 이온 주입 장비의 이온 주입 각도를 설정한 후 상기 이온 주입 장비를 이용하여 상기 포토레지스트 패턴의 위로 인(P)을 이온 주입하는 단계; 상기 이온 주입 후에 상기 포토레지스트 패턴의 제거하고, 불산용액을 이용한 습식 식각을 통해 상기 폴리실리콘에 요철을 형성하는 단계; 상기 요철이 형성된 폴리실리콘만이 남은 실리콘 웨이퍼를 단층 촬영하여 요홈의 내측벽면과 수직의 가상선이 이루는 입사각을 측정하여 상기 인이 이온 주입되는 입사각을 파악하는 단계; 및 상기 입사각이 0도가 아닐 경우 상기 이온 주입 장비의 이온 주입 각도가 0도가 되도록 재설정하여 실제 이온을 주입하는 반도체 소자의 제조과정에 적용하는 단계를 포함한다.The present invention provides a method for monitoring the ion implantation angle to easily and accurately monitor the ion implantation angle of the ion implantation equipment to prevent the asymmetrical device structure in advance. Forming a photoresist pattern on the silicon wafer; Ion implanting phosphorus (P) onto the photoresist pattern using the ion implantation device after setting an ion implantation angle of an ion implantation device; Removing the photoresist pattern after the ion implantation, and forming irregularities in the polysilicon through wet etching using a hydrofluoric acid solution; A tomography of the silicon wafer having only the uneven polysilicon formed thereon to measure an incident angle formed by an imaginary line perpendicular to the inner wall of the groove to determine an incident angle at which phosphorus is ion implanted; And resetting the ion implantation angle of the ion implantation device to 0 degree when the incident angle is not 0 degree, and applying the same to a manufacturing process of a semiconductor device in which actual ions are implanted.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 좀 더 상세하게는 이온 주입 각도를 모니터링하여 제품의 성능을 향상시키는 반도체 소자의 이온 주입 각도 조정방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for adjusting the ion implantation angle of a semiconductor device for monitoring the ion implantation angle to improve the performance of the product.
일반적으로 모스 소자(MOS Device)는 반도체 기판에 형성된 소스/드레인 영역과 이 소스/드레인 영역이 형성된 기판 상에 산화막과 게이트 폴리가 형성된 구조를 가진다.In general, a MOS device has a structure in which an oxide film and a gate poly are formed on a source / drain region formed in a semiconductor substrate and a substrate on which the source / drain region is formed.
그리고, 모스 소자는 채널의 종류에 따라 N 모스 트랜지스터와 P 모스 트랜지스터로 나눌 수 있으며, 특히 상보형 모스 트랜지스터는 N 모스 트랜지스터와 P 모스 트랜지스터가 하나의 기판에 형성된 것이다.In addition, the MOS device may be divided into N MOS transistor and P MOS transistor according to the type of channel. In particular, in the complementary MOS transistor, the N MOS transistor and the P MOS transistor are formed on one substrate.
상보형 모스 소자는 게이트 폴리가 형성된 P형 및 N형 모스 트랜지스터 영역을 포함하는 반도체 기판 상부면에 캡(cap) 산화막을 형성하고, 게이트 폴리를 마스크로 P형 및 N형 모스 트랜지스터 영역에 선택적으로 N형 및 P형 불순물을 이온 주입한다.The complementary MOS device forms a cap oxide film on the upper surface of the semiconductor substrate including the P-type and N-type MOS transistor regions in which the gate poly is formed, and selectively forms the P-type and N-type MOS transistor regions using the gate poly as a mask. N-type and P-type impurities are ion implanted.
이후, 반도체 기판 상부 전면에 산화막을 형성하고, 산화막이 각 게이트 폴리 측벽에만 남도록 이방성 식각하여 측벽 스페이서를 형성한다. 그리고, 게이트 폴리와 측벽 스페이서를 마스크로 P형 및 N형 모스 트랜지스터 영역에 선택적으로 N형 및 P형 불순물을 이온 주입하여 소스/드레인 영역을 형성한다.Thereafter, an oxide film is formed on the entire upper surface of the semiconductor substrate, and the sidewall spacers are formed by anisotropic etching so that the oxide film remains only on each gate poly sidewall. The source / drain regions are formed by selectively implanting N-type and P-type impurities into the P-type and N-type MOS transistor regions using the gate poly and sidewall spacers as masks.
이와 같은 제조과정에서 이온을 주입할 때, 게이트 전극을 형성한 후에는 이온을 주입하는 장비를 이용하여 웨이퍼의 표면으로 이온을 주입하게 되는 데, 이온이 주입되는 웨이퍼 면과 주입될 가속되는 이온과의 입사각이 0도를 유지해야만 소스 및 드레인 구조가 대칭적으로 되어 바람직한 성능을 나타내는 반도체 소자를 얻을 수 있게 된다.When ion is implanted in the manufacturing process, after the gate electrode is formed, the ion is implanted into the surface of the wafer by using an ion implantation device. Only when the incident angle of is maintained at 0 degrees, the source and drain structures become symmetrical to obtain a semiconductor device exhibiting desirable performance.
그러나 이온 주입 장비의 이상으로 인하여 조금이라도 0도를 유지하지 못할 경우 비대칭적인 소스 및 드레인 구조가 발생되고, 결과적으로 비정상적인 트랜지스터 소자나 나타난다.However, failure to maintain even 0 degrees due to anomalies in ion implantation equipment results in asymmetrical source and drain structures, resulting in abnormal transistor elements.
본 발명은 이와 같은 문제점을 해결하기 위해 제안된 것으로, 이온 주입 장비의 이온 주입 각도의 모니터링을 손쉽고 정확하게 수행하여 비대칭적인 소자 구조를 미연에 방지할 수 있도록 한 이온 주입 각도의 모니터링방법을 제공하는 데 있다.The present invention has been proposed to solve the above problems, and provides an ion implantation angle monitoring method that can easily and accurately monitor the ion implantation angle of the ion implantation equipment to prevent the asymmetrical device structure in advance. have.
상기와 같은 기술적 과제를 달성하기 위하여, 본 발명의 조정방법은, 폴리실리콘이 증착된 실리콘 웨이퍼의 위에 포토레지스트 패턴을 형성하는 단계; 이온 주입 장비의 이온 주입 각도를 설정한 후 상기 이온 주입 장비를 이용하여 상기 포토레지스트 패턴의 위로 인(P)을 이온 주입하는 단계; 상기 이온 주입 후에 상기 포토레지스트 패턴의 제거하고, 불산용액을 이용한 습식 식각을 통해 상기 폴리실리콘에 요철을 형성하는 단계; 상기 요철이 형성된 폴리실리콘만이 남은 실리콘 웨이퍼를 단층 촬영하여 요홈의 내측벽면과 수직의 가상선이 이루는 입사각을 측정하여 상기 인이 이온 주입되는 입사각을 파악하는 단계; 및 상기 입사각이 0도가 아닐 경우 상기 이온 주입 장비의 이온 주입 각도가 0도가 되도록 재설정하여 실제 이온을 주입하는 반도체 소자의 제조과정에 적용하는 단계를 포함한다.In order to achieve the above technical problem, the adjustment method of the present invention comprises the steps of: forming a photoresist pattern on a silicon wafer on which polysilicon is deposited; Ion implanting phosphorus (P) onto the photoresist pattern using the ion implantation device after setting an ion implantation angle of an ion implantation device; Removing the photoresist pattern after the ion implantation, and forming irregularities in the polysilicon through wet etching using a hydrofluoric acid solution; A tomography of the silicon wafer having only the uneven polysilicon formed thereon to measure an incident angle formed by an imaginary line perpendicular to the inner wall of the groove to determine an incident angle at which phosphorus is ion implanted; And resetting the ion implantation angle of the ion implantation device to 0 degree when the incident angle is not 0 degree, and applying the same to a manufacturing process of a semiconductor device in which actual ions are implanted.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 모니터링 방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a monitoring method according to the present invention.
먼저 도 1에 도시한 바와 같이, 실리콘 웨이퍼(1)의 표면에 폴리실리콘(3)을 5000Å 내지 70000Å 두께로 증착한다.First, as shown in FIG. 1, polysilicon 3 is deposited on the surface of the silicon wafer 1 to a thickness of 5000 kPa to 70000 kPa.
그리고 도 2에 도시한 바와 같이, 폴리실리콘(3)이 증착된 그 위에 포토레지스트를 1.0㎛ 내지 1.2㎛ 정도 두께로 코팅한 후, 메탈 라인 시디(Metal line Critical Dimension)가 0.5㎛ 이상 되는 포토레지스트 패턴(5)을 형성한 후, 현상까지 실시하여 포토레지스트 프로파일을 형성한다.As shown in FIG. 2, after the photoresist is coated with a thickness of about 1.0 μm to about 1.2 μm on the polysilicon 3 deposited thereon, the photoresist has a metal line critical dimension of 0.5 μm or more. After the pattern 5 is formed, development is carried out to form a photoresist profile.
그 후에 포토레지스트 패턴(5)이 형성된 그 위로 원자량이 31인 인 도오즈(Phosporus dose)(7)를 3E14 내지 5E14 개/cm2 농도로 70KeV ~ 90KeV 에너지 대역으로 이온을 주입하되, 이온 주입 장비를 이용한 이온 주입 입사각이 0도(°)가 되도록 세팅 후 주입한다.Thereafter, a photoresist pattern 5 is formed thereon with a dose of phosphorus (7) having a atomic weight of 31 at a concentration of 3E14 to 5E14 pieces / cm 2 at a concentration of 70KeV to 90KeV, but with ion implantation equipment. After implantation, the ion implantation angle is set to 0 degrees (°).
이온 주입이 완료되면, 도 3 및 도 4에 도시한 바와 같이 포토레지스트 패턴을 제거한 후 폴리실리콘(3)을 에치하게 되며, 폴리실리콘 에치를 위해 불산(HF)을 물에 100:1 의 비율로 희석한 불산용액을 이용한다. 이때 원자량 31인 인 도오즈가 주입된 영역의 에칭율이 빠르기 때문에 요철이 나타난다.After the ion implantation is completed, as shown in FIGS. 3 and 4, the photoresist pattern is removed and the polysilicon 3 is etched, and hydrofluoric acid (HF) is added to the water at a ratio of 100: 1 for etching the polysilicon. Dilute hydrofluoric acid solution is used. At this time, irregularities appear because the etching rate of the region having the atomic weight of 31 is injected fast.
만약 이온 주입각이 0도(°)로 세팅되었음에도 불구하고 이온 주입 장비의 문제로 인하여 틀어져 있을 경우, 도 4에 도시한 바와 같은 프로파일이 형성된다. 이러한 프로파일은 습식 에치를 통해 형성되며, 셈장비를 이용한 단층 촬영을 실시하여 확인할 수 있게 된다.If the ion implantation angle is set to 0 degrees (°), but is misaligned due to the problem of the ion implantation equipment, a profile as shown in FIG. 4 is formed. These profiles are formed through wet etch, and can be confirmed by performing tomography using a counting device.
셈장비를 이용한 확인 결과 이온 주입 각도가 기울어져 있다면, 그 기울어진 만큼 이온 주입 장비의 이온 주입 각도를 조정한 후, 실제 반도체 소자의 제조에 적용하게 된다.If the ion implantation angle is tilted as a result of the check using the counting device, the ion implantation angle of the ion implantation equipment is adjusted as much as the tilted angle, and then applied to the fabrication of the actual semiconductor device.
즉, 실리콘 웨이퍼의 표면에 게이트를 형성하고, 게이트의 양측에 소스 및 드레인 형성을 위한 이온을 주입하게 되며, 이때 상술한 바와 같은 과정을 통해 이온 주입 장비의 이온 주입 각도는 입사각이 0도가 되도록 세팅되어진다.That is, a gate is formed on the surface of the silicon wafer, and ions for source and drain formation are implanted on both sides of the gate. In this case, the ion implantation angle of the ion implantation apparatus is set such that the incidence angle is 0 degrees. It is done.
실시예Example
이온 주입 장비를 이용한 이온 주입시 웨이퍼 면에 대한 입사각이 7도가 된 경우를 도 5을 참조하여 살펴보면,Referring to FIG. 5, the incident angle of the wafer surface during the ion implantation using the ion implantation apparatus becomes 7 degrees.
폴리실리콘(3)이 증착된 실리콘 웨이퍼(1)에 포토레지스트를 코팅하고, 포토레지스트 패턴을 형성한 후 감광되지 않은 나머지 포토레지스트를 제거한다.A photoresist is coated on the silicon wafer 1 on which the polysilicon 3 is deposited, and after forming a photoresist pattern, the remaining unresisted photoresist is removed.
남겨진 포토레지스트 패턴 위로 원자량 31인 인 도오즈를 전제한 바와 같이 입사각이 0도가 되도록 이온 주입한다.Ion implantation is performed so that the incident angle is 0 degrees, assuming that the indium oxide having an atomic weight of 31 is placed on the remaining photoresist pattern.
그리고 나서, 습식 에치를 실시하여 형성된 반도체 소자의 프로파일을 셈장비를 이용하여 확인한다.Then, the profile of the semiconductor element formed by performing wet etch is confirmed using a counting apparatus.
그러면, 폴리실리콘(3)에 형성된 요홈(9)의 내측벽면과 요홈(9)의 저면이 이루는 각도를 세타(θ)라 하고, 요홈(9)의 내측벽면과 가상의 수직선(V)이 이루는 각인 입사각을 파이(φ)라 하며, 가상의 수직선(V)과 요홈(9)의 저면 및 내측벽면으로 형성된 직각삼각형에서 밑변을 a, 높이를 b로 정의한다.Then, the angle formed between the inner wall surface of the groove 9 formed in the polysilicon 3 and the bottom surface of the groove 9 is called theta θ, and the inner wall surface of the groove 9 and the virtual vertical line V are formed. The marking angle of incidence is called phi, and the base side is defined as a and the height is b in the right triangle formed by the imaginary vertical line V and the bottom and inner wall of the groove 9.
Tanθ = b/a 이므로, a 및 b값을 측정하면 θ값을 알 수 있게 된다. 이렇게 측정한 값이 0도가 아니고 다른 값을 나타낸다면, 이온 주입 장비를 이용한 이온주입시 입사각이 0도가 되도록 재조정을 실시한다.Since Tanθ = b / a, the value of θ can be known by measuring the values of a and b. If the measured value is different from 0 degrees and the value is different, the readjustment is performed so that the incident angle is 0 degrees during ion implantation using ion implantation equipment.
그리고 나서, 실제 반도체 소자의 제조시 이온 주입하게 되면 조정된 입사각대로 이온 주입이 이루어지게 된다.Then, when ion implantation is performed during the manufacture of the actual semiconductor device, ion implantation is performed at the adjusted incidence angle.
이와 같이 본 발명은 실제 반도체 소자의 제조 이전에 이온 주입 장비의 이온 주입 각도가 제대로 세팅되었는 지 모니터링 한 후 조정을 통하여 실제 반도체 소자 제작시에는 이온 주입각이 정확하게 이루어지도록 한다.As described above, the present invention monitors whether the ion implantation angle of the ion implantation equipment is properly set prior to the actual fabrication of the semiconductor device, and then accurately adjusts the ion implantation angle when fabricating the actual semiconductor device.
따라서 완성된 반도체소자들 중에서 불량으로 판정된 수많은 반도체소자를 확인하지 않고서도 이온주입장비가 정확하게 세팅되지 않았음을 확인할 수 있어 반도체 소자의 수율을 크게 향상시킨다.Therefore, it is possible to confirm that the ion implantation equipment is not set correctly without checking a large number of semiconductor devices that are determined to be defective among the completed semiconductor devices, thereby greatly improving the yield of semiconductor devices.
도 1은 본 발명에 따른 이온 주입 각도의 조정을 위해 실리콘 웨이퍼에 폴리실리콘을 증착한 상태를 도시한 단면도이고,1 is a cross-sectional view showing a state in which polysilicon is deposited on a silicon wafer for adjusting an ion implantation angle according to the present invention;
도 2는 도 1에 이어서 폴리실리콘 위로 포토레지스트 패턴을 형성하고 이온을 주입하는 상태를 도시한 단면도이고,FIG. 2 is a cross-sectional view illustrating a state of forming a photoresist pattern and implanting ions onto polysilicon following FIG. 1;
도 3은 도 2에 이어서 포토레지스트 패턴을 제거한 상태를 도시한 단면도이고,3 is a cross-sectional view illustrating a state in which a photoresist pattern is removed following FIG. 2;
도 4는 도 3에 이어서 폴리실리콘을 제거한 상태를 도시한 단면도이고,4 is a cross-sectional view illustrating a state in which polysilicon is removed following FIG. 3;
도 5는 본 발명에 따른 이온 주입 각도 조정방법을 설명하기 위해 입사각이 기울어지게 이온 주입된 상태를 도시한 단면도이다.5 is a cross-sectional view illustrating a state in which the incidence angle is ion implanted to explain the ion implantation angle adjusting method according to the present invention.
Claims (5)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950015566A (en) * | 1993-11-24 | 1995-06-17 | 김광호 | Symmetric ion implantation method |
| JP2000138178A (en) * | 1998-08-25 | 2000-05-16 | Fujitsu Ltd | Method for evaluating ion implantation distribution, manufacture of semiconductor device, and method for designing semiconductor device |
| US6437350B1 (en) * | 2000-08-28 | 2002-08-20 | Varian Semiconductor Equipment Associates, Inc. | Methods and apparatus for adjusting beam parallelism in ion implanters |
| US6451621B1 (en) * | 2002-01-16 | 2002-09-17 | Advanced Micro Devices, Inc. | Using scatterometry to measure resist thickness and control implant |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950015566A (en) * | 1993-11-24 | 1995-06-17 | 김광호 | Symmetric ion implantation method |
| JP2000138178A (en) * | 1998-08-25 | 2000-05-16 | Fujitsu Ltd | Method for evaluating ion implantation distribution, manufacture of semiconductor device, and method for designing semiconductor device |
| US6437350B1 (en) * | 2000-08-28 | 2002-08-20 | Varian Semiconductor Equipment Associates, Inc. | Methods and apparatus for adjusting beam parallelism in ion implanters |
| US6451621B1 (en) * | 2002-01-16 | 2002-09-17 | Advanced Micro Devices, Inc. | Using scatterometry to measure resist thickness and control implant |
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