KR100478358B1 - Protection circuit against a electrostatic discharge of ic for managing battery - Google Patents

Abstract

The present invention relates to a protection circuit against the electrostatic discharge of the battery management IC, and more particularly, to compensate the peripheral application circuit for the functional operation of the battery management IC and the resistance of the electrostatic discharge (ESD) implemented by the battery management IC itself. It is possible to secure the stable reliability of the product, and by using the capacitor and transient voltage suppression element in the peripheral application circuit to generate the current path by the high current to the battery, so that the high current can be delivered in a short time, so the electrostatic energy flowing into the IC for battery management Minimize the damage.

Description

PROTECTION CIRCUIT AGAINST A ELECTROSTATIC DISCHARGE OF IC FOR MANAGING BATTERY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit of an IC for battery management, and more particularly, to configure a peripheral circuit to prevent the IC from being easily damaged by electrostatic discharge (ESD) and to maintain stable functional operation. The present invention relates to a protection circuit against electrostatic discharge of an IC for battery management which prevents the IC from being damaged by the latch-up phenomenon of the IC.

In general, as shown in FIG. 1, the battery management circuit 10 may be controlled by the battery management IC 11 and the battery management IC 11 to control the current flow of the battery power source 12, 13. ), The first to sixth resistors R1 to R6 and the first to fourth capacitors C1 to C4 which protect against the electrostatic discharge (ESD) introduced into the respective input and output terminals of the battery management IC 11. )

The battery management IC 11 includes a plurality of input / output terminals, and controls each operation of the battery. Here, the battery management IC 11 uses MAXIM's DS276x Battery Monitoring IC. In addition, the battery management IC 11 includes a battery voltage B + detecting terminal VIN, an input terminal VDD of the battery voltage B +, an input terminal VSS of the battery ground voltage B-, and a sleep mode. Release input terminal (PS), low pass filter external capacitor connection terminal (IS1, IS2), data communication terminal (DQ), charge / discharge current detection terminal (SNS), discharge control terminal (DC), charge control terminal (CC) Charging side potential detection terminal (PLS) is provided.

The asynchronous serial communication terminal (D) can send and receive data to and from the host in one line. The battery power terminals (B + and B-) supply the battery power, and the power output terminals (P + and P-) supply power. Outputs

The first MOSFET 12 has a gate connected to the DC terminal of the battery management IC 11, a source connected to the battery power supply B +, and a drain connected to the drain of the second MOSFET 13 so that current flows in the battery power. To control.

The second MOSFET 13 has a gate connected to the CC terminal of the battery management IC 11, a drain and a source connected between the first MOSFET 12 and the power output terminal P +, and interlocked with the first MOSFET 12 so as to interoperate with the battery. Control the current flow in the power supply.

The first to sixth resistors R1 to R6 are connected to respective input / output terminals (VDD terminal, VIN terminal, DC terminal, CC terminal, PLS terminal, and DQ terminal) of the battery management IC 11 to discharge high current and high voltage. Attenuate (ESD).

The first capacitor C1 is connected between the VDD terminal of the battery management IC 11 connected to the battery power terminals B + and B- and the VSS terminal to bypass the power supply of the battery management IC 11. Maintain power stabilization.

The second capacitor C2 is connected between the IS1 terminal and the IS2 terminal of the battery management IC 11 to suppress the transfer of external noise when the battery management IC 11 senses a current.

The third capacitor C3 is connected in parallel between the input side of the first MOSFET 12 and the output side of the second MOSFET 13 to suppress power overshooting during switching of the first and second MOSFETs 12 and 13 to maintain power supply stabilization. .

The fourth capacitor C4 is connected in parallel between the power output terminals P + and P- to maintain a stable output power for bypass of the output power.

However, such a conventional battery management circuit 10 is incapable of using the IC for battery management in the contact discharge ± 8㎸ and the air discharge ± 15㎸ which is the level 4 of the electrostatic discharge (ESD) standard 'IEC 1000-4-2'. A malfunction occurs and a latch-up phenomenon occurs in which the power supply is short-circuited inside the battery management IC 11, thereby causing the function management of the battery management IC 11 to be stopped and burned out. Normal operation will be restored when B + and B- are cut off, but the internal power of the battery management IC 11 does not cut off the battery power terminals B + and B-, resulting in increased current consumption and shortening of battery life. And there is a problem that can explode.

Therefore, an object of the present invention is to solve the above problems, and the stable reliability of the product by complementing the resistance of the electrostatic discharge (ESD) implemented by the peripheral application circuit and the battery management IC itself for the functional operation of the battery management IC By using the capacitor and the transient voltage suppression element in the surrounding application circuit, the current path by the high current is generated toward the battery so that the high current can be delivered in a short time to minimize the damage by minimizing the electrostatic energy flowing into the battery management IC. To reduce it.

Features of the present invention for achieving the above object,

A battery management IC having a plurality of input / output terminals including a data communication terminal (DQ) and controlling a charge / discharge operation of a battery, a gate connected to a discharge control terminal (DC) of the battery management IC, and a battery power source A source is connected to the terminal B + to control the discharge current flow of the battery power, a drain is connected to the drain of the first MOSFET, and a gate is connected to the charge control terminal CC of the battery management IC. In the protection circuit for the electrostatic discharge of the battery management IC comprising a second MOSFET for controlling the flow of the charging current of the battery power source is connected to the power source output terminal (P +) in conjunction with the first MOSFET,

Connected between the data communication terminal DQ and the ground power supply terminal B- of the battery, the data communication terminal operates when the high current of the electrostatic discharge is drawn into the data communication terminal, thereby bypassing the high current to the battery ground power supply terminal B-. A first transient voltage suppression element; It is connected between a power ground output terminal (P-) and the battery ground power terminal (B-) and is operated when a high current of electrostatic discharge is drawn into the power ground output terminal (P-) to supply a high current to the battery ground power terminal (B-). It characterized in that it comprises a second transient voltage suppression element to bypass.

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The present invention further includes a first resistor disposed between the battery power supply terminal B + and the input terminal VDD of the battery voltage B +, wherein the input terminal is prevented from latching up the battery management IC. It is preferable to set the value of the first resistor so that the voltage drop due to the high current flowing in (VDD) is 1 V or less.

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Further, in the present invention, a third capacitor installed in parallel with the first MOSFET and the second MOSFET is connected between the battery power terminal B + and the power output terminal P +, and the third capacitor is connected to the power output terminal ( The capacitance value is preferably set so that a high current of the electrostatic discharge drawn into P +) can flow to the battery power supply terminal B +.

In addition, the present invention is connected between the power output terminals (P +, P-), but the capacity to flow the high current of the electrostatic discharge flowing into the power output terminals (P +, P-) to the power output terminals (P-, P +) of the opposite polarity It is preferred to further include a fourth capacitor having a value.

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Hereinafter, the configuration of the protection circuit against electrostatic discharge of the battery management IC according to the present invention will be described in detail with reference to FIG.

2 is a circuit diagram showing a configuration of a protection circuit against electrostatic discharge of the battery management IC according to an embodiment of the present invention. In FIG. 2, the same code | symbol is attached | subjected about the same code | symbol as the conventional battery management circuit shown in FIG.

2, the protection circuit 100 for electrostatic discharge of the battery management IC according to the present invention, the battery management IC 11, the first MOSFET 12, the second MOSFET 13, 1 to 6 resistors R1 to R6, first to fourth capacitors C1 to C4, a first transient voltage suppressor 110, and a second transient voltage suppressor 120.

The battery management IC 11 includes a plurality of input / output terminals, and controls each operation of the battery. Here, the battery management IC 11 uses MAXIM's DS276x Battery Monitoring IC.

The first MOSFET 12 has a gate connected to the DC terminal of the battery management IC 11, a source connected to the battery power supply B +, and a drain connected to the drain of the second MOSFET to control the flow of discharge current of the battery power supply. do.

The second MOSFET 13 has a gate connected to the CC terminal of the battery management IC 11, a drain connected to the drain of the first MOSFET 12, and a source connected to the power output terminal P + to interlock with the first MOSFET 12. Control the charging current flow of the battery power source.

The first to sixth resistors R1 to R6 are connected to respective input / output terminals (VDD terminal, VIN terminal, DC terminal, CC terminal, PLS terminal, and DQ terminal) of the battery management IC 11 to discharge high current and high voltage. Attenuate (ESD). Here, the first resistor R1 connected to the VDD terminal of the battery management IC 11 has a resistance value such that the voltage drop due to the high current flowing to the VDD terminal is 1 V or less to prevent latch-up of the battery management IC 11. 1.0 ms) is set.

The asynchronous serial communication terminal (D) can send and receive data to and from the host in one line, and the battery power terminal (B +) and battery ground power terminal (B-: hereinafter, battery power terminal B-) are batteries Supplies power, and the power output terminal P + and the power ground output terminal P- (hereinafter referred to as power output terminal P-) output power.

The first capacitor C1 is connected between the VDD terminal of the battery management IC 11 connected to the battery power terminals B + and B- and the VSS terminal to bypass the power supply of the battery management IC 11. Maintain power stabilization.

The second capacitor C2 is connected between the IS1 terminal and the IS2 terminal of the battery management IC 11 to suppress the transfer of external noise when the battery management IC 11 senses a current.

The third capacitor C3 is connected in parallel between the input side of the first MOSFET 12 and the output side of the second MOSFET 13 to suppress power overshooting during switching of the first and second MOSFETs 12 and 13 to maintain power supply stabilization. . Here, the third capacitor C3 has a capacitance value of 0.1 mA so that the high current of the electrostatic discharge flowing into the power supply output terminal P + may flow to the battery power supply terminal B +.

The fourth capacitor C4 is connected in parallel between the power output terminals P + and P- to maintain a stable output power for bypass of the output power. Herein, the fourth capacitor C4 has a capacitance value of 0.1 mA so that the high current of the electrostatic discharge flowing into the power output terminals P + and P- may flow to the power output terminals P- and P + of opposite polarity. In addition, the capacity of the fourth capacitor (C4) and the breakdown voltage are calculated as 330 Ω / 150 방전 to 15 ㎸, 15 A / 1 방전 discharge energy in accordance with IEC 1000-4-2. When applying 'Capacity type', it is calculated as (15000V × 150kV) / (100000kV) = 22.4V, and the internal resistance (ESR) of 0.1kV is about 0.2kV, so if the internal voltage is 25V or more do.

The first transient voltage suppression (TVS) element 110 is connected between the asynchronous serial communication terminal D and the battery power supply terminal B- to draw a high current of electrostatic discharge into the asynchronous serial communication terminal D-. Operation to bypass the high current to the battery power supply (B-).

The second transient voltage suppressing element 120 is connected between the power output terminal (P-) and the battery power terminal (B-) is operated when the high current of the electrostatic discharge into the power output terminal (P-) to convert the high current into the battery power terminal ( Bypass to B-).

Hereinafter, an operation of the protection circuit against electrostatic discharge of the battery management IC according to the present invention will be described in detail with reference to FIG. 2.

First, the protection circuit 100 for electrostatic discharge of the battery management IC according to the present invention passes the high current of the incoming electrostatic discharge (ESD) to the battery as quickly as possible while maintaining the functional operation of the battery management IC 11. It is configured to minimize the electrostatic energy delivered to each input, output terminal of the battery management IC (11).

On the other hand, the characteristics of the first and second transient voltage suppression elements 110 and 120 have a high internal resistance of several kΩ or more at the operating voltage or less, and have physical properties that change to several m < > By operating by high current at the moment of changing the current flow.

That is, the first transient voltage suppression element 110 is operated when the high current of the electrostatic discharge is drawn into the asynchronous serial communication terminal D to form a path between the asynchronous serial communication terminal D and the battery power source B- so that the high current is generated. Bypasses the battery power supply terminal B- to protect against malfunction, latch-up and burnout of the battery management IC 11.

In addition, the second transient voltage suppression element 120 is operated when the high current of the electrostatic discharge is drawn into the power output terminal P- to form a path between the power output terminal P- and the battery power terminal B- to generate a high current. Bypassing to the power supply terminal B- protects the battery management IC 11 from malfunction, latch up and burnout.

At this time, since the internal current sense resistance of the battery management IC 11 is about 25 mΩ, the inflow path is bypassed by the first and second transient voltage suppression elements 110 and 120 to block the direct inflow of the battery management IC 11. have.

As described above, according to the protection circuit against the electrostatic discharge of the battery management IC according to the present invention, the peripheral application circuit for the functional operation of the battery management IC and the resistance of the electrostatic discharge (ESD) implemented by the battery management IC itself. It is possible to secure stable reliability of the product by creating a current path by high current toward the battery by using a capacitor and transient voltage suppression element among peripheral application circuits, so that a high current can be delivered in a short time to enter the battery management IC. Damage can be reduced by minimizing electrostatic energy.

1 is a circuit diagram illustrating a configuration of a battery management protection circuit according to an exemplary embodiment.

2 is a circuit diagram showing a configuration of a protection circuit against electrostatic discharge of the battery management IC according to an embodiment of the present invention;

<Description of the symbols for the main parts of the drawings>

11: battery management IC 12, 13: first, second MOSFET

110, 120: first and second transient voltage suppressors C1 to C4: first to fourth capacitors

R1 to R6: first to sixth resistors

Claims (4)

A battery management IC having a plurality of input / output terminals including a data communication terminal (DQ) and controlling a charge / discharge operation of a battery, a gate connected to a discharge control terminal (DC) of the battery management IC, and a battery power source A source is connected to the terminal B + to control the discharge current flow of the battery power, a drain is connected to the drain of the first MOSFET, and a gate is connected to the charge control terminal CC of the battery management IC. In the protection circuit for the electrostatic discharge of the battery management IC comprising a second MOSFET for controlling the flow of the charging current of the battery power source is connected to the power source output terminal (P +) in conjunction with the first MOSFET, Connected between the data communication terminal DQ and the ground power supply terminal B- of the battery, the data communication terminal operates when the high current of the electrostatic discharge is drawn into the data communication terminal, thereby bypassing the high current to the battery ground power supply terminal B-. A first transient voltage suppression element; It is connected between a power ground output terminal (P-) and the battery ground power terminal (B-) and is operated when a high current of electrostatic discharge is drawn into the power ground output terminal (P-) to supply a high current to the battery ground power terminal (B-). And a second transient voltage suppressor for bypassing the circuit. The method of claim 1, further comprising a first resistor disposed between the battery power supply terminal B + and the input terminal VDD of the battery voltage B +, wherein the input is configured to prevent latch-up of the battery management IC. A protection circuit for electrostatic discharge of a battery management IC, characterized in that the value of the first resistor is set so that the voltage drop due to the high current flowing through the terminal (VDD) is 1 V or less. The power supply terminal of claim 1, wherein a third capacitor disposed in parallel with the first MOSFET and the second MOSFET is connected between the battery power terminal B + and the power output terminal P +, and the third capacitor is connected to the power output terminal. And a capacitance value is set such that a high current of the electrostatic discharge drawn into (P +) flows to the battery power supply terminal (B +). The method of claim 1, wherein the high current of the electrostatic discharge flowing into the power output terminals (P +, P-) connected to the power output terminals (P +, P-) flows to the output terminals (P-, P +) of opposite polarity. And a fourth capacitor having a capacitance value. The protection circuit for electrostatic discharge of an IC for battery management.