TWI812319B - Fast charging protocol chip and its system - Google Patents

Abstract

Embodiments of the present invention provide a fast charging protocol chip and a system thereof. The fast charging protocol chip provided according to the embodiment of the present invention includes: an internal power supply module configured to generate an internal power supply voltage for powering the internal circuit of the fast charging protocol chip based on the input voltage of the fast charging protocol chip; power power The MOS field effect transistor is connected between the internal power supply module and the internal power supply pin of the fast charge protocol chip; and the slope detection module is configured to detect the change slope of the input voltage of the fast charge protocol chip, and based on the fast charge The change slope of the input voltage of the chip is agreed upon to control the turn-on and turn-off of the power MOS field effect transistor. By using the slope detection module to control the on and off of the power MOS field effect transistor, the internal power supply voltage of the chip can be prevented from losing power, which means that the chip will not be out of control and the area of the chip can be saved.

Description

Fast charging protocol chip and its system

The present invention generally relates to the field of integrated circuits, and in particular, to a fast charging protocol chip and its system.

Usually, in fast charging applications, you may encounter a situation where the output VBUS is short-circuited to ground. In this case, more and more applications hope that the fast charging protocol chip itself will not lose control, that is, to power the internal circuit of the chip. The internal supply voltage will not drop below the power reset voltage threshold. In the prior art, the technical means adopted to solve this technical problem is usually to utilize reverse phase blocking of Schottky diodes so that the internal supply voltage does not lose power quickly.

However, in some processes, this Schottky diode requires the use of additional masks, which increases the cost of the system. In addition, even if no additional masks are added in the process, as the power consumption of the wafer increases, In order to make the voltage drop of the Schottky diode meet the requirements, the area of the Schottky diode increases, which in turn causes the area of the wafer to increase and the cost of the wafer to increase.

Embodiments of the present invention provide a fast charging protocol chip and its system, which can use the slope detection module to control the on and off of the power MOS field effect transistor, which can save the area and cost of the chip, and when an output short circuit occurs , the power MOS field effect transistor can be turned off to prevent the chip's internal power supply voltage from losing power, so that the chip's internal circuit can work normally, that is, it will not cause the chip to lose control.

On the one hand, embodiments of the present invention provide a fast charging protocol chip, including: an internal power supply module configured to generate power for an internal circuit of the fast charging protocol chip based on an input voltage of the fast charging protocol chip. internal supply voltage; power power MOS field effect power a crystal connected between the internal power supply module and the internal power supply pin of the fast charge protocol chip; and a slope detection module configured to detect the change slope of the input voltage of the fast charge protocol chip, and based on The changing slope of the input voltage of the fast charging protocol chip controls the turn-on and turn-off of the power MOS field effect transistor.

On the other hand, embodiments of the present invention provide a fast charging system, including the fast charging protocol chip described in the first aspect.

The fast charging protocol chip and its system provided by the embodiments of the present invention can control the on and off of the power MOS field effect transistor by using the slope detection module, and can prevent the internal power supply voltage of the chip from losing power. That is to say, It will not cause the chip to run out of control, and can save the chip area.

210: Primary side pulse width modulation controller

220: Secondary side synchronous rectification

2301: Internal power supply module

2302: Input voltage detection module

2303:Fault detection circuit

2304: Gate driver

230: Fast charging protocol chip provided by existing technology

430: Fast charging protocol chip provided by the invention

4301: Internal power supply module

4302: Input voltage detection module

4303:Fault detection circuit

4304: Gate driver

4305: Slope detection module

AVDD: internal supply voltage

Cavdd: chip external capacitance

Clp: on-chip filter capacitor

comp1: first comparator

comp2: second comparator

CS: current sensing pin

D0: Parasitic diode

Dsb: Schottky diode

GATE: Gate

GND: Ground pin

I0: first current source/second current source

LDO: Low Dropout Linear Regulator

M1: Transistor

MN_ext: transistor

MP0, MP1, MP2: transistor

Np: primary side inductance

Nsec: secondary inductance

PWM: primary side pulse width modulation

R1, R2, Rdw, Rlp, Rup: resistance

slope_det: first comparison result

slope_en: second comparison result

SR: Secondary side synchronous rectification

sw_ctl: switch control signal

sw_ctli: inverted switch control signal

SW1, SW2: switch

T1: Transformer

VBUS: output voltage

VIN: input voltage

vin_div: divided voltage

vin_div_lpf: filter voltage

vin_div_lpf_shift: first shift level

vin_div_shift: second shift level

vin_low: input voltage detection signal

vref_scp: reference voltage

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. For those of ordinary skill in the art, without exerting creative efforts, they can also Other schemas can be derived from these schemas.

Figure 1 shows a schematic structural diagram of the flyback pulse width modulation control architecture; Figure 2 shows a schematic structural diagram of a fast charging control system based on the flyback pulse width modulation control architecture; Figure 3 shows the fast charging control system provided by the existing technology. A schematic diagram of the short-circuit protection implementation of the charging protocol chip; Figure 4 shows a schematic diagram of the short-circuit protection implementation of the fast charging protocol chip provided by an embodiment of the present invention; and Figure 5 shows a schematic diagram of the input voltage in the embodiment shown in Figure 4 Structural diagram of the sampling loop.

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain the invention and not to limit the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element.

In order to better understand the fast charging protocol chip and its system provided by embodiments of the present invention, the architecture and basic working principles of the AC (Alternate Current, AC)/Direct Current (DC) fast charging system are first described below. introduce. As an example, the fast charging system can adopt a fly-back architecture. For example, Figure 1 shows a schematic structural diagram of a fly-back pulse width modulation control architecture.

The fast charging system shown in Figure 1 uses a flyback architecture, and the primary/secondary inductors of transformer T1 are opposite ends. During the turn-on period of the power MOS field effect transistor M1, the primary inductor Np stores energy; during the turn-off period of the power MOS field effect transistor M1, the primary inductor Np transfers the stored energy to the secondary inductor Nsec, and the secondary inductor demagnetizes and supplies its energy to the load.

As another example, FIG. 2 shows a schematic structural diagram of a fast charging control system based on a flyback pulse width modulation control architecture. As shown in Figure 2, the AC/DC fast charging system mainly includes: primary side pulse width modulation (Pulse Width Modulation, PWM) controller 210, secondary side synchronous rectifier (Synchronous Rectifier, SR) 220 and fast charging protocol chip 230 etc., wherein the fast charging protocol chip 230 can be integrated with a fast charging protocol and a constant voltage/constant current (CV/CC) loop.

As shown in Figure 2, the PWM controller 210 can be used to control the turn-on and turn-off of the primary-side power MOS field effect transistor M1. The Schottky diode in Figure 1 is replaced with Figure 2 Synchronous rectification in the battery, which can greatly improve the efficiency of fast charging systems.

In addition, as can be seen from FIG. 2 , the input voltage VIN can generate an output voltage through a controlled transistor MN_ext (eg, an N-type metal-oxide-semiconductor (NMOS) transistor) located outside the die 230 VBUS to power subsequent devices. Among them, when the power-on initialization is completed, or any fault is detected during operation, the transistor MN_ext is disconnected to cut off the path from the input voltage VIN to VBUS, thereby protecting the entire fast charging system.

It should be noted that among all the above protections, the one with the most stringent requirements on the off time of the transistor MN_ext is the output short circuit (VBUS and GND short circuit) protection.

In order to achieve short circuit protection, a Schottky diode can be provided inside the chip 230 to prevent the internal supply voltage AVDD from also falling rapidly when the VIN voltage drops rapidly. Specifically, as shown in FIG. 3 , FIG. 3 shows a schematic diagram of a short-circuit protection implementation method of a fast charging protocol chip provided by the prior art.

As an example, the fast charge protocol chip 230 may include an internal power supply module (for example, a low dropout linear regulator (LDO)) 2301, an input voltage detection module 2302, a fault detection circuit 2303 and a gate driver. 2304, Schottky diode Dsb, etc. The chip 230 may include an input pin VIN, a power supply pin AVDD, and a gate drive pin GATE.

As shown in Figure 3, LDO 2301 can generate an internal low-voltage supply voltage AVDD based on the input voltage VIN for powering the internal circuit of the chip, and output it to the AVDD pin through the Schottky diode Dsb for external use of the chip. Capacitor Cavdd performs voltage stabilization and filtering.

In the example shown in Figure 3, when the system is in normal working condition and no fault is detected, the power MOS field effect transistor MN_ext located outside the chip remains in the on state; when the system is working, if VBUS occurs In the case of a short circuit to ground, the VIN voltage will also drop rapidly as VBUS drops. However, due to the reverse blocking of the Schottky diode Dsb, the internal supply voltage AVDD will not drop as the voltage VIN drops. The input voltage detection module 2302 is powered by the internal power supply voltage AVDD due to rapid power outage. The low level of VIN can be detected normally to output a vin_low signal at a high level (for example, "1"), and then the power MOS field effect transistor MN_ext is turned off through the subsequent gate driver 2304.

It can be seen that the fast charging protocol chip provided in Figure 3 adds Schottky diode Dsb to utilize its reverse blocking, which can well block the discharge path from the internal supply voltage AVDD to the input voltage VIN when a VBUS short circuit occurs. , thereby reducing the requirements for the power MOS field effect transistor MN_ext turn-off time, so that the chip can be fully controlled to protect the entire system.

In summary, the circuit shown in Figure 3 can achieve short-circuit protection, and the circuit is relatively simple and reliable. However, the above circuit has several shortcomings: first, the Schottky diodes provided by many processes usually require the use of additional masks, which increases the cost; second, with the complexity of fast charging protocol chips , the minimum output voltage setting of VIN will be closer and closer to the AVDD reset voltage threshold, and the clock frequency of the chip will be further increased, which will increase the power consumption of the chip. In order to make the voltage drop on the Schottky diode meet the above strict requirements , causing the area of the Schottky diode to increase, causing the area of the wafer to increase, which in turn leads to an increase in the cost of the wafer.

In order to solve the existing technical problems, embodiments of the present invention provide a new short-circuit protection implementation method for fast charging protocol chips. The following first introduces the fast charging protocol chip provided by the embodiment of the present invention.

It should be noted that for ease of introduction, the following embodiments are introduced by taking a fast charging protocol chip suitable for fly-back architecture as an example. It can be understood that it is only provided as an example and should not be interpreted as Restrictive.

As an example, embodiments of the present invention provide a more effective implementation of short-circuit protection for fast charging protocol chips. Specifically, as shown in FIG. 4 , FIG. 4 shows a schematic diagram of a short-circuit protection implementation method for a fast charging protocol chip provided by an embodiment of the present invention.

As an example, the fast charge protocol chip 430 may include an internal power supply module (eg, LDO) 4301, an input voltage detection module 4302, a fault detection circuit 4303, a gate driver 4304, a slope detection module 4305, and a power MOS field. Effective transistor MP0, etc. The chip 430 may include an input pin VIN, a power supply pin AVDD, and a gate drive pin GATE.

The difference between the wafer shown in Figure 4 and the wafer shown in Figure 3 mainly lies in that by utilizing the controlled power MOS field effect transistor MP0 (for example, P-type metal-oxide semiconductor (Metal-Oxide) shown in Figure 4 -Semiconductor, PMOS) to replace the Schottky diode Dsb in Figure 3 to achieve short circuit protection, where the power MOS field effect transistor MP0 is connected between the internal power supply module 4301 and the internal power supply pin AVDD, And a new slope detection module 4305 is added to use the slope detection module 4305 to detect the change slope of the chip's input voltage, and control the conduction and switching of the power MOS field effect transistor MP0 based on the change slope of the chip's input voltage. Shut down.

It can be understood that if the gate source drive voltage (VSG) of the power MOS field effect transistor MP0 is high enough, the same chip area can be used to achieve a smaller voltage drop than the Schottky diode Dsb.

As an example, the slope detection module 4305 may be configured to control the power MOS field effect transistor MP0 from on to off when the negative slope of the input voltage of the fast charge protocol chip is greater than the negative slope threshold, and during fast charging When the positive slope of the input voltage of the agreed chip is greater than the positive slope threshold, the power MOS field effect transistor MP0 is controlled to change from off to on.

As an example, the slope detection module 4305 may include a voltage dividing unit (including resistors Rup and Rdw), a low-pass filter unit (including a resistor Rlp and a capacitor Clp), a shift unit (including, for example, two same-sized transistors MP1 and Transistor MP2, resistor R1, resistor R2, switch SW1, switch SW2 and current source I0), first comparator comp1, second comparator comp2 and logic unit (including AND gate and inverter), etc.

Wherein, the voltage dividing unit can be configured to divide the input voltage VIN of the fast charge protocol chip to generate a divided voltage vin_div; the filtering unit can be configured to filter the divided voltage vin_div to generate a filtered voltage vin_div_lpf; shift The unit may be configured to generate a first shift level vin_div_lpf_shift and a second shift level vin_div_shift by performing level shifts on the filtered voltage vin_div_lpf and the divided voltage vin_div respectively; the first comparator comp1 may be configured to generate a first comparison result slope_det by comparing the first shift level vin_div_lpf_shift and the second shift level vin_div_shift; the second comparator comp2 may be configured to generate a first comparison result slope_det by comparing the divided voltage vin_div and the reference voltage. vref_scp is compared to generate a second comparison result slope_en; and the logic unit may be configured to generate a switch for controlling the on and off of the power MOS field effect transistor MP0 based on the first comparison result slope_det and the second comparison result slope_en. Control signal sw_ctl.

Similar to the fast charging protocol chip shown in Figure 3, the fast charging protocol chip shown in Figure 4 also includes an internal power supply module 4301, which can be used to generate a low-voltage supply voltage AVDD; an input voltage detection circuit 4302 powered by the internal supply voltage AVDD , can be used to turn off MN_ext located outside the chip when low voltage of VIN is detected.

As an example, the shift unit may include: a first shift branch, which may include a first PMOS transistor MP1, a first switch sw1, and a first resistor R1, and may be configured to operate when the first switch sw1 is in an on state and in an off state. When in the off state, perform different level shifts on the filter voltage vin_div_lpf respectively; and the second shift branch, which may include a second PMOS transistor MP2, a second switch sw2 and a second resistor R2, may be configured to operate in the second When the switch sw2 is in the on state and in the off state, the divided voltage vin_div is shifted to different levels respectively; wherein, the on and off of the first switch sw1 and the second switch sw2 can be respectively controlled by the inverted switch. The control signal sw_ctli and the switch control signal sw_ctl are used to control.

As an example, the first shift branch may also include a first current source I0 and a first transistor MP1, wherein the first current source I0 may be connected to the internal power supply pin AVDD of the fast charge protocol chip and the first resistor R1 In between, the source and drain of the first transistor MP1 can be connected to the first resistor R1 and the reference ground respectively, and the gate of the first transistor MP1 can receive the filtered voltage vin_pin_lpf; and, the second shift branch can also It includes a second current source I0 and a second transistor MP2, wherein the second current source I0 can be connected between the internal power supply pin AVDD of the fast charge protocol chip and the second resistor R2, and the source of the second transistor MP2 and The drain electrode may be connected to the second resistor R2 and the reference ground respectively, and the gate electrode of the second transistor MP2 may receive the divided voltage vin_div.

Specifically, after the input voltage VIN is divided by the voltage dividing unit, a divided voltage vin_div is generated. After the divided voltage is filtered by a low-pass filtering unit, a filtered voltage vin_div_lpf is generated. The divided voltage vin_div and the filtered voltage vin_div_lpf are respectively The two input terminals of the subsequent shift units, namely the gates of MP2 and MP1, are provided to generate level-shifted voltages vin_div_shift and vin_div_lpf_shift respectively. Next, the voltages vin_div_shift and vin_div_lpf_shift are provided to the two gates of the comparator comp1 respectively. There are two input terminals (for example, a negative phase input terminal and a positive phase input terminal), so that the comparator comp1 can compare the two to generate the first comparison result slope_det, and at the same time, the divided voltage vin_div can be provided to an input of the comparator comp2 terminal (for example, the negative input terminal), the other input terminal (for example, the positive input terminal) of the comparator comp2 can receive the reference voltage vref_scp, so that the comparator comp2 can compare the two to generate the second comparison signal slope_en , after the first comparison signal slope_det and the second comparison signal slope_en undergo a logical AND operation through the "AND" gate, the switch control signal sw_ctl can be generated. The switch control signal sw_ctl can be used to control the on and off of the power MOS field effect transistor MP0. off, the switch control signal sw_ctl can also be inverted through an inverter to generate an inverted switch control signal sw_ctli. The signals sw_ctl and sw_ctli can be provided to the switches sw2 and sw1 in the shift unit respectively to control these two The switch is turned on and off, which is used to generate the positive slope threshold, the negative slope threshold, the necessary hysteresis voltage, etc. (this will be described in detail below).

Among them, when the signal sw_ctl is at the high level, the switch sw2 is in the on state; when the signal sw_ctl is at the low level, the switch sw2 is in the off state; when the signal sw_ctli is at the high level, the switch sw1 is in the on state; when the signal sw_ctli is at the low level, the switch sw1 is in shutdown state.

In the embodiment shown in Figure 4, when a VBUS short circuit occurs, the chip can detect that the negative slope of VIN is greater than the negative slope threshold, and then disconnects the power MOS field effect transistor MP0 to prevent the internal supply voltage AVDD from powering down. This allows the voltage detection circuit to work normally, that is, to detect the low voltage of VIN; then, when the VIN voltage recovers, the chip can detect that the positive slope of VIN is greater than the positive slope threshold, and then turns on the power MOS field effect transistor. MP0.

The following is a detailed introduction to the working principle of the fast charging protocol chip. For example, the fast charging protocol chip can include three working states: normal working state, short circuit protection state and voltage recovery state. The following mainly introduces the above three states respectively.

As an example, for the normal working state, when the power MOS field effect transistor MP0 is in the on state, the first switch sw1 is in the on state, the second switch sw2 is in the off state, and the divided voltage vin_div is equal to the filter voltage vin_div_lpf, the The second shift level vin_div_shift is greater than the first shift level vin_div_lpf_shift, the first comparison result slope_det is at a low level, and the second comparison result slope_en is related to the divided voltage vin_div and the reference voltage vref_scp.

Specifically, when the fast charging system is in normal working condition, the transistor MN_ext located outside the chip is in a conductive state, the input voltage VIN of the chip supplies power to VBUS through the transistor MN_ext, and the switching control signal sw_ctl of the power MOS field effect transistor MP0 = "0", that is, MP0 is in the on state, and the inverted switch control signal sw_ctli = "1". The switch control signals sw_ctl and sw_ctli are respectively used to control the switch sw2 to be in the off state and the switch sw1 to be in the on state. When the input voltage When VIN is stable, the divided voltage vin_div and the filtered voltage vin_div_lpf are equal. Since the first resistor R1 in the shift unit is short-circuited by the first switch sw1, and since the second switch sw2 is turned off, there is I0*R2 on the second resistor R2. voltage drop, so the voltage vin_div_shift generated by the divided voltage vin_div and the filtered voltage vin_div_lpf through the shift unit is higher than the voltage vin_div_lpf_shift, so that the comparator comp1 compares the two and outputs the comparison result slope_det="0", and at the same time divides the voltage vin_div voltage It is compared with the reference voltage vref_scp through the comparator comp2. The purpose is to allow the slope detection module 4305 to only work when the input voltage VIN is lower than a preset value, thereby avoiding false triggering when the input voltage VIN is output normally. Due to this slope detection, the divided voltage vin_div is higher than the reference voltage vref_scp during normal operation, causing the comparator comp2 to output the comparison result slope_en="0".

Moreover, when the fast charging system is in normal working condition, the output signal vin_low of the input voltage detection module 4302 = “0”, if the fault detection circuit 4303 does not detect other Fault, outputting a detection result indicating that there is no fault, the gate driver 4304 can maintain the transistor MN_ext in a conductive state based on the output signal vin_low from the input voltage detection module 4302 and the detection result from the fault detection circuit 4303.

As an example, for the VBUS short-circuit state, when the divided voltage vin_div is smaller than the filtered voltage vin_div_lpf by the first preset threshold, the second shift level vin_div_shift is smaller than the first shift level vin_div_lpf_shift, and the first comparison result slope_det is at a high level, And when the second comparison result slope_en is at a high level, the switch control signal sw_ctl is at a high level, and the power MOS field effect transistor MP0 is in an off state.

Specifically, when VBUS is short-circuited to ground, the input voltage VIN will drop rapidly following the drop of VBUS, causing the input voltage VIN to have a negative slope. At this time, the divided voltage vin_div divided by the voltage-dividing resistors Rup and Rdw is larger than its value. The vin_div_lpf after low-pass filtering drops faster. If the negative slope of the input voltage VIN drop is large enough, then there must be a moment when the divided voltage vin_div can be lower than the filtered voltage vin_div_lpf by the voltage drop of I0*R2, and then The second shift level vin_div_shift voltage can be made lower than the first shift level vin_div_lpf_shift, and the output signal slope_det of the first comparator comp1 changes from "0" to "1". At this time, if the input voltage VIN is low enough such that The divided voltage vin_div is lower than the reference voltage vref_scp, then the output signal slope_en of the second comparator comp2 also changes from "0" to "1", and the output signals slope_det and slope_en from the comparator comp1 and the comparator comp2 pass through the "AND" gate Perform logical AND operation, and the generated switch control signal sw_ctl changes from "0" to "1". When the switch control signal sw_ctl is at a high level, the power MOS field effect transistor MP0 is turned off. At the same time, the switch control at a high level is The signal sw_ctl and the inverted switch control signal sw_ctli at a low level can be used to control the second switch sw2 to turn on and the first switch sw1 to turn off respectively, so that the first shift level vin_div_lpf_shift is instantly higher than the second shift level vin_div_shift The voltage drop of high I0*(R1+R2) introduces hysteresis, which can improve the anti-interference ability of the slope detection module 4305 near the detection threshold. Due to this slope detection method, the detection can be completed quickly when the input voltage VIN is high, and the discharge path from the internal supply voltage AVDD to the input voltage VIN is blocked when a VBUS short circuit occurs. Therefore, the input voltage detection module 4302 can complete VIN low voltage detection when the internal power supply voltage AVDD is normal, so that the output signal vin_low of the input voltage detection module 4302 changes from "0" to "1", and the gate driver 4304 can have enough time to turn off. When the power crystal MN_ext is turned off, the input voltage VIN no longer decreases as VBUS decreases.

As an example, the voltage recovery state can be divided into the following two situations: One situation is that during the recovery process of the input voltage VIN, the divided voltage vin_div is larger than the filtered voltage vin_div_lpf by the second preset threshold, so that the second shift bit When the quasi vin_div_shift is greater than the first shift level vin_div_lpf_shift, so that the first comparison result slope_det is at a low level, the switch control signal sw_ctl is at a low level, and the power MOS field effect transistor MP0 is in the on state; another situation is that when the input voltage VIN During the recovery process, the divided voltage vin_div cannot be greater than the filtered voltage vin_div_lpf by the second preset threshold, so that the second shift level vin_div_shift will not be greater than the first shift level vin_div_lpf_shift, so that the first comparison result slope_det is always at a high level. , but when the input voltage VIN rises to such a level that the divided voltage vin_div is greater than the reference voltage vref_scp, so that the output signal slope_en of the comparator comp2 is at a low level, the power MOS field effect transistor MP0 can also be restored to the on state. For those skilled in the art, the second situation is relatively easy to understand. For convenience of description, only the control principle of the first situation is described in detail below.

Specifically, since the VIN short-circuit protection is detected and the external transistor MN_ext is disconnected, the energy provided by the primary-side PWM controller will cause the input voltage VIN to rise. At this time, the divided voltage is divided by the voltage-dividing resistors Rup and Rdw. vin_div rises faster than its filtered voltage vin_div_lpf after low-pass filtering. If the positive slope of the rise of the input voltage VIN is large enough, there must be a moment when the divided voltage vin_div is higher than the filtered voltage vin_div_lpf by a voltage drop of I0*R1 , and then the second shift level vin_div_shift is higher than the first shift level vin_div_lpf_shift, and the output signal slope_det of the comparator comp1 changes from "1" to "0". At this time, no matter what the output signal slope_en of the comparator comp2 is value, the "AND" gate will output the switch control signal sw_ctl at a low level, so that the switch control signal sw_ctl controls the power MOS field effect transistor MP0 to turn on, and the input voltage VIN once again supplies the internal power supply voltage AVDD Power supply. At the same time, the switch control signal sw_ctl at a low level and the inverted switch control signal sw_ctli at a high level can respectively control the second switch sw2 to turn off and the first switch sw1 to turn on, so that the first shift level vin_div_lpf_shift is instantaneously higher than the second switch sw2. The second shift level vin_div_shift lowers the voltage drop of I0*(R1+R2), which introduces hysteresis, thus improving the anti-interference ability of the slope detection module 4305 near the detection threshold. Next, if the input voltage detection module 4302 detects that the input voltage VIN returns to above the normal value, the output signal vin_low of the input voltage detection module 4302 changes from "1" to "0", and the gate driver 4304 is configured based on the output The signal vin_low is used to turn on the external transistor MN_ext again, so that all circuits return to the initial state of normal operation and prepare for the next short circuit detection.

Furthermore, it is necessary to further determine which circuit parameters the negative slope threshold during short circuit protection and the positive slope threshold during input voltage recovery depend on, so that the circuit designer can select appropriate circuit parameters to obtain an appropriate negative slope threshold when designing the circuit. and positive slope threshold. Specifically, the following formula is derived based on Kirchhoff's voltage law, as shown in FIG. 5 , which shows a schematic structural diagram of the sampling loop for the input voltage in the embodiment shown in FIG. 4 .

VR(t)+Vlpf(t)=Vdiv(t).............(1)

其中，Vin(t)為輸入電壓VIN隨時間變化的函數，當發生VBUS短路時，Vin(t)可以近似表示為如下所示的線性函數：Vin(t)=V0-k．t...........................(3)在公式(3)中，V0為VBUS短路發生時VIN的初始電壓，k為VBUS短路發生時VIN的下降斜率，將公式(3)代入公式(2)中，可得：

Formula (1) can be further refined to obtain formula (2):

Among them, Vin ( t ) is a function of the input voltage VIN changing with time. When a VBUS short circuit occurs, Vin ( t ) can be approximately expressed as a linear function as shown below: Vin ( t )=V0-k. t........................(3) In formula (3), V0 is the initial voltage of VIN when VBUS short circuit occurs, k is the falling slope of VIN when a VBUS short circuit occurs. Substituting formula (3) into formula (2), we can get:

當輸出短路發生時，圖4在檢測點處滿足如下條件：Vlpf(t)-Vdiv(t)=I0．R2..................(6)將公式(3)和公式(5)代入公式(6)中，可得：

在公式(7)中，當滿足t>>Rlp．Clp時，可以得到短路檢測的負斜率閾值與電路參數之間的對應關係，如公式(8)所示：

另外，從公式(7)中也可以得到不同的VIN負斜率下，比較器comp1的檢測時間與VIN斜率k之間的對應關係，如公式(9)所示：

In formula (4), Rlp and Clp are the resistance value of the resistor and the capacitance value of the capacitor in the low-pass filter shown in Figure 4. Rdw and Rup are the voltage dividing resistors of VIN. By solving one part of formula (4) First-order differential equation, the function of Vlpf ( t ) can be obtained:

When an output short circuit occurs, Figure 4 satisfies the following conditions at the detection point: Vlpf(t)-Vdiv(t)=I0. R2.............(6) Substituting formula (3) and formula (5) into formula (6), we can get:

In formula (7), when t>>Rlp is satisfied. Clp, the corresponding relationship between the negative slope threshold of short circuit detection and the circuit parameters can be obtained, as shown in formula (8):

In addition, the corresponding relationship between the detection time of comparator comp1 and the VIN slope k under different negative slopes of VIN can also be obtained from formula (7), as shown in formula (9):

It can be seen from formula (9) that when an output short circuit occurs, the faster the input voltage VIN drops and the larger k is, the shorter the detection time of comparator comp1 is.

In the same way, when the input voltage VIN is recovering, the corresponding relationship between the positive slope threshold and the circuit parameters can be obtained, as shown in formula (10):

k _thn and k _{th p} in formulas (8) and (10) are respectively the corresponding VIN negative slope threshold and positive slope threshold when short-circuit protection occurs and the input voltage recovers from the actual test of the system. According to formula (8) and formula ( 10), the parameters of the circuit components can be reasonably selected to effectively realize the short-circuit protection of the output VBUS.

In summary, the fast charging protocol chip and the fast charging system including the chip provided by embodiments of the present invention can reduce the cost of the chip and implement a reliable and effective output short-circuit protection solution.

Specifically, compared with the traditional short-circuit protection method using reverse blocking of Schottky diodes, the fast charging protocol chip and its system provided by embodiments of the present invention can achieve the following advantages: the cost of the chip can be saved. ;Can convert the slope of the input voltage into instant voltage Comparing the voltage difference provides a fast slope detection method, which can effectively prevent the chip's internal power supply voltage from losing power, that is, it will not cause the chip to run out of control; the negative slope threshold when an output short circuit occurs and the positive slope when VIN recovers can be set separately. The slope threshold improves flexibility; whether it is near the detection point of the negative slope threshold or the positive slope threshold, hysteresis is introduced to improve the anti-interference ability; the judgment of the absolute value voltage of VIN is added as a condition for enabling slope detection , that is, only when the input voltage VIN is lower than the preset threshold and higher than the safe operating voltage, it is allowed to disconnect the power MOS field effect transistor MP0 through the slope detection module during negative slope detection, which can be avoided Under the typical output of VIN, when performing output dynamic or VIN step-down operation, the short-circuit protection is accidentally triggered; in the short-circuit protection state, the slope detection module can be used to disconnect the internal power supply module LDO to the internal power supply voltage AVDD. Even if the power MOS field effect transistor MP0 is turned off by mistake for some reason during normal operation, the output signal of the internal power supply module LDO can still pass through the parasitic diode D0 of MP0. Powers AVDD (only the short-term voltage drop will increase), and the parasitic diode D0 also has a reverse blocking function similar to the traditional Schottky diode Dsb; in addition, the output of the slope detection module does not Will be used to directly turn off the external transistor MN_ext. Therefore, it has better anti-interference ability against external impacts such as system electrostatic discharge (ESD).

Embodiments of the present invention also provide a short-circuit protection solution for a fast charging system, including the fast charging protocol chip provided by the embodiment of the present invention as described above. The details of the chip are described in detail above. Therefore, for convenience, Description will not be repeated here.

In summary, embodiments of the present invention provide a short-circuit protection scheme that can be applied to flyback architecture AC/DC secondary side fast charging chips. In applications that require higher reliability of fast charging systems, embodiments of the present invention provide The fast charging protocol chip and its system can perform output short circuit detection very well, thus effectively protecting the entire fast charging system.

It is to be understood that this invention is not limited to the specific arrangements and processes described above and illustrated in the drawings. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and illustrated. Those skilled in the art can After appreciating the spirit of the present invention, various changes, modifications and additions may be made, or the order between steps may be changed.

The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), appropriate firmware, a plug-in program, a function card, or the like. When implemented in software, elements of the invention are programs or program code fragments used to perform the required tasks. The program or program code fragments may be stored in a machine-readable medium, or transmitted over a transmission medium or communications link via a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links Road, wait. Code snippets can be downloaded via computer networks such as the Internet, intranets, etc.

It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps. That is to say, the steps may be performed in the order mentioned in the embodiments, or may be different from the order in the embodiments, or several steps may be performed simultaneously.

The above are only specific implementation modes of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can be implemented with reference to the aforementioned methods. The corresponding process in the example will not be described again here. It should be understood that the protection scope of the present invention is not limited thereto. Any person familiar with the technical field can easily think of various equivalent modifications or substitutions within the technical scope disclosed in the present invention. These modifications or substitutions should be covered by within the protection scope of the present invention.

430:Chip

4301: Internal power supply module

4302: Input voltage detection module

4303:Fault detection circuit

4304: Gate driver

4305: Slope detection module

AVDD: internal supply voltage

Cavdd: chip external capacitance

Clp: on-chip filter capacitor

comp1: first comparator

comp2: second comparator

D0: Parasitic diode

GATE: Gate

I0: first current source/second current source

LDO: Low Dropout Linear Regulator

MN_ext: Transistor

MP0, MP1, MP2: transistor

Plp, R1, R2: Resistor

PWM: primary side pulse width modulation

slope_det: first comparison result

slope_en: second comparison result

sw_ctl: switch control signal

SW1, SW2: switch

VBUS: output voltage

VIN: input voltage

vin_div: divided voltage

vin_div_lpf: filter voltage

vin_div_lpf_shift: first shift level

vin_div_shift: second shift level

vin_low: input voltage detection signal

vref_scp: reference voltage

Claims (12)

A fast charging protocol chip, characterized by comprising: an internal power supply module configured to generate an internal power supply voltage for powering the internal circuit of the fast charging protocol chip based on the input voltage of the fast charging protocol chip; a power MOS field effect transistor connected between the internal power supply module and the internal power supply pin of the fast charge protocol chip; and a slope detection module configured to detect the input voltage of the fast charge protocol chip The changing slope of the input voltage of the fast charging protocol chip is used to control the on and off of the power MOS field effect transistor. The slope detection module includes: a voltage dividing unit configured as By dividing the input voltage of the fast charging protocol chip, a divided voltage is generated; the filtering unit is configured to filter the divided voltage to generate a filtered voltage; the shift unit is configured to generate a filtered voltage by respectively The filtered voltage and the divided voltage perform level shifts to generate a first shift level and a second shift level; a first comparator is configured to compare the first shift level and The second shift level is compared to generate a first comparison result; a second comparator is configured to generate a second comparison result by comparing the divided voltage and the reference voltage; and a logic unit is configured Generate a switch control signal for controlling on and off of the power MOS field effect transistor based on the first comparison result and the second comparison result. The fast charge protocol chip according to claim 1, wherein the slope detection module is further configured to: when the negative slope of the input voltage of the fast charge protocol chip is greater than a negative slope threshold, control the power MOS The field effect transistor changes from on to off. The fast charge protocol chip according to claim 1, wherein the slope detection module is further configured to: when the positive slope of the input voltage of the fast charge protocol chip is greater than a positive slope threshold, control the The power MOS field effect transistor changes from off to on. The fast charging protocol chip according to claim 1, wherein the shift unit includes: a first shift branch, including a first switch and a first resistor, configured to operate when the first switch is in a conductive state and When in the off state, perform different level shifts on the filtered voltage respectively; and the second shift branch, including the second switch and the second resistor, is configured to perform different level shifts when the second switch is in the on state and When in the off state, the divided voltages are respectively shifted to different levels; wherein, the turn-on and turn-off of the first switch and the second switch are controlled by the power MOS field effect transistor. Switch control signal control. The fast charge protocol chip according to claim 4, wherein the first shift branch further includes a first current source and a first transistor, wherein the first current source is connected to the fast charge protocol chip. between the internal power supply pin and the first resistor, the source and drain of the first transistor are connected to the first resistor and the reference ground respectively, and the gate of the first transistor receives the filter voltage; and, the second shift branch also includes a second current source and a second transistor, wherein the second current source is connected between the internal power supply pin of the fast charge protocol chip and the third Between the two resistors, the source and drain of the second transistor are connected to the second resistor and the reference ground respectively, and the gate of the second transistor receives the divided voltage. The fast charging protocol chip according to claim 5, wherein when the switch control signal of the power MOS field effect transistor is at a high level, the first switch is in an off state and the second switch is in an on state. ; When the switch control signal of the power MOS field effect transistor is at a low level, the first switch is in an on state, and the second switch is in an off state. The fast charging protocol chip as described in claim 1, wherein when the divided voltage When the first preset threshold is smaller than the filter voltage, the second shift level is smaller than the first shift level, the first comparison result is at a high level, and the second comparison result is at a high level , the switching control signal of the power MOS field effect transistor is at a high level, and the power MOS field effect transistor is in an off state. The fast charge protocol chip according to claim 1, wherein when the divided voltage is greater than the filter voltage by a second preset threshold, the second shift level is greater than the first shift level, And when the first comparison result is at a low level, the switching control signal of the power MOS field effect transistor is at a low level, and the power MOS field effect transistor is in a conductive state. The fast charging protocol chip according to claim 4, wherein when the power MOS field effect transistor is in a conductive state, the first switch is in a conductive state, the second switch is in an off state, and the branch When the voltage is equal to the filtered voltage, the second shift level is greater than the first shift level, the first comparison result is at a low level, and the second comparison result is equal to the sum of the divided voltage and related to the reference voltage. The fast charging protocol chip as described in claim 5, wherein the negative slope threshold is determined according to the following formula:

Wherein, k _thn is the negative slope threshold, I 0 is the current value provided by the first current source or the second current source, R 2 is the resistance value of the second resistor, Rlp and Clp are respectively the The resistance value of the resistor and the capacitance value of the capacitor included in the filter module, Rup and Rdw are respectively the resistance values of the resistors included in the voltage dividing module and connected to the input voltage and the reference ground respectively. The fast charging protocol chip as described in claim 4, wherein the positive slope threshold is determined according to the following formula:

Wherein, k _thp is the positive slope threshold, I 0 is the current value provided by the first current source or the second current source, R 1 is the resistance value of the first resistor, Rlp and Clp are respectively The resistance value of the resistor and the capacitance value of the capacitor included in the filter module, Rup and Rdw are respectively the resistance values of the resistors included in the voltage dividing module and connected to the input voltage and the reference ground respectively. A fast charging protocol system, characterized by including the fast charging protocol chip as described in any one of claims 1 to 11.

Images