KR100476393B1 - Semiconductor memory device for reducing package test time - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a package and test technology for a semiconductor memory device, and an object thereof is to provide a semiconductor memory device capable of reducing package test time and package cost. The present invention can reduce package cost and package test time by implementing the remaining product family as an internal option in addition to the product family determined by wire bonding. To this end, the test mode generator generates a test mode bandwidth control signal, and in response to the signal, implements a switching circuit that cuts off the path of the normal mode package option signal in the test mode and enables the path of the test mode package option signal. .

Description

Semiconductor memory device for reducing package test time

TECHNICAL FIELD The present invention relates to semiconductor memories, and more particularly, to packaging and testing techniques for semiconductor memory devices.

The main issue in the recent semiconductor memory field is changing from integration to operating speed. As a result, high-speed synchronous memories such as double data rate syncghronous DRAM (DDR SDRAM) and RAMBUS DRAM are emerging as a new topic in the semiconductor memory field.

Synchronous memory refers to a memory that operates in synchronization with an external system clock. Among the DRAMs, SDRAM is the mainstream of the mass production memory market. The SDRAM performs one data access every clock by synchronizing input / output operations to the rising edge of the clock. In contrast, a high-speed synchronous memory such as DDR SDRAM has a feature in which input / output operations are synchronized not only on the rising edge of the clock but also on the falling edge, so that two data accesses are possible every clock.

Currently produced DRAM products have a bandwidth of X4 / X8 / X16. That is, the bandwidth of the product is determined according to the request of the orderer, and each has a unique pin arrangement and wiring according to the bandwidth.

Figure 1 shows the pinout of a typical X4 and X16 SDRAM (54 pins).

Referring to FIG. 1, in the case of the X16 SDRAM, the data input / output pins DQ0 to DQ15, the address pins A0 to A12, the bank address pins BA0 and BA1, and the power supply pins VDD, VSS, VDDQ, VSSQ), data mask pins (LDQM, UDQM), command pins (/ WE, / CAS, / RAS, / CS), clock pins (CK), clock enable pins (CKE), and the like. Each of these is wire bonded with a pad PAD in a die through a lead frame. In the case of X16 SDRAM, all 16 DQ pins are used, and only one of the 54 pins remains unconnected (NC).

On the other hand, since X4 SDRAM uses only four DQ pins (DQ0, DQ1, DQ2, and DQ3), 12 DQ pins that are wire-bonded in X16 SDRAM remain unconnected (NC), and data mask pins. Among the (LDQM and UDQM), the lower data mask pin LDQM remains in the non-connected state (NC), and thus 14 pins out of 54 pins remain in the non-connected state (NC).

For reference, since the data mask signal is controlled in units of bytes, one data mask pin DQM is used in X4 or X8, and two data mask pins LDQM and UDQM are used in X16.

Figure 2 shows the pinout of a typical X4, X8 and X16 DDR SDRAM (66 pins).

Referring to FIG. 2, in DDR SDRAM, data strobe pins (LDQS, UDQS, and DQS), reference voltage pins (VREF), and sub clock pins (/ CK), which are not used in the SDRAM, are larger than the SDRAM. No different. In other words, 16 DQ pins are used for X16 DDR SDRAM, eight for X8 DDR SDRAM, and four DQ pins for X4 DDR SDRAM.

For reference, two data mask pins (LDM and UDM) are bonded and used in X16 DDR SDRAM, but the lower data mask pin (LDM) is not used in X4 and X8 DDR SDRAM and is in an unconnected state (NC). Only one data mask pin DM is used. In addition, two data strobe pins (LDQS and UDQS) are bonded and used in the X16 DDR SDRAM, but the lower strobe pin (LDQS) is not used in the X4 and X8 DDR SDRAM, and the data is disconnected (NC). Only the strobe pin (DQS) is used.

As described above, as shown in FIGS. 1 and 2, all semiconductor memory products have unique pinouts and wirings according to their bandwidths.

On the other hand, as the integration degree of semiconductor memory is rapidly increasing, tens of millions of cells are integrated in one memory chip. As the number of memory cells increases, it takes a long time to test whether they are normal or defective. In these package tests, it is important to consider the accuracy of the test results as well as how quickly the test is performed.

In order to meet the demands in terms of such test time, a parallel test capable of multi-bit access at the same time has been proposed. However, such a parallel test method inevitably degrades the screen ability due to compressing and testing data, and has a disadvantage in that it does not properly reflect relativity due to data path difference or power noise.

Therefore, in order to understand the product characteristics more accurately, it is inevitable to use a non-compression method that takes a long time to test. Hereinafter, a description will be given on the premise of an uncompressed test method.

3 is a wire bonding diagram for each package option according to the prior art.

Referring to FIG. 3, in the case of the X4 product 100, the package option pad PAD X4 101 is wire-bonded with the VDD pin and the other package option pad PAD X8 102 with the VSS pin. The pads that are dark in the figure are wire bonded with the package leads, and the pads that are bright are in the floating state. Meanwhile, in the case of the X8 product 110, the package option pad PAD X4 111 is wire-bonded with the VSS pin and the other package option pad PAD X8 112 is VDD pin. In addition, for the X16 product 120, the package option pads PAD X4 121 and PAD X8 122 are wire bonded with the VSS pins, respectively.

4 is a circuit diagram of a package option signal generation block according to the prior art.

Referring to FIG. 4, VDD or VSS applied to the package option pads PAD X4 and PAD X8 are buffered through the buffer units 130 and 140 formed of two inverters and output as the package option signals sX4 and sX8.

Table 1 below is a package option table showing the operating bandwidth according to the wire bonding.

X4 X8 X16 PAD X4 VDD VSS VSS PAD X8 VSS VDD VSS sX4 H L L sX8 L H L

Referring to Table 1, when the package option signals sX4 and sX8 are logic level high (H) and low (L), respectively, the package operates as X4, and the package option signals sX4 and sX8 are logic level low (L), respectively. And if the high (H), the corresponding package is operated by X8, and if the package option signals sX4 and sX8 are both logic level low (L), the corresponding package is operated by X16.

On the other hand, when only the test of the package option determined by wire bonding to the package option pad as described above is difficult to detect a defect due to the change in the bandwidth, it is not only tested for the package option but also the remaining package options. It is often done. In particular, for products wired in X4 or X8 packages, it is difficult to test characteristics for packages with higher bandwidths because some of the DQ pins are disconnected (NC), but for products wired in X16 packages. It is possible to sufficiently test the characteristics of the bandwidths of X8 and X4.

Suppose you are testing the characteristics of a wire-bonded product in an X16 package. To test the X4 and X8 package characteristics, you must modify the wiring of the package option pad. That is, after performing the X16 package characteristic test, the wiring of the package option pad is modified to correspond to the X8 package, the X8 package characteristic test is performed, and then the wiring is modified again to perform the X4 package characteristic test. In this case, since the wiring modification process corresponding to each package option is required, the package cost and test time increase.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of reducing package test time and package cost.

According to an aspect of the present invention for achieving the above technical problem, the first and second package option pad; First and second buffer units configured to generate first and second default package option signals by buffering an external signal applied according to a bonding combination of the first and second package option pads; A test mode generator configured to generate first and second test mode bandwidth control signals for providing first and second test mode package options except for a default package option in a test mode; A first switching unit for blocking an output path of the default package option signal in response to the first and second test mode bandwidth control signals in a normal mode; A second switching unit for enabling output paths of first and second internal option signals corresponding to the first test mode package option in response to the first test mode bandwidth control signal; And a third switching unit for enabling output paths of third and fourth internal option signals corresponding to the second test mode package option in response to the second test mode bandwidth control signal in a test mode. An element is provided.

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The present invention can reduce package cost and package test time by implementing the remaining product family as an internal option in addition to the product family determined by wire bonding. To this end, the test mode generator generates a test mode bandwidth control signal, and in response to the signal, implements a switching circuit that cuts off the path of the normal mode package option signal in the test mode and enables the path of the test mode package option signal. .

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

5 is an exemplary view of a wire bonding structure for each package option applied to the present invention.

Referring to FIG. 5, in the case of the X4 product 200, the package option pad PAD X4 201 is wire bonded to the VDD pin and the other package option pad PAD X8 202 is connected to the VSS pin. Meanwhile, in the case of the X8 product 210, the package option pad PAD X4 211 is wire bonded to the VSS pin, and the other package option pad PAD X8 212 is wired to the VDD pin. In addition, for the X16 product 220, the package option pads PAD X4 221 and PAD X8 222 are wire bonded with the VSS pins, respectively.

That is, the configuration and application signal of the package option pad in the wire bonding structure applied to the present invention is not different from the prior art (see FIG. 3). However, in the present invention, whether the X4 product 200 or the X8 product 210 is the same, the wire bonding structure of the X16 product 220 having the maximum bandwidth and the DQ pin is the same. That is, whatever the package option, all DQ pins are wire bonded.

6 is a block diagram of a package option signal generation circuit according to an embodiment of the present invention.

Referring to FIG. 6, the package option signal generation circuit according to the present embodiment includes at least one package option pad and includes a normal mode for generating a default package option signal for determining an operation bandwidth of a device according to a bonding state thereof. A test mode package option providing unit 60 for internally providing a package option providing unit 60 and a remaining package option which is operated in a test mode and implemented according to the bonding state of the package option pad, and a test mode bandwidth And a package option selector 64 for selectively outputting the output signal of the normal mode package option provider 60 or the test mode package option provider 62 as a package option signal in response to the control signal test_mode_X. .

FIG. 7 is a detailed circuit diagram of the package option signal generation circuit of FIG. 6 and illustrates a case of bonding to an X16 product by default.

Referring to FIG. 7, the normal mode package option providing unit 60 includes a package option pad PAD X4 70 wire-bonded with a VSS pin, and a package option pad PAD X8 72 wire-bonded with VSS pins. A buffer unit 74 for buffering an external signal applied to the option pad PAD X4 70 to generate the package option signal sX4, and a package option signal sX8 by buffering an external signal applied to the package option pad PAD X8 72. A buffer unit 76 for generating a. Here, the buffer units 74 and 76 each have two inverters connected in series.

The test mode package option providing unit 62 includes a test mode generator 78 for generating the test mode bandwidth control signals test_mode_X8z and test_mode_X4z.

The package option selector 64 is inserted into an output terminal of the normal mode package option provider 60, and includes a first switching unit SW1 for blocking an output of the normal mode package option provider 60 in a test mode; A second switching unit SW2 for delivering a package option signal set corresponding to the X8 package option to the output terminal in the test mode and a third switching for delivering a package option signal set corresponding to the X4 package option to the output terminal in the test mode The part SW3 is provided. The first switching unit SW1 is controlled by the output of the NAND gate NAND1 having the test mode bandwidth control signals test_mode_X8z and test_mode_X4z as inputs, and transmits an output signal of the buffer units 74 and 76 to the output terminal. TG1, TG2). The transmission gates TG1 and TG2 are simultaneously turned on / off by receiving the output of the NAND gate NAND1 and the signal inverted through the inverter INV1 with the same polarity. The second switching unit SW2 includes transmission gates TG3 and TG4 controlled by the test mode bandwidth control signal test_mode_X8z to transfer VSS and VDD to an output terminal. The transmission gates TG3 and TG4 are simultaneously turned on / off by receiving the test mode bandwidth control signal test_mode_X8z and the signal inverted through the inverter INV2 with the same polarity. The third switching unit SW2 includes transmission gates TG5 and TG6 controlled by the test mode bandwidth control signal test_mode_X4z to transfer VDD and VSS to an output terminal. The transmission gates TG5 and TG6 are simultaneously turned on / off by receiving the test mode bandwidth control signal test_mode_X4z and the signal inverted through the inverter INV3 with the same polarity.

Here, the NAND gate NAND1 may be implemented as an AND gate and an inverter, and may be implemented using another logic gate (eg, a NOA gate). In addition, the transmission gates TG1 to TG6 may be replaced with other switching elements (eg, MOS transistors).

Hereinafter, an operation of the semiconductor memory device having the package option signal generation circuit configured as described above will be described.

First, in the normal mode, the test mode bandwidth control signals test_mode_X8z and test_mode_X4z both indicate logic level high. Accordingly, since the outputs of the NAND gate NAND1 and the inverter INV1 are logic level low and high states, the two transmission gates TG1 and TG2 are turned on, and the outputs of the buffer units 74 and 76 are converted into package option signals. Output as sX4 and sX8. In FIG. 7, the package option pads PAD X4 70 and PAD X8 72 are both wire-bonded with the VSS pin so that both the sX4 and sX8 represent logic level lows, so the chip operates at X16.

Next, in the test mode, any one of the test mode bandwidth control signals test_mode_X8z and test_mode_X4z is enabled to the logic level low so that the outputs of the NAND gate NAND1 and the inverter INV1 become the logic level high and low states, respectively. This turns off the transmission gates TG1 and TG2.

First, a case in which the test mode bandwidth control signal test_mode_X8z is output at logic level high and test_mode_X4z is output at logic level low in the test mode generator 78 will be described. In this case, as described above, the transmission gates TG1 and TG2 of the first switching unit SW1 are turned off to block the output paths of the buffer units 74 and 76. Meanwhile, the transmission gates TG3 and TG4 of the second switching unit SW2 are turned on to output VSS and VDD, respectively. At this time, since the package option signals sX4 and sX8 represent logic level low and high, respectively, the chip operates as X8.

Second, a case in which the test mode bandwidth control signal test_mode_X8z is output at a logic level low and test_mode_X4z is output at a logic level high in the test mode generator 78 will be described. In this case, as described above, the transmission gates TG1 and TG2 of the first switching unit SW1 are turned off to block the output paths of the buffer units 74 and 76. Meanwhile, the transmission gates TG5 and TG6 of the third switching unit SW3 are turned on to output VDD and VSS, respectively. At this time, since the package option signals sX4 and sX8 represent logic level high and low, respectively, the chip operates as X4.

Table 2 below is an operation table showing the operating bandwidth in the test mode of the X16 package.

X4 X8 X16 test_mode_X4z L H H test_mode_X8z H L H sX4 H L L sX8 L H L

Referring to Table 2, in case of the X16 package, if the test mode bandwidth control signals test_mode_X4z and test_mode_X8z are logic level low (L) and high (H), the corresponding package is operated as X4 to test the X4 package characteristics. If the test mode bandwidth control signals test_mode_X4z and test_mode_X8z are logic level high (H) and low (L), respectively, the package operates as X8 to test the X8 package characteristics. In the present invention, the test mode means a test mode for changing a package option, and the X16 package characteristic may be tested in a normal mode state. Therefore, it is possible to simply test the default bandwidth as well as the other bandwidth in one chip packaged with the default.

Meanwhile, Table 2 above illustrates the test mode operation in the X16 package, but the present invention can be applied to the X8 package or the X4 package in principle. For example, the X8 package can wire-bond VSS pins and VDD pins to package option pads PAD X4 and PAD X8, respectively, and use test_mode_X4 and test_mode_X16z for test mode bandwidth control.

Tables 3 and 4 below are operation tables showing operating bandwidths in the test mode of the X8 package and the X4 package, respectively. Note that even when the present invention is applied to the X8 package and the X4 package, wire bonding is performed on all the DQ pins as shown in FIG. 5.

X4 X8 X16 test_mode_X4z L H H test_mode_X16z H H L sX4 H L L sX8 L H L

X4 X8 X16 test_mode_X8z H L H test_mode_X16z H H L sX4 H L L sX8 L H L

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the case in which the X4 / X8 / X16 package option is determined using the X4 PAD and the X8 PAD as the package option pad has been described as an example, but the present invention uses the X4 PAD and X16 PAD as the package option pad. This also applies to X8 PAD and X16 PAD as a package option pad.

The present invention can also be applied to the case where the number of package option pads is added or subtracted according to the number of operating bandwidths.

Currently, semiconductor memory chips are packaged in bandwidths of X4 / X8 / X16. Thus, in order to characterize each package of X4 / X8 / X16 on one chip, packages for all three bandwidths must be manufactured and tested on each of them. However, the present invention can significantly reduce package cost and package test time by implementing the remaining product family as an internal option in addition to the product family determined by wire bonding.

1 is a pinout diagram of a typical X4 and X16 SDRAM (54 pins).

2 is a pinout diagram of a typical X4, X8 and X16 DDR SDRAM (66 pins).

3 is a wire bonding diagram for each package option according to the prior art.

4 is a circuit diagram of a package option signal generation block according to the prior art.

Figure 5 is an illustration of a wire bonding structure for each package option applied to the present invention.

6 is a block diagram of a package option signal generation circuit in accordance with an embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of the package option signal generation circuit of FIG. 6. FIG.

* Explanation of symbols for the main parts of the drawings

60: normal mode package option provider

62: test mode package option provider

64: package option selection

test_mode_X: Test Mode Bandwidth Control Signal

Claims (15)

delete delete delete delete delete First and second package option pads; First and second buffer units configured to generate first and second default package option signals by buffering an external signal applied according to a bonding combination of the first and second package option pads; A test mode generator configured to generate first and second test mode bandwidth control signals for providing first and second test mode package options except for a default package option in a test mode; A first switching unit for blocking an output path of the default package option signal in response to the first and second test mode bandwidth control signals in a normal mode; A second switching unit for enabling output paths of first and second internal option signals corresponding to the first test mode package option in response to the first test mode bandwidth control signal; And A third switching unit for enabling output paths of third and fourth internal option signals corresponding to the second test mode package option in response to the second test mode bandwidth control signal in a test mode; A semiconductor memory device having a. The method of claim 6, Multiple data input / output pins, And a plurality of wires bonded to each of the data input / output pins. The method according to claim 6 or 7, The first switching unit, A logic gate unit for logically combining the first and second test mode bandwidth control signals; And first and second switches controlled by the output of the logic gate part to switch outputs of the first and second buffer parts. The method of claim 8, And the logic gate portion includes a NAND gate to receive the first and second test mode bandwidth control signals. The method of claim 8, The second switching unit, And third and fourth switches configured to switch the first and second internal option signals under the control of the first test mode bandwidth control signal. The method of claim 10, The third switching unit, And fifth and sixth switches configured to switch the third and fourth internal option signals under the control of the second test mode bandwidth control signal. The method of claim 11, Each of the first to sixth switches includes a transmission gate. The method according to claim 6 or 7, The first and second package option pads are X4 pads and X8 pads. The method according to claim 6 or 7, The first and second package option pads are X4 pads and X16 pads. The method according to claim 6 or 7, The first and second package option pads are X8 pads and X16 pads.