CN107705820B - Test mode multiplexer and memory chip - Google Patents
Test mode multiplexer and memory chip Download PDFInfo
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- CN107705820B CN107705820B CN201711108202.8A CN201711108202A CN107705820B CN 107705820 B CN107705820 B CN 107705820B CN 201711108202 A CN201711108202 A CN 201711108202A CN 107705820 B CN107705820 B CN 107705820B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention provides a test mode multiplexer which is used for a memory chip and comprises a test mode switch and a normal operation switch, wherein when the test mode switch is controlled to be opened, a test signal is input to an internal circuit for testing, after the test is finished, when the normal operation switch is controlled to be opened, the normal operation signal is input to the internal circuit for operation, so that the protection of the internal circuit during normal operation is ensured, the damage of the input signal to the internal circuit is avoided, and meanwhile, the normal operation path is not influenced by the test path. The invention also provides a memory chip, which has the technical effects.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test mode multiplexer and a memory chip.
Background
The multiplexer can select a signal from a plurality of analog or digital input signals and forward it, outputting different selected signals to the same output line. By adopting the multiplexer, multiple paths of data information can share one channel. In existing DDR memories, especially DDR3/DDR4, there is no test mechanism for input signals such as voltage or time signals, resulting in damage to the internal circuitry of the memory chip when signals are input to DDR3/DDR 4.
Therefore, how to test the DDR memory is a technical problem that the skilled person is required to solve.
Disclosure of Invention
The present invention provides a test mode multiplexer, and a memory chip, to overcome or alleviate one or more of the problems of the prior art, and at least provide a beneficial choice.
As one aspect of the present invention, there is provided a test mode multiplexer for a memory chip, comprising:
the test mode switch is provided with a test signal input end, a test signal control end and a test signal output end, wherein the test signal input end is used for receiving a test signal, the test signal output end is connected with an internal circuit of the memory chip, and the test signal control end is used for receiving a first control signal for controlling the on-off of the test mode switch; and
The normal operation switch is provided with a normal operation input end, a normal operation control end and a normal operation output end, wherein the normal operation input end is used for receiving a normal operation signal, the normal operation output end is connected with the internal circuit of the memory chip, and the normal operation control end is used for receiving a second control signal for controlling the on-off of the normal operation switch.
Preferably, in the above test mode multiplexer, the test mode switch includes a first PMOS transistor and a first NMOS transistor, where one gate of the first PMOS transistor or a gate of the first NMOS transistor is configured to receive the first control signal for controlling on/off of the test mode switch, one source of the first PMOS transistor and one source of the first NMOS transistor is configured to receive the test signal, and one of the first PMOS transistor and the first NMOS transistor is connected to the internal circuit.
Preferably, in the above test mode multiplexer, the normal operation switch includes a second PMOS transistor and a second NMOS transistor, where a gate of the second PMOS transistor and a gate of the second NMOS transistor are configured to receive a second control signal for controlling on-off of the normal operation switch, one of the second PMOS transistor and the first NMOS transistor is configured to receive the normal operation signal, and a drain of the second PMOS transistor and one of the second NMOS transistor are connected to the internal circuit.
Preferably, in the test mode multiplexer, the test mode multiplexer further includes:
the first output end of the controller is connected to the test signal control end in the test mode switch, the second output end of the controller is connected to the normal working control end, the first input end of the controller is used for receiving a switching command, the controller is used for sending the first control signal to the test signal control end and sending the second control signal to the normal working control end according to the switching command, and the signals of the first control signal and the second control signal are opposite.
Preferably, in the above test mode multiplexer, the second input end of the controller is connected to the internal circuit, and the second input end of the controller is configured to receive one of a test end command and a normal operation end command fed back by the internal circuit, send the second control signal to the normal operation control end according to the test end command, or receive the normal operation end command fed back by the internal circuit, and send the first control signal to the test signal control end according to the normal operation end command.
Preferably, in the above test mode multiplexer, the internal circuit includes a MOS transistor, and a gate of the MOS transistor is connected to the test signal output terminal of the test mode switch and the normal operation output terminal of the normal operation switch.
Preferably, in the above test mode multiplexer, the internal circuit includes a power supply, and the test signal output terminal connected to the test mode switch is connected to the normal operation output terminal of the normal operation switch.
In another aspect, the present invention further provides a memory chip, including a test multiplexer as set forth in any one of the above.
The invention adopts the technical scheme and has the following advantages: through the route switching between test mode switch and the normal operating switch, when control test mode switch was opened, input test signal to internal circuit test, after the test was accomplished, when control normal operating switch was opened, input normal operating signal to internal circuit operated, guaranteed at normal operating time, to internal circuit's protection, avoided the signal of input to cause the damage to internal circuit, simultaneously, normal operating route did not receive the influence of test route.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
Fig. 1 is a schematic circuit diagram of a test mode multiplexer according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a test mode multiplexer including a controller according to an embodiment of the present invention.
Fig. 3 is a schematic circuit diagram of another test mode multiplexer according to an embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of another test mode multiplexer including a controller according to an embodiment of the present invention.
Reference numerals:
100. an internal circuit; 101MOS tube; 102. a power supply;
200. a test mode switch;
201. a test signal control end; 202. a test signal input; 203. a test signal output;
300. a normal mode switch;
301. a normal operation control end; 302. a normal operation input; 303. a normal operation output end;
210. a first PMOS tube; 220. a first NMOS tube;
211. a grid electrode of the first PMOS tube; 212. a grid electrode of the first NMOS tube;
310. a second PMOS tube; 320. a second NMOS tube;
311. a grid electrode of the second PMOS tube; 312. a grid electrode of the second NMOS tube;
400. a controller;
401. a first output of the controller; 402. a second output of the controller;
403. a first input of the controller; 404. a second input of the controller.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Example 1
In one embodiment, a test mode multiplexer is provided, as shown in fig. 1, for a memory chip, comprising:
the test mode switch 200, the test mode switch 200 has a test signal input end 202, a test signal control end 201 and a test signal output end 203, the test signal input end 202 is used for receiving a test signal, the test signal output end 203 is connected with the internal circuit 100 of the memory chip, and the test signal control end 201 is used for receiving a first control signal for controlling the on-off of the test mode switch 200; and
The normal operation switch 300, the normal operation switch 300 has a normal operation input end 302, a normal operation control end 301, and a normal operation output end 303, the normal operation input end 302 is used for receiving a normal operation signal, the normal operation output end 303 is connected with the internal circuit 100 of the memory chip, and the normal operation control end 301 is used for receiving a second control signal for controlling the on-off of the normal operation switch 300.
In this embodiment, in the test mode switch 200 and the normal operation switch 300 are switched to each other, in the test mode, the test signal control end 201 receives a first control signal for controlling the on/off of the test mode, if the first control signal controls the test mode switch 200 to be turned on, the test signal enters the internal circuit 100 of the memory chip through the test signal input end 202 and the test signal output end 203, the internal circuit 100 obtains a parameter range of normal operation of the internal circuit 100 according to the test signal, the second control signal controls the normal operation switch 300 to be turned on, and the normal operation signal enters the internal circuit 100 through the normal operation input end 302 and the normal operation output end 303, so that protection of the internal circuit 100 during normal operation is ensured, damage to the internal circuit 100 caused by the input signal is avoided, and meanwhile, a path of normal operation is not affected by the test path.
On the basis of the above-mentioned test mode multiplexer, as shown in fig. 3 and 4, the test mode switch 200 includes a first PMOS tube 210 and a first NMOS tube 220, one gate (211 or 212) of the first PMOS tube and the first NMOS tube is used for receiving a first control signal for controlling on/off of the test mode switch 200, one source of the first PMOS tube 210 and one source of the first NMOS tube 220 are used for receiving a test signal, and one drain of the first PMOS tube 210 and one drain of the first NMOS tube 220 are connected with the internal circuit 100.
The gate 211 of the first PMOS transistor or the gate 212 of the first NMOS transistor is a test signal control end 201, the source of the first PMOS transistor 210 or the source of the first NMOS transistor 220 is a test signal input end 202, and the drain of the first PMOS transistor 210 or the drain of the first NMOS transistor 220 is a test signal output end 203.
On the basis of the test mode multiplexer, the normal operation switch includes a second PMOS transistor 310 and a second NMOS transistor 320, where a gate 311 of the second PMOS transistor or a gate 312 of the second NMOS transistor is configured to receive a second control signal for controlling on/off of the normal operation switch 300, and a source of the second PMOS transistor 310 or a source of the first NMOS transistor 220 is configured to receive the normal operation signal, and a drain of the second PMOS transistor 310 or a drain of the second NMOS transistor 320 is connected to the internal circuit 100.
The gate 311 of the second PMOS transistor or the gate 312 of the second NMOS transistor is the normal operation control end 301, the source of the second PMOS transistor 310 or the source of the second NMOS transistor 320 is the normal operation input end 302, and the drain of the second PMOS transistor 310 or the drain of the second NMOS transistor 320 is the normal operation output end 303.
On the basis of the test mode multiplexer, as shown in fig. 2 and 4, the method further includes:
the controller 400, the first output terminal 401 of the controller is connected to the test signal control terminal 201 in the test mode switch 200, the second output terminal 402 of the controller is connected to the normal operation control terminal 301 in the normal operation switch 300, the first input terminal 403 of the controller is used for receiving the switching command, the controller 400 is used for sending the first control signal to the test signal control terminal 201 according to the switching command, and sending the second control signal to the normal operation control terminal 301, and the signals of the first control signal and the second control signal are opposite.
When testing, the controller 400 sends a first control signal indicating that the test mode switch 200 is turned on to the test signal control terminal 201 according to the switching command, controls the test mode switch 200 to be turned on, sends a second control signal indicating that the normal operation mode switch is turned off to the normal operation control terminal 301, and controls the normal operation switch 300 to be turned off, so as to enter a test stage, and then the test mode switch 200 receives the test signal and sends the test signal to the internal circuit 100 for testing.
If the test is finished, the controller 400 sends a second control signal indicating that the normal operation mode switch is turned on to the normal switch control terminal according to the switching command, controls the normal operation mode switch to be turned on, sends a first control signal indicating that the test mode switch 200 is turned off to the test signal control terminal 201, controls the test mode switch 200 to be turned off, thereby entering the normal operation stage, and then the normal operation switch 300 receives the normal operation signal and sends the normal operation signal to the internal circuit 100.
It should be noted that the first output terminal 401 of the controller may be connected to the gate 211 of the first PMOS transistor or the gate 212 of the first NMOS transistor in the test mode switch 200, and the second output terminal 402 of the controller may be connected to the gate 311 of the second PMOS transistor or the gate 312 of the second NMOS transistor in the normal operation switch 300, which are all within the protection scope of the present embodiment.
On the basis of the above-mentioned test mode multiplexer, the second input 404 of the controller is connected to the internal circuit 100, and the second input 404 of the controller is configured to receive one of a test end command and a normal operation end command fed back by the internal circuit 100, send a second control signal to the normal operation control end 301 according to the test end command, or receive the normal operation end command fed back by the internal circuit 100, and send a first control signal to the test signal control end 201 according to the normal operation end command.
The controller 400 may control the switching between the test mode switch 200 and the normal operation switch 300 through a test end command or a normal operation end command fed back from the internal circuit 100, in addition to receiving the switching command through the first input terminal.
On the basis of the above-mentioned test mode multiplexer, as shown in fig. 2, the internal circuit 100 includes a MOS transistor 101, and the test signal output terminal 203 of the test mode switch 200 and the normal operation output terminal 303 of the normal operation switch 300 are connected to the gate of the MOS transistor 101.
Wherein the test signal received by the test signal input 202 comprises receiving a test voltage signal. The threshold voltage range of the MOS tube 101 in the internal circuit 100 is tested by receiving the test voltage signal, so that the internal circuit 100 is prevented from being damaged when the memory chip works normally.
On the basis of the above-described test mode multiplexer, as shown in fig. 2, the internal circuit 100 includes a power supply 102, and the test signal output terminal 203 of the test mode switch 200 and the normal operation output terminal 303 of the normal operation switch 300 are connected to the power supply 102.
Wherein the test signal received by the test signal input 202 includes a test charging time signal. Testing the charge time signal includes: tRCD, (RAS-to-CAS Delay, delay time for the transmission of a Row address to a column address), the difference between the Row address and column address clock cycles, or tRP, (Row-precharge Delay, memory Row address strobe precharge time), i.e., the clock cycle required for precharge before the arrival of the next memory cycle, tRAS, (Row-active Delay, memory Row address strobe Delay time), etc., including, but not limited to, the several time signals described above.
Taking the input test charge time signal as tRP as an example, DDR3 or DDR4 needs to be precharged for so much time as to prepare for the next access operation when the column operation is ended, so that the time threshold range of tRP is measured in the test mode, ensuring that the internal circuit 100 operates at the proper charge time when the memory chip is operating normally.
It should be noted that in the above embodiment, the internal circuit and the test mode switch, the normal operation switch, and the controller are all provided inside the memory chip.
Example two
The invention also provides a memory chip comprising a test multiplexer as claimed in any one of the preceding claims.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A test mode multiplexer for a memory chip, comprising:
the test mode switch is provided with a test signal input end, a test signal control end and a test signal output end, wherein the test signal input end is used for receiving a test signal, the test signal output end is connected with an internal circuit of the memory chip, and the test signal control end is used for receiving a first control signal for controlling the on-off of the test mode switch; and
The normal working switch is provided with a normal working input end, a normal working control end and a normal working output end, wherein the normal working input end is used for receiving a normal operation signal, the normal working output end is connected with the internal circuit of the memory chip, the normal working control end is used for receiving a second control signal for controlling the on-off of the normal working switch,
in a test mode, the test signal control end receives the first control signal and controls the test mode switch to be opened, the test signal enters the internal circuit through the test signal input end and the test signal output end, the internal circuit obtains a parameter range of normal operation of the internal circuit according to the test signal, then, the second control signal controls the normal operation switch to be opened, and the normal operation signal enters the internal circuit through the normal operation input end and the normal operation output end.
2. The test mode multiplexer of claim 1, wherein the test mode switch comprises a first PMOS transistor and a first NMOS transistor, wherein a gate of the first PMOS transistor and the first NMOS transistor is configured to receive the first control signal for controlling on/off of the test mode switch, wherein a source of the first PMOS transistor and the first NMOS transistor is configured to receive the test signal, and wherein a drain of the first PMOS transistor and the first NMOS transistor is configured to be connected to the internal circuit.
3. The test mode multiplexer of claim 2, wherein the normal operation switch comprises a second PMOS transistor and a second NMOS transistor, wherein a gate of the second PMOS transistor and the second NMOS transistor is configured to receive a second control signal for controlling on/off of the normal operation switch, wherein a source of the second PMOS transistor and the first NMOS transistor is configured to receive the normal operation signal, and wherein a drain of the second PMOS transistor and the second NMOS transistor is connected to the internal circuit.
4. The test mode multiplexer of claim 1, further comprising:
the first output end of the controller is connected to the test signal control end in the test mode switch, the second output end of the controller is connected to the normal operation control end in the normal operation switch, the first input end of the controller is used for receiving a switching command, the controller is used for sending the first control signal to the test signal control end and sending the second control signal to the normal operation control end according to the switching command, and the signals of the first control signal and the second control signal are opposite.
5. The test mode multiplexer of claim 4, wherein a second input of the controller is coupled to the internal circuit, the second input of the controller is configured to receive one of a test end command and a normal operation end command fed back by the internal circuit, send the second control signal to the normal operation control terminal according to the test end command, and send the first control signal to the test signal control terminal according to the normal operation end command.
6. The test mode multiplexer of any one of claims 1-5, wherein a MOS transistor is included in the internal circuit, a gate of the MOS transistor being connected to the test signal output of the test mode switch and the normal operation output of the normal operation switch.
7. The test mode multiplexer of any one of claims 1 to 5, wherein a power supply is included in the internal circuit, connected to the test signal output of the test mode switch and the normal operation output of the normal operation switch.
8. A memory chip comprising the test mode multiplexer of claim 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711108202.8A CN107705820B (en) | 2017-11-08 | 2017-11-08 | Test mode multiplexer and memory chip |
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| CN201711108202.8A CN107705820B (en) | 2017-11-08 | 2017-11-08 | Test mode multiplexer and memory chip |
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| CN107705820B true CN107705820B (en) | 2024-03-26 |
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| CN109901051A (en) * | 2019-03-01 | 2019-06-18 | 马鞍山创久科技股份有限公司 | A kind of chip Dynamic Current Testing system |
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| US5594694A (en) * | 1995-07-28 | 1997-01-14 | Micron Quantum Devices, Inc. | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell |
| US5815511A (en) * | 1995-10-13 | 1998-09-29 | Fujitsu Limited | Semiconductor integrated circuit equipped with test circuit |
| KR20040000260A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Semiconductor memory device for reducing package test time |
| CN207409263U (en) * | 2017-11-08 | 2018-05-25 | 睿力集成电路有限公司 | A kind of test pattern multiplexer and storage chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040101660A (en) * | 2003-05-26 | 2004-12-03 | 삼성전자주식회사 | Output buffer circuits having signal path use for test and the test method of the same |
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| US4873669A (en) * | 1986-07-30 | 1989-10-10 | Mitsubishi Denki Kabushiki Kaisha | Random access memory device operable in a normal mode and in a test mode |
| US5594694A (en) * | 1995-07-28 | 1997-01-14 | Micron Quantum Devices, Inc. | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell |
| US5815511A (en) * | 1995-10-13 | 1998-09-29 | Fujitsu Limited | Semiconductor integrated circuit equipped with test circuit |
| JP3607760B2 (en) * | 1995-10-13 | 2005-01-05 | 富士通株式会社 | Semiconductor integrated circuit device |
| KR20040000260A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Semiconductor memory device for reducing package test time |
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