CN107705820A - A kind of test pattern multiplexer and storage chip - Google Patents
A kind of test pattern multiplexer and storage chip Download PDFInfo
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- CN107705820A CN107705820A CN201711108202.8A CN201711108202A CN107705820A CN 107705820 A CN107705820 A CN 107705820A CN 201711108202 A CN201711108202 A CN 201711108202A CN 107705820 A CN107705820 A CN 107705820A
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- 238000012360 testing method Methods 0.000 title claims abstract description 152
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 2
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- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention provides a kind of test pattern multiplexer, for storage chip, switched including test mode switch and normal work, switched by the path between test mode switch and normal work switch, when controlling test mode switch opening, input test signal to internal circuit is tested, after the completion of test, when controlling normal work switch opening, input normal work signal to internal circuit is run, it ensure that in normal work, protection to internal circuit, the signal of input is avoided to cause to damage to internal circuit, simultaneously, the influence in the path of normal operation not tested person path.Present invention also offers a kind of storage chip, has above-mentioned technique effect.
Description
Technical field
The present invention relates to technical field of semiconductors, is related to a kind of test pattern multiplexer, further relates to a kind of storage chip.
Background technology
Multiplexer can select some signal and be forwarded from multiple analog or digital input signals, will be different
Selected signal output is into same outlet line.Using multiplexer, the path channels of multichannel data information sharing one can be made.
In existing DDR memory, especially DDR3/DDR4, do not have test machine to the signal such as voltage or time signal of input
System, causes when to DDR3/DDR4 input signals, the internal circuit damage of storage chip.
Therefore, it is that those skilled in the art are badly in need of technical problems to be solved that test how is carried out to DDR memory.
The content of the invention
The present invention provides a kind of test pattern multiplexer, and a kind of storage chip, to overcome or alleviated by background technology
Existing one or more problem, provide at a kind of beneficial selection.
As one aspect of the present invention, there is provided a kind of test pattern multiplexer, for storage chip, including：
Test mode switch, the test mode switch have test signal input, test signal control terminal and test
Signal output part, the test signal input are used to receive test signal, and the test signal output end connects storage chip
Internal circuit, the test signal control terminal is used to receive the first control signal for controlling the test mode switch break-make；
And
Normal work switchs, and normal work switch is with normal work input, normal work control terminal and normal
Working outputs, the normal work input are used to receive normal operation signal, described in the normal work output end connection
The internal circuit of storage chip, the normal work control terminal, which is used to receiving, controls the of the normal work switch on and off
Two control signals.
Preferably, in above-mentioned test pattern multiplexer, the test mode switch includes the first PMOS and first
NMOS tube, a wherein grid for first PMOS or the grid of first NMOS tube, which are used to receive, controls the test mould
A wherein source electrode for first control signal of formula switch on and off, first PMOS and first NMOS tube is used to connect
Wherein the one of Acceptance Tests signal, first PMOS and first NMOS tube is connected with the internal circuit.
Preferably, in above-mentioned test pattern multiplexer, the normal operation switch includes the second PMOS and second
A wherein grid for NMOS tube, the grid of second PMOS and second NMOS tube, which is used to receive, controls the normal work
Make the second control signal of switch on and off, wherein the one of second PMOS and first NMOS tube be used to receiving it is described just
Wherein one drain electrode of normal run signal, second PMOS and second NMOS tube is connected with the internal circuit.
Preferably, in above-mentioned test pattern multiplexer, in addition to：
Controller, the first output end of the controller are connected to the test signal control in the test mode switch
End processed, the second output end of the controller are connected to the normal work control terminal, and the first input end of the controller is used
In receiving switching command, the controller is used to send first control signal to the test letter according to the switching command
Number control terminal and second control signal is sent to the normal work control terminal, first control signal and described the
Both signals of two control signals are opposite.
Preferably, in above-mentioned test pattern multiplexer, the second input of the controller is connected to the internal electricity
Road, for receiving, the test that the internal circuit feeds back terminates order to the second input of the controller and normal operation terminates
One of order, order is terminated according to the test and sends second control signal to the normal work control terminal,
Or receive the normal operation that the internal circuit feeds back and terminate order, terminating order according to the normal operation sends described first
Control signal is to the test signal control terminal.
Preferably, in above-mentioned test pattern multiplexer, the internal circuit includes metal-oxide-semiconductor, the grid of the metal-oxide-semiconductor
It is defeated to be connected to the normal work that the test signal output end of the test mode switch and the normal work switch
Go out end.
Preferably, in above-mentioned test pattern multiplexer, the internal circuit includes power supply, is connected to the test mould
The test signal output end of formula switch connects with the normal work output end that the normal work switchs.
On the other hand, present invention also offers a kind of storage chip, including the test reuse device described in any one as described above.
The present invention uses above-mentioned technical proposal, has the following advantages that：It is switched by test mode switch and normal work
Between path switching, control test mode switch open when, input test signal to internal circuit is tested, test complete
Afterwards, when controlling normal work switch opening, input normal work signal to internal circuit is run, and ensure that in normal work
When, the protection to internal circuit, avoid the signal of input from causing to damage to internal circuit, meanwhile, the path of normal operation is not
The influence in tested person path.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to is limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, it is further by reference to accompanying drawing and the following detailed description, the present invention
Aspect, embodiment and feature would is that what is be readily apparent that.
Brief description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent same or analogous through multiple accompanying drawing identical references
Part or element.What these accompanying drawings were not necessarily to scale.It should be understood that these accompanying drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the electrical block diagram of test pattern multiplexer provided in an embodiment of the present invention.
Fig. 2 is the electrical block diagram of the test pattern multiplexer provided in an embodiment of the present invention for including controller.
Fig. 3 is the electrical block diagram of another test pattern multiplexer provided in an embodiment of the present invention.
Fig. 4 is that the circuit structure for the test pattern multiplexer that another kind provided in an embodiment of the present invention includes controller shows
It is intended to.
Reference：
100 internal circuits；101MOS is managed；102 power supplys；
200 test mode switches；
201 test signal control terminals；202 test signal inputs；203 test signal output ends；
300 normal mode switch；
301 normal work control terminals；302 normal work inputs；303 normal work output ends；
210 first PMOSs；220 first NMOS tubes；
The grid of 211 first PMOSs；The grid of 212 first NMOS tubes；
310 second PMOSs；320 second NMOS tubes；
The grid of 311 second PMOSs；The grid of 312 second NMOS tubes；
400 controllers；
First output end of 401 controllers；Second output end of 402 controllers；
The first input end of 403 controllers；Second input of 404 controllers.
Embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, accompanying drawing and description are considered essentially illustrative rather than restrictive.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", " on ", " under ", "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer ", " up time
The orientation or position relationship of the instruction such as pin ", " counterclockwise ", " axial direction ", " radial direction ", " circumference " be based on orientation shown in the drawings or
Position relationship, it is for only for ease of and describes the present invention and simplify description, rather than indicates or imply that signified device or element must
There must be specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the invention, " multiple " are meant that two or more,
Unless otherwise specifically defined.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integrally；Can be that machinery connects
Connect or electrically connect, can also be communication；Can be joined directly together, can also be indirectly connected by intermediary, can be with
It is connection or the interaction relationship of two elements of two element internals.For the ordinary skill in the art, may be used
To understand the concrete meaning of above-mentioned term in the present invention as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature it " on " or it " under "
Can directly it be contacted including the first and second features, it is not directly to contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " side " and " above " include fisrt feature
Directly over second feature and oblique upper, or it is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature is
Two features " under ", " lower section " and " following " fisrt feature that includes are directly over second feature and oblique upper, or be merely representative of the
One characteristic level is highly less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and
And purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
Embodiment one
In a kind of embodiment, there is provided a kind of test pattern multiplexer, as shown in figure 1, being used for storage chip, wrap
Include：
Test mode switch 200, test mode switch 200 have test signal input 202, test signal control terminal
201 and test signal output end 203, test signal input 202 is used to receive test signal, and test signal output end 203 connects
Connect the internal circuit 100 of storage chip, test signal control terminal 201 is used to receiving the of the control break-make of test mode switch 200
One control signal；And
Normal work switch 300, normal work switch 300 have normal work input 302, normal work control terminal
301 and normal work output end 303, normal work input 302 is used to receive normal operation signal, normal work output end
The internal circuit 100 of 303 connection storage chips, normal work control terminal 301 are used to receive control normal work switch 300
Second control signal of break-make.
In the present embodiment, mutually switch in test mode switch 200 and normal work switch 300, in test pattern
Under, test signal control terminal 201 receives the first control signal of control test pattern break-make, if the control test of the first control signal
Mode switch 200 is opened, and test signal enters storage chip by test signal input 202 and test signal output end 203
Internal circuit 100, internal circuit 100 obtains the parameter area of the normal work of internal circuit 100 according to test signal, second
Control signal control normal work switch 300 is opened, and normal work signal is defeated by normal work input 302 and normal work
Go out end 303 and enter internal circuit 100, ensure that in normal work, the protection to internal circuit 100, avoid the signal of input
Internal circuit 100 is caused to damage, meanwhile, the influence in the path of normal operation not tested person path.
On the basis of above-mentioned test pattern multiplexer, as shown in Figures 3 and 4, test mode switch 200 includes the first PMOS
A wherein grid (211 or 212) for the NMOS tube 220 of pipe 210 and first, the first PMOS and the first NMOS tube, which is used to receive, to be controlled
A wherein source electrode for first control signal of the break-make of test mode switch 200, the first PMOS 210 and the first NMOS tube 220 is used
In receiving test signal, wherein one drain electrode of the first PMOS 210 and the first NMOS tube 220 is connected with internal circuit 100.
Wherein, the grid 212 of the NMOS tube of grid 211 or first of the first PMOS is test signal control terminal 201, first
The source electrode of PMOS 210 or the source electrode of the first NMOS tube 220 are test signal input 202, the drain electrode of the first PMOS 210 or
The drain electrode of first NMOS tube 220 is test signal output end 203.
On the basis of above-mentioned test pattern multiplexer, normal operation switch includes the second PMOS 310 and the 2nd NMOS
Pipe 320, the grid 312 of the NMOS tube of grid 311 or second of the second PMOS are used to receive control normal work 300 break-makes of switch
The second control signal, the source electrode of the source electrode of the second PMOS 310 or the first NMOS tube 220 is used to receive normal operation signal,
The drain electrode of second PMOS 310 or the drain electrode of the second NMOS tube 320 are connected with internal circuit 100.
Wherein, the grid 312 of the NMOS tube of grid 311 or second of the second PMOS is normal work control terminal 301, second
The source electrode of PMOS 310 or the source electrode of the second NMOS tube 320 are normal work input 302, the drain electrode of the second PMOS 310 or
The drain electrode of second NMOS tube 320 is normal work output end 303.
On the basis of above-mentioned test pattern multiplexer, as shown in Figures 2 and 4, in addition to：
Controller 400, the first output end 401 of controller are connected to the test signal control in test mode switch 200
End 201, the second output end 402 of the controller are connected to the normal work control terminal 301 in normal work switch 300, control
The first input end 403 of device processed is used to receive switching command, and controller 400 is used to send the first control signal according to switching command
To test signal control terminal 201, the second control signal is sent to normal work control terminal 301, the first control signal and the second control
Both signals of signal processed are opposite.
Wherein, when being tested, controller 400 is sent according to switching command to be represented to open test mode switch 200
First control signal to test signal control terminal 201, control test mode switch 200 is opened, and is sent and is represented to close normal work
Second control signal of mode switch is to normal work control terminal 301, and control normal work switch 300 is closed, hence into survey
In the examination stage, test mode switch 200 receives test signal afterwards, and sends to internal circuit 100 and tested.
If test terminates, controller 400 is sent according to switching command to be represented to open the second control that normal mode of operation switchs
Signal processed to normal switch control terminal, control normal mode of operation switch is opened, sends and represent to close test mode switch 200
First control signal to test signal control terminal 201, close by control test mode switch 200, hence into normal work stage,
Normal work switch 300 receives normal work signal afterwards, and sends to internal circuit 100.
It is pointed out that the first PMOS that the first output end 401 of controller may be connected in test mode switch 200
The grid 212 of the NMOS tube of grid 211 or first of pipe, the second output end 402 of controller switch connectable to normal work
The grid 312 of the NMOS tube of grid 311 or second of the second PMOS in 300, protection domain in the present embodiment
It is interior.
On the basis of above-mentioned test pattern multiplexer, the second input 404 of controller is connected to internal circuit 100,
Test of second input 404 of controller for receiving the feedback of internal circuit 100 terminates order and normal operation terminates order
One of, order is terminated according to test and sends the second control signal to normal work control terminal 301, or receives internal circuit
The normal operation of 100 feedbacks terminates order, and terminating order according to normal operation sends the first control signal to test signal control
End 201.
Wherein, controller 400 can also pass through internal circuit in addition to receiving switching command by first input end
The test of 100 feedbacks terminates order or normal operation terminates order control test mode switch 200 and normal work switch 300
Between switch over.
On the basis of above-mentioned test pattern multiplexer, as shown in Fig. 2 internal circuit 100 includes metal-oxide-semiconductor 101, test
The normal work output end 303 and metal-oxide-semiconductor 101 of test signal output end 203 and the normal work switch 300 of mode switch 200
Grid connection.
Wherein, the test signal that test signal input 202 receives includes receiving test voltage signal.With internal circuit
The grid of metal-oxide-semiconductor 101 connection in 100, it is therefore an objective to by acceptance test voltage signal come metal-oxide-semiconductor 101 in testing internal circuit 100
Threshold voltage ranges, avoid storage chip in normal work, internal circuit 100 is without damage.
On the basis of above-mentioned test pattern multiplexer, as shown in Fig. 2 internal circuit 100 includes power supply 102, test
The normal work output end 303 of test signal output end 203 and the normal work switch 300 of mode switch 200 is connected to power supply
102。
Wherein, the test signal that test signal input 202 receives includes test charge-time signal.Test the charging interval
Signal includes：TRCD, (RAS-to-CAS Delay, internal memory row address are transferred to the time delay of column address), row addressing and
The difference in row addressable clock cycle, or tRP, (Row-precharge Delay, when internal memory row address strobe is pre-charged
Between), i.e., the clock cycle that the precharge before being arrived in next storage cycle needs, tRAS, (Row-active Delay, it is interior
Deposit row address strobe time delay) etc., certainly, including but not limited to above-mentioned several time signals.
Illustrate so that input test charge-time signal is tRP as an example, at the end of operation is arranged, DDR3 or DDR4 need tRP
So more times enter line precharge, to be prepared for accessing operation next time, therefore, under test pattern, measure tRP's
Time threshold scope, ensure storage chip in normal work, internal circuit 100 is run under the suitable charging interval.
It is pointed out that in above-mentioned embodiment, internal circuit and test mode switch, normal work switch and control
Device processed is arranged inside storage chip.
Embodiment two
Present invention also offers a kind of storage chip, including the test reuse device described in any one as described above.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, its various change or replacement can be readily occurred in,
These should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (8)
- A kind of 1. test pattern multiplexer, for storage chip, it is characterised in that including：Test mode switch, there is test signal input, test signal control terminal and test signal output end, the test letter Number input is used to receive test signal, the internal circuit of the test signal output end connection storage chip, the test letter Number control terminal is used to receive the first control signal for controlling the test mode switch break-make；AndNormal work switchs, and has normal work input, normal work control terminal and normal work output end, the normal work Make input to be used to receive normal operation signal, the normal work output end connects the internal electricity of the storage chip Road, the normal work control terminal are used to receive the second control signal for controlling the normal work switch on and off.
- 2. test pattern multiplexer as claimed in claim 1, it is characterised in that the test mode switch includes the first PMOS A wherein grid for pipe and the first NMOS tube, first PMOS and first NMOS tube, which is used to receive, controls the test A wherein source electrode for first control signal of mode switch break-make, first PMOS and first NMOS tube is used for Test signal is received, wherein one drain electrode of first PMOS and first NMOS tube is connected with the internal circuit.
- 3. test pattern multiplexer as claimed in claim 2, it is characterised in that the normal operation switch includes the 2nd PMOS It is described normal that a wherein grid for pipe and the second NMOS tube, second PMOS and second NMOS tube is used for reception control A wherein source electrode for second control signal of operating switch break-make, second PMOS and first NMOS tube is used to receive Wherein one drain electrode and the internal circuit of the normal operation signal, second PMOS and second NMOS tube connect Connect.
- 4. test pattern multiplexer as claimed in claim 1, it is characterised in that also include：Controller, the first output end of the controller are connected to the test signal control in the test mode switch End, the second output end of the controller are connected to the normal work control terminal in the normal work switch, the control The first input end of device processed is used to receive switching command, and the controller is used to send first control according to the switching command Signal processed is to the test signal control terminal and sends second control signal to the normal work control terminal, and described the Both signals of one control signal and second control signal are opposite.
- 5. test pattern multiplexer as claimed in claim 4, it is characterised in that the second input of the controller is connected to The internal circuit, the test that the second input of the controller is used to receiving the internal circuit feedback terminate order and just One of normal end of run order, order is terminated according to the test and sends second control signal to the normal work Make control terminal, terminating order according to the normal operation sends first control signal to the test signal control terminal.
- 6. the test pattern multiplexer as any one of claim 1 to 5, it is characterised in that wrapped in the internal circuit Metal-oxide-semiconductor is included, the grid of the metal-oxide-semiconductor is connected to the test signal output end of the test mode switch and the normal work Make the normal work output end switched.
- 7. the test pattern multiplexer as any one of claim 1 to 5, it is characterised in that wrapped in the internal circuit Include power supply, be connected to the test mode switch the test signal output end and normal work switch it is described normal Working outputs.
- 8. a kind of storage chip, it is characterised in that including the test pattern multiplexer described in claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711108202.8A CN107705820B (en) | 2017-11-08 | 2017-11-08 | Test mode multiplexer and memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711108202.8A CN107705820B (en) | 2017-11-08 | 2017-11-08 | Test mode multiplexer and memory chip |
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| Publication Number | Publication Date |
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| CN107705820A true CN107705820A (en) | 2018-02-16 |
| CN107705820B CN107705820B (en) | 2024-03-26 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901051A (en) * | 2019-03-01 | 2019-06-18 | 马鞍山创久科技股份有限公司 | A kind of chip Dynamic Current Testing system |
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| KR20040000260A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Semiconductor memory device for reducing package test time |
| US20040239358A1 (en) * | 2003-05-26 | 2004-12-02 | Si-Young Choi | Output buffer circuit having signal path used for testing and integrated circuit and test method including the same |
| CN207409263U (en) * | 2017-11-08 | 2018-05-25 | 睿力集成电路有限公司 | A kind of test pattern multiplexer and storage chip |
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| US4873669A (en) * | 1986-07-30 | 1989-10-10 | Mitsubishi Denki Kabushiki Kaisha | Random access memory device operable in a normal mode and in a test mode |
| US5594694A (en) * | 1995-07-28 | 1997-01-14 | Micron Quantum Devices, Inc. | Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell |
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| KR20040000260A (en) * | 2002-06-24 | 2004-01-03 | 주식회사 하이닉스반도체 | Semiconductor memory device for reducing package test time |
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| CN107705820B (en) | 2024-03-26 |
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