KR100473910B1 - Methods of forming conductive capacitor pulgs, methods of forming capacitor contact openings, and methods of forming memory arrays - Google Patents

Abstract

A method of forming a conductive capacitor plug, a method of forming a capacitor contact hole, and a method of forming a memory array are disclosed. In one embodiment, the conductive capacitor plug is formed to extend from a location proximate the substrate node to a location protruding over all conductive material in adjacent bit lines. In yet another embodiment, the capacitor contact holes are etched through the first insulating material received over the bit line and word line, optionally with a second insulating material covering the portion of the bit line and the word line. This hole is etched to the substrate position adjacent to the word line in a self-aligned manner with respect to the bit line and word line. In another embodiment, the capacitor contact hole is formed to protrude below the bit line after the bit line is formed. In a preferred embodiment, a capacitor-over-bit line memory arrangement is formed.

Description

METHODS OF FORMING CONDUCTIVE CAPACITOR PULGS, METHODS OF FORMING CAPACITOR CONTACT OPENINGS, AND METHODS OF FORMING MEMORY ARRAYS}

The present invention relates to a method of manufacturing a conductive capacitor plug, a method of manufacturing a capacitor contact hole, and a method of manufacturing a memory array.

The semiconductor process includes a number of process steps in which individual layers are masked and etched to form a semiconductor component. Mask alignment is important because even minor misalignments can cause device failure. In some photomasking steps, proper alignment is very important to achieve good fabrication. In the case of some other photomasking steps, the design rules are more relaxed to give a wider range of misalignment. One way to relax design rules is to provide a process sequence that allows for so-called self-aligned etching, such as in encapsulated word lines, in memory circuit fabrication. Furthermore, the aim is to reduce or minimize the number of steps in a particular process flow. Minimizing or reducing the steps reduces the cost and reduces the risk of process errors affecting the final device.

The invention arises from the need associated with improving semiconductor memory arrays and in particular the way capacitor-over-bit line memory arrays are fabricated.

1 is a plan view of a semiconductor wafer portion of a process according to one embodiment of the invention.

FIG. 2 is a plan view of a portion of a semiconductor wafer at a different process step than FIG. 1;

3 is a cross-sectional view taken along line 3-3 of FIG.

4 is a view of the FIG. 3 wafer portion in another process step.

5 is a view of the portion of the FIG. 4 wafer in another process step.

6 is a view of the FIG. 5 wafer portion in another process step.

7 is a view of the FIG. 6 wafer portion in another process step.

8 is a view of the FIG. 7 wafer portion in another process step.

9 is a cross-sectional view taken along line 9-9 of FIG. 8;

10 is a view of the FIG. 9 wafer portion in another process step.

FIG. 11 is a view of the FIG. 10 wafer portion in another process step.

12 is a view of the FIG. 11 wafer portion in another process step.

13 is a view of the FIG. 12 wafer portion in another process step.

FIG. 14 is a cross sectional view along line 14-14 of FIG. 8 having reduced dimensions. FIG.

15 is a view of the FIG. 14 wafer portion in another process step.

FIG. 16 is a view of the FIG. 15 wafer portion in another process step. FIG.

17 is a view of a semiconductor wafer portion in a process according to another embodiment of the invention. 17 is consistent with the processing that may occur following the diagram of FIG. 12.

A method of manufacturing a conductive capacitor plug, a method of manufacturing a capacitor contact hole, and a method of manufacturing a memory array will be described. In one embodiment, the conductive capacitor plug is fabricated to extend from a location proximate the substrate node to a location protruding over all conductive material in adjacent bit lines. In another embodiment, the capacitor contact hole is etched through the first insulating material received over the bit line and word line, optionally with a second insulating material covering the bit line and a portion of the word line. The hole is etched to a substrate location proximate the word line in a self-aligned manner relative to the bit line and the word line. In another embodiment, the capacitor contact hole is formed protruding below the bit line after the bit line is formed. In a preferred embodiment, capacitor-over-bit line memory arrays are formed.

In FIG. 1, the semiconductor wafer portion 20 of the process according to one embodiment of the invention comprises a substrate 22 of semiconductor nature. The substrate 22 includes a plurality of active regions 24 and a plurality of isolation regions 26. Isolation region 26 may be formed by a variety of techniques, including shallow trench isolation.

2 and 3, a plurality of conductive lines 28 are formed over the substrate 22, making up the word lines of the memory arrangement to be formed. Each word line 28 includes a gate oxide layer 30, a conductive polysilicon layer 32, and a silicide layer 34. An insulating covering is formed over the individual word lines 28 and includes sidewall spacers 36 and insulating caps 38. It is preferred that an insulating covering encapsulates the word line. Examples of insulating materials include oxide or nitride / oxynitride materials formed through decomposition of TEOS. A diffusion region 40 is provided, formed in the middle of the word line 28, defining the substrate node location where telecommunication is desired. The diffusion region shown includes a lightly doped drain (LDD) region (not specifically shown).

In FIG. 4, a first layer 42 is formed between conducting lines 28 over the substrate 22. The first layer 42 includes a first insulating material that is different from the insulating material that covers or encapsulates the word line 28. An example of a first insulating material may be borophosphosilicate glass (BPSG glass), which is subsequently flowed back and is generally planarized by conventional techniques to provide a flat top surface 44. A first masking layer 46 is formed over the substrate and defines a plurality of bit line plug mask holes 48. An example material is photoresist.

In FIG. 5, it is preferred that the material of the first layer 42 is etched through the bit line plug mask hole 48 and the individual substrate diffusion regions 40 between the selected word lines 28 are exposed. This etching forms a bit plug hole 50 in the middle of the selected word line.

In FIG. 6, conductive material 52 is formed and electrically connected over the individual substrate diffusion regions 40 below the bit plug holes 50 (FIG. 5). An example material is conductive doped polysilicon, which may be subsequently removed after the polysilicon has been deposited so as to isolate the conductive material in the bit plug holes and form individual plugs 54. Plug 54 may be formed by chemical-mechanical polishing of conductive material 52, or through various etch back techniques.

In FIGS. 7 and 8, individual bit lines 56 are formed and electrically connected to the individual conductive bit line plugs 54. Bit line 56 is formed over insulating material 42 and word line 28 shown. Bit line 56 includes polysilicon layer 58 and silicide or other conductive layer 60 (ie, tungsten). Insulating covering 62 may be formed over the conductive material of the bit line and may include suitable oxide or nitride / oxynitride materials formed through TEOS decomposition. It is preferred that the various bit line layers be blanket deposited on the substrate and then photomasked and etched to provide the bit line shown (FIG. 8). Alternatively, the bit line plug and the bit line may comprise a common material that is deposited during the same process step. For example, layers 52 and 58 may comprise the same material deposited thick enough to form conductive plugs and bit lines 56.

In FIG. 9, a cross section taken along line 9-9 of FIG. 8 is shown. It cuts between three separate bit line plugs 54 and their associated bit lines 56.

In FIG. 10, an insulating material layer is formed over the substrate 22 and etched to provide an insulating covering in the form of sidewall spacers 64. Sidewall spacers 64 serve to encapsulate individual bit lines with insulating covering 62. However, the insulating material that eventually becomes sidewall spacers 64 need not be etched at this time to form the sidewall spacers. Examples of insulating material 64 include oxides formed through TEOS decomposition, or nitrides / oxynitrides. In a preferred embodiment, the insulating material used for the word line (FIG. 3) encapsulation is the same material as the material used for the bit line encapsulation.

In FIG. 11, it is preferred that a second layer 66 is formed over the word line and bit line 56, and the second layer 66 comprises a first insulating material formed over the word line 28, such as BPSG. Layers 42 and 66 constitute a plurality of separately formed layers of the first insulating material, and in the preferred embodiment comprise two layers.

In FIG. 12, a second patterned masking layer 68 is formed over the second layer 66, and a plurality of hole patterns 70 are formed over the various substrate diffusion regions 40. Holes 70 are formed on opposite sides of individual word lines, with individual bit line plugs formed between the individual word lines. A preferred alternative to forming individual holes 70 over the diffusion regions shown is to form so-called stripe openings that can be opened over multiple diffusion regions, where the stripes holes intersect the bit line spacers. An example of a striped hole is shown inside dashed line 72 in FIG. 8.

Whether the individual holes 70 are formed in the second masking layer 68 or the stripe holes 72 are formed, the capacitor contact holes 74 are respectively formed of the first and second layers 42 and 66 of insulating material. Is etched through. In the example shown, the capacitor contact holes 74 are etched to protrude below the bit line 56, to a location adjacent to individual word lines of the memory arrangement. In a preferred embodiment, the etching exposes the individual diffusion regions 40. In this example, and because the individual holes 70 are formed in the second masking layer 68, a portion of the second layer 66 remains on the individual bit lines. However, when the aforementioned striped holes 72 (FIG. 8) are formed, all of the first insulating material 66 on the individual bit lines will ideally be removed.

In a preferred embodiment, the material used for bit line and word line encapsulation may be selected to include the same material. That is, it may be selected to include an optional material that is differentiated for the etching of layers 42 and 66. Thus, the etch chemistry may be selected to etch the materials of the two layers 42, 66 selectively for the material encapsulating both the word line and the bit line. Thus, the capacitor contact hole 74 can be formed in a self-aligning manner to self align to both the bit line and the word line. Aspects of the invention also include a non-capacitor-over-bit line memory array fabrication process, and also include selective etching of contact holes rather than capacitor contact holes.

In FIGS. 13 and 14, conductive material 76 is formed in the individual contact holes 74 and is electrically connected to the individual diffusion regions 40. Examples of such materials are conductive-doped polysilicon, which may be chemically polished or etched back to form individual capacitor plugs 78. In the example shown, conductive material 76 extends from adjacent diffusion region 40 to projections laterally adjacent to individual conducting portions of the bit line. In a preferred embodiment, conductive material 76 extends to a position that protrudes higher than any conductive portion of any bit line. Individual conductive capacitor plugs 78 include separate surfaces 80 adjacent each plug end. Surface 80 is disposed in the projection above the conducting portion of the bit line.

In Figures 15 and 16, an insulating layer 82, such as BPSG, is formed over the substrate and then patterned and etched to form individual capacitor containers 84 (Figure 16). The storage capacitor is formed by depositing the storage node layer 86, the cell dielectric layer 88, and the cell plate layer 90. Thus, this process forms part of the capacitor-over-bit line memory arrangement.

However, in one aspect, the foregoing method may facilitate memory circuit formation over other techniques in which capacitor plugs are formed prior to bit line formation. Such other techniques may reveal alignment issues as long as capacitor container-to-bit line and capacitor container-to-word line alignment is involved. . Aspects of the present invention can form capacitor plugs to self-align to word lines and bit lines while preserving the mask count needed to form a basic memory array. Other aspects of the present invention can alleviate the alignment constraints imposed on capacitor container alignment by eliminating the requirement to etch the container to self-align to other structures, including bit lines.

In FIG. 17, and in accordance with an alternative embodiment of the invention, the storage capacitor may be formed directly in the contact hole 74 (FIG. 12) so that no capacitor plug 78 (FIG. 13) is needed. The same numbers as the above-mentioned embodiments are used where appropriate, and if there is a difference, they are denoted by the subscript "a". Layer 66a is formed over the substrate and then patterned and etched along layer 42 to form capacitor container 84a, as mentioned above. A storage capacitor is then formed by depositing storage node layer 86a, cell dielectric layer 88a, and cell plate layer 90a. Thus, this process forms a conductive material at least partially in the individual contact holes 74. The storage capacitor configuration is shown for illustrative purposes only. Thus, other configurations are possible. For example, the plugging material 76 of FIGS. 13 and 14 may be partially inwardly etched to provide greater space, thus providing greater capacitance for capacitor formation. As another example, some or all of the insulating material outside of the capacitor container side will be etched away prior to capacitor dielectric layer formation to provide greater surface area and greater capacitance. The memory cells of the invention can be fabricated to occupy 6F ² , 8F ² , or other area, with 6F ² being most preferred.

Claims (48)

A method of forming a conductive capacitor plug 78 in a capacitor-over-bit line memory array, the method comprising: Extending the conductive material 76 from a position adjacent the substrate node to a position higher than all of the conductive material in the adjacent bit line 56. The step of stretching the conductive material, Etching through the insulating material a contact hole 74 self-aligned to the bit line 56, and Forming the conductive material 76 in the contact hole 74. And a conductive capacitor plug forming step. The method of claim 1, wherein the etching step, Etching is performed after the bit line 56 is formed. And a conductive capacitor plug forming step. The method of claim 2, wherein the step of forming the conductive material 76, Forming a storage capacitor at least partially in the contact hole 74, And a conductive capacitor plug forming step. The method of claim 1, wherein the etching step, Etching the contact hole 74 through two distinctly formed insulating material layers 42, 66. And a conductive capacitor plug forming step. The method of claim 1, wherein the arrangement comprises a word line 28 extending below the bit line 56, wherein the etching step comprises: Etching the contact hole 74 to self-align both to the bit line 56 and the word line 28, And a conductive capacitor plug forming step. Method according to claim 5, characterized in that the insulating material comprises at least two layers of insulating material (42, 66) formed separately. The method of claim 1, wherein the stretching comprises: Forming a patterned masking layer 68 over the substrate 22 and forming a hole pattern 70 over the substrate node location Including the step of etching, Etching the insulating material through the hole pattern 70 sufficient to form the contact hole 74 after the bit line 56 is formed. And a conductive capacitor plug forming step. 8. The method of claim 7, wherein the hole pattern (70) is formed over a plurality of substrate node locations where individual capacitors are to be formed. The method of claim 1 wherein the substrate node location comprises a diffusion region 40 and the etching step comprises: Etching to expose a portion of the diffusion region 40 after the bit line 56 is formed. The step of forming a conductive material, To form a conductive material 76 electrically connected with the diffusion region 40. And a conductive capacitor plug forming step. 10. A method as claimed in claim 9, wherein the insulating material comprises at least two layers of insulating material (42, 66) formed separately. A method of forming capacitor contact holes in a capacitor-over-bit line memory array, the method comprising: Etching the hole 74 through a first insulating material received over the bit line 56 and the word line 28. Wherein the etching etches the hole 74 through the first insulating material in a manner selective to a second insulating material covering the bit line 56 and the word line 28, wherein the etching The hole (74) is characterized in that it extends to a substrate position self-aligned with respect to the bit line (56) and the word line (28) and adjacent to the word line (28). 12. The method of claim 11 wherein the first insulating material comprises a layer of insulating material (42, 66) formed separately. 12. The method of claim 11 wherein the first insulating material comprises two layers of insulating material (42, 66) formed separately. 12. The method of claim 11 wherein the second insulating material separates and encapsulates the bit line (56) and the word line (28). 12. The method of claim 11 wherein the substrate location comprises a diffusion region 40 and the etching step comprises: Exposing the diffusion region 40 outwardly, And forming a capacitor contact hole. The method of claim 11, wherein the etching step, Removing all the first insulating material from above the bit line, And forming a capacitor contact hole. The method of claim 11, wherein the etching step, Forming a patterned masking layer 68 over said first insulating material forming a hole pattern 70, and Etching the hole 74 along the hole pattern 70, And forming a capacitor contact hole. The method of claim 11, wherein the method is To form a conductive material 76 in the hole 74. And further comprising a step wherein the conductive material (76) extends laterally adjacent to the conductive portion of the bit line (56). The method of claim 11, wherein the method is Forming a conductive material 76 in the hole 74, And further comprising a step in which the conductive material (76) extends to a position higher than any conductive portion of the bit line (56). A method of etching an arrangement of capacitor contact holes 74 in a capacitor-over-bit line memory arrangement, the method comprising: Etching the arrangement of the capacitor contact holes 74 below the bit line 56 after formation of the bit line 56. Wherein the etching step comprises: Etching selectively through the first insulating material to the second insulating material covering the portions of the bit line 56. And etching the capacitor contact hole array. The method of claim 20, wherein the etching step, Etching the holes 74 downward to a position adjacent to the individual substrate diffusion region 40, And etching the capacitor contact hole array. The method of claim 20, wherein the etching step, Etching holes 74 downward to a position adjacent to individual word lines 28 of the arrangement, And etching the capacitor contact hole array. The method of claim 22, wherein the etching step, Exposing an individual substrate diffusion region 40 in the middle of the word line 28, And etching the capacitor contact hole array. delete The method of claim 20, wherein the etching step, Selectively etching through the first insulating material with respect to the second insulating material covering the portion of the word line 28 of the arrangement, And etching the capacitor contact hole array. 26. The method of claim 25, wherein the first insulating material comprises a plurality of first insulating material layers (42, 66) formed separately. The method of claim 20, wherein the method is Forming a conductive material 76 in the contact hole 74, And further comprising a step wherein the conductive material (76) extends laterally close to the bit line (56). The method of claim 20, wherein the method is Forming a conductive material 76 in the contact hole 74, Further comprising a step wherein the conductive material (76) extends to a position higher than any conductive portion of the bit line (56). A method of forming a capacitor-over-bit line memory array, the method comprising: Forming a plurality of word lines 28 over the substrate 22 with the insulating material disposed thereon; Forming a plurality of bit lines 56 overlying the word lines 28 with an insulating material disposed thereon; Forming a first insulating material over the word line 28 and the bit line 56, wherein the first insulating material is different in terms of etchingability from the insulating material over the word line and the insulating material over the bit line, Selectively etch capacitor contact holes 74 through the first insulating material for the insulating material over bit line 56 and the insulating material over word line 28, wherein the hole 74 is connected to the bit line ( 56 and self-aligned to the word line 28 and extends to a position adjacent the substrate 22, A method of forming a capacitor-over-bit line memory array comprising the above steps. 30. The method of claim 29, wherein forming the first insulating material comprises: Forming a plurality of layers of insulating material 42, 66 over one or more of the word line 28 and the bit line 56. And forming a capacitor-over-bit line memory array. 30. The method of claim 29, wherein forming the first insulating material comprises: Forming one insulating material layer 42 over the word line 28, After the bit line 56 is formed, forming a further insulating material layer 66 over the bit line 56. A method of forming a capacitor-over-bit line memory array comprising the above steps. 32. The method of claim 31, wherein Forming a patterned masking layer 68 over the first insulating material to form mask holes 70 Wherein the mask holes 70 are received over a plurality of substrate positions at which capacitor contact holes 74 are to be etched, and the step of etching the capacitor contact holes 74 includes: -Etching the contact holes 74 through the mask holes 70, And forming a capacitor-over-bit line memory array. The method of claim 29, wherein the method is Forming a conductive material 76 in the contact hole 74, And further comprising a step wherein the conductive material 76 is formed to extend from an adjacent individual substrate diffusion region 40 to a position at the same height as the conductive material of the individual bit line 56. A method of forming a bit line memory array. The method of claim 29, wherein the method is Forming a conductive material 76 in the contact hole 74, And further comprising a step wherein the conductive material 76 is formed to extend from an adjacent individual substrate diffusion region 40 to a position higher than any conductive material of the bit line 56. Method of forming a bit line memory array. A method of forming a capacitor-over-bit line memory array, the method comprising: A plurality of word lines 28 are formed over the substrate 22, A plurality of bit lines 56 are formed above the word lines 28, Forming an insulating material over the word line 28 and the bit line 56, After forming the bit line 56, etching the hole 74 through the insulating material and exposing outwardly the diffusion region 40 received in the substrate 22 adjacent the word line 28, And wherein the hole 74 is self-aligned with respect to the word line 28 and the bit line 56 adjacent to the hole 74. Forming method. 36. The method of claim 35, wherein forming the insulating material comprises: Forming two separate layers of insulating material 42, 66 over the substrate 22, Including the step of etching the hole 74, Selectively etching the two layers of insulating material 42, 66 against an insulating covering formed over portions of the bit line 56 and word line 28, And forming a capacitor-over-bit line memory array. 36. The method of claim 35, wherein the method is Forming a conductive material 76 in the hole 74, And wherein the conductive material 76 extends from the adjacent diffusion region 40 to a position higher than any conductive material of the bit line 56. Forming method. A method of forming a memory array, the method comprising: Forming a plurality of conductive lines on the substrate 22, Forming a conductive bit line plug 54 in the middle of the pair of conducting lines 28, Forming a bit line 56 electrically connected to the conductive bit line plug 54, A conductive capacitor plug 78 is formed at a position adjacent to one of the pair of conductive lines 28, wherein the capacitor plug 78 extends away from the substrate 22 and the conducting portion of the bit line 56. Ends from above, Forming a capacitor over capacitor plug 78 that is electrically connected to the capacitor plug 78, and Before forming the conductive bit line plug 54, forming a first insulating material over the conductive line 28. Wherein the step of forming a conductive capacitor plug 78 is above the bit line 56 or the conducting line 28, or above the bit line 56 and the conducting line 28. Selectively etching a hole (74) through the first insulating material relative to the second insulating material. 39. The method of claim 38 wherein the memory array is a capacitor-over-bit line memory array. 39. The method of claim 38 wherein the bit line plug (54) and the bit line (56) comprise one or more common materials. 39. The method of claim 38 wherein the bit line plug (54) and the bit line (56) comprise at least one common material, wherein the common material is deposited in a common processing step. 39. The method of claim 38, wherein forming the capacitor plug 54 comprises: Forming a surface 80 of the capacitor plug 78 higher than any conducting portion of the bit line 56, And forming a memory array. 39. The method of claim 38, wherein forming the conductive capacitor plug 78 comprises: Selectively etching holes 74 into the first insulating material for a second insulating material on the conducting line 28, And forming a memory array. The method of claim 38, wherein the method is Prior to forming the conductive capacitor plug 78, forming a first insulating material over the bit line 56. And further comprising forming conductive capacitor plugs 78, Selectively etching holes 74 into a first insulating material for a second insulating material on the bit line 56, And forming a memory array. The method of claim 38, wherein the method is Prior to the formation of the conductive bit line plug 54, forming a first layer of the first insulating material over the conductive line 28, Prior to formation of the conductive capacitor plug 54, forming a second layer of the first insulating material over the bit line 56, Further comprising the above steps, wherein the step of forming the conductive capacitor plug 78, Selectively etching holes 74 into the first insulating material with respect to the second insulating material over the conducting line 28 and the bit line 56, And forming a memory array. The method of claim 45, wherein the etching step, Exposing a substrate diffusion region 40 adjacent the conducting line 28, And forming a memory array. A method of forming a memory array, the method comprising: Forming a plurality of word lines 28 encapsulated with a first insulating material over the substrate 22, A second layer of insulating material 42 having a flat top surface 44 is formed on the word line 28, Patterning the second insulating material layer 42 to form a bit line plug hole 50 exposing the first substrate diffusion region 40 between the two word lines 28, A conductive material 52 is formed over at least a portion of the second insulating material that is in electrical connection with the first substrate diffusion region 40, Removing a portion of the conductive material 52 over the substrate diffusion region 40 to form a bit line plug 54 in the bit line plug hole 50, A bit line 56 encapsulated with a third insulating material is formed over the second insulating material, wherein the bit line 56 is electrically connected with the bit line plug 54, A fourth layer of insulating material 66 is formed over the bit line 56, Patterning the fourth layer of insulating material 66 to form a hole 70 over the second substrate diffusion region 40, wherein the second substrate diffusion region 40 connects the bit line plug 54. Located opposite one of the two formed word lines 28, thereby forming a hole 74 that is self-aligned to the word line 28 and the bit line 56, Forming a conductive material 76 in the self-aligned hole 74, and extending the conductive material 76 to a position higher than the bit line 56. A memory array forming method comprising the above steps. A method of forming a memory array, the method comprising: Forming a plurality of word lines 28 over the substrate 22 with the insulating material disposed thereon; Forming a plurality of bit lines 56 overlying the word lines 28 with an insulating material disposed thereon; Forming a first insulating material over the word line 28 and the bit line 56, wherein the first insulating material is etched away from the insulating material over the word line 28 and the insulating material over the bit line 56. Different in terms of possible, Selectively etching a contact hole 74 through the first insulating material with respect to the insulating material above the bit line 56 and the insulating material above the word line 28, wherein the hole 74 is the bit line. Self-aligned to 56 and word line 28 and extending to a position adjacent to substrate 22, A memory array forming method comprising the above steps.