JPH10289986A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to ensure sufficient capacitance of a memory cell capacitor even when the capacitor is made fine by a method wherein an anisotropic etching operation is applied to a first conductive film which is deposited on an installing film, a capacitor electrode is formed and a second conductive film is deposited on it so as to form a capacitor. SOLUTION: By a wet etching operation, an insulation film is removed selectively with reference to an etching stopper layer 27, and conductor plugs 27A, 27B protrude upward from the etching stopper layer 27. Then, a conductive amorphous or polysilicon film 29 is deposited uniformly, an anisotropic etching operation which acts in a direction nearly perpendicular to the main face of a substrate 21 is performed to the polysilicon film, and capacitor electrode patterns 29A, 29B are formed on the basis of the conductive film 29. In addition, a thermal oxide film is formed on the patterns, and an SiN film 30 is deposited on the film. In addition, the surface of the SiN film 30 is thermally oxidized, and a polysilicon film 31 is deposited uniformly as a counter electrode so as to cover the electrode patterns 29A, 29B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a capacitor and a method for manufacturing such a semiconductor device. Semiconductor devices, especially DR
In a semiconductor memory device having a capacitor such as an AM, the storage capacity is increasing year by year due to miniaturization. Especially DR
In AM, information is stored in the form of electric charges in a memory cell capacitor. However, if the memory cell capacitor is miniaturized as a result of miniaturization, the amount of electric charge stored in the capacitor decreases. It becomes difficult to determine which of 0 and 0.

Therefore, conventionally, a structure and a manufacturing method of a DRAM capable of minimizing a decrease in capacitance while miniaturizing a device pattern of a semiconductor device have been studied.

[0003]

2. Description of the Related Art FIGS. 13A to 13C and FIG.
(D), (E) is a figure explaining the manufacturing process of the conventional typical DRAM. Referring to FIG. 13A, an oxide film 2 including a field oxide film 2A is formed in an active region on p-type Si substrate 1, and field oxide film 2A defines an active region. In the active region, n ⁺ -type diffusion regions 1A, 1B, and 1C are formed as in a normal memory cell, and a gate pattern 3 made of polysilicon extends on oxide film 2.

The gate pattern 3 is covered with an oxide film 3A,
An interlayer insulating film 4 made of BPSG covers the structure. A contact hole 4A exposing the diffusion region 1B is formed in the interlayer insulating film 4, and a bit line pattern 5 made of polysilicon is formed through the contact hole 4A.
Contact with Further, in the state of FIG.
On the interlayer insulating film 4, an interlayer insulating film 6 made of another BPSG
Are formed so as to fill the bit line pattern 5.

Next, in the step of FIG. 13B, a contact hole 6A penetrating the interlayer insulating films 4 and 6 to expose the diffusion region 1A or 1C is formed. The contact hole 6A
, A polysilicon or amorphous silicon layer 7 is deposited on the interlayer insulating film 6. FIG.
In the step (C), a resist pattern 8 is further formed on the layer 7.
14D, the capacitor pattern 7A is formed on the interlayer insulating film 6 by patterning the layer 7 using the resist pattern 8 as a mask in the step of FIG.

Next, in the step of FIG. 14E, a dielectric film 9 is formed on the capacitor electrode pattern 7A, and a polysilicon film 10 is further deposited thereon.

[0007]

FIG. 15 is a block diagram of FIG.
FIG. 9E is a plan view showing an arrangement of the capacitor electrode pattern 7A on the interlayer insulating film 6 in FIG. Referring to FIG. 15, it can be seen that the electrode pattern 7A has a rounded corner instead of a regular rectangular shape. This is because, if the integration density of the DRAM is increased by miniaturization and at the same time, a sufficient capacitance is required for the memory cell capacitor, the interval between the electrode patterns 7A is inevitably very close. This is because, when the resist pattern 8 is formed, exposure must be performed near the resolution limit of high-resolution lithography. In other words, conventionally, the distance between the electrode patterns 7A is limited by the resolution limit at the time of exposure, and when the DRAM is miniaturized, it is difficult to sufficiently secure the dimensions and therefore the area of the electrode patterns 7A. Met.

Further, in the conventional method shown in FIGS. 13A to 14E, since the resist pattern 8 is used, the number of steps is large, the production cost is increased, and the production throughput of the semiconductor device is reduced. Had. Therefore,
It is a general object of the present invention to provide a semiconductor device and a method for manufacturing the same, which have solved the above problems.

A more specific object of the present invention is to provide a structure of a semiconductor device capable of securing a sufficient capacitance for a memory cell capacitor even when miniaturized, and a method of manufacturing the same. A further object of the present invention is to provide a manufacturing method capable of forming a memory cell capacitor without a mask step in the manufacture of a semiconductor device capable of securing a sufficient capacitance for a memory cell capacitor even when miniaturized.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a capacitor, comprising the steps of: (A) forming an insulating film on a substrate; (B) forming a conductive pillar so as to protrude upward from the insulating film; and (C) depositing a first conductive film on the insulating film so as to cover the conductive pillar. And (D) applying an anisotropic etching to the first conductive film acting substantially perpendicularly to a main surface of the substrate,
Forming a capacitor electrode; (E) depositing a dielectric film on the capacitor electrode; and (F) depositing a second conductive film on the dielectric film;
A method of manufacturing a semiconductor device, comprising: forming a capacitor; or as described in claim 2, wherein the conductive pillar penetrates the insulating film;
The method according to claim 1, wherein the diffusion region formed on the substrate is electrically contacted, or as described in claim 3, the anisotropic etching is performed in the step (D). , Wherein said step (A) is continued by the method of claim 1 or 2, or as described in claim 4, wherein said capacitor electrode is spatially separated from an adjacent capacitor electrode.
A step of covering the surface of the insulating film with an etching stopper layer serving as a stopper for etching acting on the insulating film, between the step (B) and the step (B). The characteristic etching is performed until the etching stopper layer is exposed, by the method according to any one of claims 1 to 3,
Alternatively, as described in claim 5, further comprising the step of forming hemispherical polysilicon grains on the electrode pattern, the step (E) is such that the dielectric film covers the hemispherical polysilicon grains. The method according to any one of claims 1 to 4, or a method for manufacturing a semiconductor device having a capacitor as described in claim 6, wherein the method is performed on a substrate. Forming an interlayer insulating film; forming a first conductive film on the interlayer insulating film; and forming the first conductive film on the first conductive film so as to protrude upward from the surface of the first conductive film. Forming a conductive pillar through the interlayer insulating film; depositing a first insulating film on the conductive pillar along the shape of the conductive pillar; The film is applied to the main surface of the substrate. A first anisotropic etching acting vertically is applied until the top surface of the pillar and the first conductive film are exposed, and a first insulating sleeve is formed by the first insulating film. And after the first anisotropic etching step, on the first conductive film,
Depositing a second conductive film so as to cover the first insulating sleeve and the top surface of the pillar; and forming the second conductive film on the second conductive film substantially perpendicular to the main surface of the substrate. Applying a operative second anisotropic etch until the surface of the interlayer insulating film is exposed to form a first conductive sleeve outside the first insulating sleeve; Removing the sleeve by selective etching, leaving the pillar and the first conductive sleeve such that the first conductive sleeve separates and surrounds the pillar; and a surface of the pillar and the first conductive sleeve. A step of depositing a dielectric film on the surface of the conductive sleeve; and a step of depositing a third conductive film constituting a counter electrode film on the dielectric film. Depending on manufacturing method or request As described in 7, the pillar is formed of a hollow sleeve, and the step of depositing the dielectric film is performed such that the dielectric film also covers the inner wall surface of the hollow sleeve. According to the method of claim 6, or as described in claim 8, the second
After the anisotropic etching step, a fourth conductive film and a second conductive film are formed on the interlayer insulating film before the selective etching step.
A step of sequentially depositing the first insulating sleeve and the first insulating sleeve so as to include the pillar and the first conductive sleeve and the first insulating sleeve surrounding the pillar; Applying a third anisotropic etching that acts substantially perpendicularly to the main surface until the fourth conductive film is exposed, and forming a second insulating sleeve with the second insulating film. Depositing a fifth conductive film on the fourth conductive film so as to include the second insulating sleeve, the fourth conductive film, and the pillar; And performing an anisotropic etching process on the fourth conductive film substantially perpendicularly to the main surface of the substrate until the surface of the interlayer insulating film is exposed. A second conductive film adhered to the first conductive sleeve by a conductive film. The conductive sleeve is formed, the second
A second insulating film surrounding the second conductive sleeve.
Forming an insulating sleeve of the fifth conductive film,
Forming a third conductive sleeve surrounding the second insulating sleeve, wherein the selective etching step includes:
The method according to claim 6 or 7, wherein the second insulating sleeve is removed substantially simultaneously with the first insulating sleeve, or as described in claim 9, wherein A formed substrate, an interlayer insulating film formed on the substrate, a contact hole formed in the interlayer insulating film, exposing the diffusion region, and a capacitor contacting the diffusion region via the contact hole. A conductive pillar extending in the contact hole, one end of which contacts the diffusion region, and the other end of which forms a protrusion protruding from the interlayer insulating film; A storage electrode electrically contacting the protrusion of the conductive pillar, a capacitor dielectric film formed on the storage electrode, and 11. A semiconductor device comprising a formed counter electrode, or as described in claim 10, substantially preventing etching of a material forming the interlayer insulating film on a surface of the interlayer insulating film. The semiconductor device according to claim 9, wherein an etching stopper layer is formed, or the surface of the storage electrode has an irregular shape, as described in claim 11. The conductive pillar is formed of a hollow sleeve defined by an inner wall surface, and the capacitor dielectric film is formed of the conductive pillar by the semiconductor device according to claim 9 or 10. The inner wall surface is covered with a metal.
14. The semiconductor device according to claim 9, wherein the storage electrode is in close contact with the protrusion of the pillar by the semiconductor device according to any one of the above or as described in claim 13. 15. By device or by claim 14
As described in the above, the storage electrode is composed of the conductive pillar itself and one or more conductive sleeves surrounding the conductive pillar, and the capacitor dielectric film is formed of the conductive pillar protrusion and the one or more conductive sleeves. The semiconductor device according to claim 9, wherein the conductive pillar and the one or more conductive sleeves cover the plurality of conductive sleeves. 15. The semiconductor device according to claim 14, wherein the conductive films are electrically connected to each other via a conductive film formed on the film surface.
17. A semiconductor substrate, a word line electrode formed on a surface of the semiconductor substrate with a gate oxide film corresponding to a channel region therebetween, or the semiconductor substrate according to claim 16. A first diffusion region formed corresponding to one end of the channel region, a second diffusion region formed corresponding to the other end of the channel region in the semiconductor substrate, An interlayer insulating film formed on a substrate and covering the gate electrode and the first and second diffusion regions, and formed in the interlayer insulating film;
A first contact hole that exposes the first diffusion region, a second contact hole that is formed in the interlayer insulating film and exposes the second diffusion region, and a first contact hole that exposes the second diffusion region. In a semiconductor device including a memory cell capacitor that contacts the first diffusion region and a bit line electrode that contacts the second diffusion region via the second contact hole, the memory cell capacitor includes A conductive pillar extending in the first contact hole, one end of which is in contact with the first diffusion region, and the other end of which is formed on the interlayer insulating film; A storage electrode that closely contacts the protrusion of the pillar, a capacitor dielectric film formed to cover the storage electrode, and the capacitor dielectric film More it becomes possible and a counter electrode formed on the solved by a semiconductor device according to claim.

Hereinafter, the principle of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the present invention, first, FIG.
In the step (A), an interlayer insulating film 12 is deposited on the semiconductor substrate 11 on which the diffusion regions 11A and 11B have been formed, and the surface of the interlayer insulating film 12 is further etched.
After covering with C, an insulating film (not shown) is further deposited thereon, and contact holes 12A and 12B are formed through the insulating film and the interlayer insulating film 12 to expose the diffusion regions 11A and 11B, respectively. I do. Further, after the contact holes 12A and 12B are filled with a conductor such as polysilicon, the insulating film on the etching stopper layer 12C is removed, so that the conductive pillars 12A and 12A projecting upward from the interlayer insulating film 12 are formed.
Form B. Further, the conductive pillars 12A, 12A
A conductive film 13 made of polysilicon or amorphous silicon is deposited so as to cover B.

Next, in the step of FIG. 1B, the etching stopper layer 12C performs anisotropic etching on the conductive film 13 to act substantially perpendicular to the main surface of the substrate 11. The process is performed until the conductive film 13 is exposed.
Is divided into electrode patterns 13A and 13B. Further, in the step of FIG. 1C, by sequentially depositing a dielectric film 14 and a conductive film 15 on the structure of FIG. 1B, the capacitors C1 and C2 adjacent to each other are removed from the contact holes 12A, It can be formed without performing any masking steps other than the masking step for forming 12B. Since the patterns 13A and 13B are formed without performing the masking process in this way, the distance D between the patterns 13A and 13B can be reduced without causing the alignment error or the exposure resolution limit problem associated with the masking process.
The distance can be substantially reduced from the distance D in FIG.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIGS. 2 (A) to 2 (D) and 3 (E) to 3 (E)
(G) shows a step of manufacturing the DRAM memory cell according to the first embodiment of the present invention. Referring to FIG. 2A, p-type S
An oxide film 22 including a field oxide film 22A is formed in an active region on the i-substrate 21, and the field oxide film 22A defines an active region. In the active region, n ⁺ -type diffusion regions 21A, 21B and 21C are formed as in a normal memory cell, and a gate pattern 23 made of polysilicon extends on the oxide film 22. As usual, the gate pattern 23 forms a word line pattern to the memory cell.

The gate pattern 23 is covered with an oxide film 23A, on which an interlayer insulating film 24 of BPSG covers.
In the interlayer insulating film 24, a contact hole 24A exposing the diffusion region 21B is formed by performing dry etching using a mixed gas of CHF ₃ , CF ₄ and Ar in a parallel plate etcher having an RF frequency of 380 kHz. Then, the bit line pattern 25 made of polysilicon contacts the diffusion region 21B via the contact hole 24A. Further, in the state of FIG. 2A, an interlayer insulating film 26 made of another BPSG is formed on the interlayer insulating film 24.
An etching stopper layer 27 acting as an etching stopper for the film 26 and another insulating film 28 are sequentially deposited on the interlayer insulating film 26 so as to fill the bit line pattern 25. Typically, the interlayer insulating film 24 and the insulating film 28 are made of BPSG or high-density plasma CV.
Is formed from SiO ₂ film deposited by method D, whereas the etching stopper layer 27 is formed of SiN film is typically formed to a thickness of 20 nm.

Next, in the step of FIG. 2B, the films 24 to 24 are formed by high-resolution photolithography using a resist.
28, contact holes 26A and 26B are formed to expose diffusion regions 21A and 21C, respectively. Further, in the step of FIG. 2C, the contact holes 26A and 26B are filled with conductive polysilicon, respectively, and the polysilicon film remaining on the insulating film 28 is selectively removed to form the contact holes 26A and 26B. Plugs 27A, 2 filling plugs 26, 26B
7B is obtained.

Further, in the step of FIG. 2D, the structure of FIG. 2C is wet-etched in an HF or buffered HF aqueous solution, so that the insulating film 28 is selectively formed with respect to the etching stopper layer 27. As a result, the conductor plugs 27A and 27B protrude upward from the etching stopper layer 27. Next, in the step of FIG. 3E, a conductive amorphous or polysilicon film 29 is uniformly deposited on the structure of FIG. 2D, and the polysilicon of FIG. For the membrane 29,
The anisotropic etching acting in a direction substantially perpendicular to the main surface of the substrate 21 is performed in a mixed gas of Cl ₂ and O ₂ using, for example, an ECR etching apparatus. At this time, the anisotropic etching is performed until the etching stopper layer 27 is exposed. As a result, as shown in FIG.
Thus, capacitor electrode patterns 29A and 29B are formed.

In the anisotropic etching step of FIG. 3F, vertical anisotropy is dominant, but it is also possible to use so-called quasi-anisotropic etching in which etching is also performed in the lateral direction. . This is the same in the other embodiments described below. Further, in this embodiment, FIG.
A thermal oxide film is formed on the capacitor electrode patterns 29A and 29B of (F), and a SiN film 30 is deposited thereon. Further, after thermally oxidizing the surface of the SiN film 30, a polysilicon film 31 is uniformly deposited as a counter electrode so as to cover the electrode patterns 29A and 29B. In such a structure, the dielectric film 30 forms a so-called ONO structure together with the upper and lower thermal oxide films thus formed, and both of the electrode patterns 29A and 29B constitute storage electrodes of a DRAM memory cell capacitor.

Since the storage electrode patterns 29A and 29B formed by such a method are formed without using photolithography or a mask process, the distance between the patterns can be reduced without being restricted by the resolution of the exposure system. Can be done. In the present embodiment, the exposure requiring high resolution is only a photolithography process for forming the contact holes 26A and 26B, and a mask process is not used for exposing the storage electrode patterns 29A and 29B. The manufacturing throughput of the device is greatly improved.

In the above description, the conductive pillars 13A, 13A
Although 3B or the deposition of the conductive film 13 is performed from the beginning using amorphous silicon or polysilicon doped with conductive impurities, the present invention is not limited to such a specific embodiment. For example, it is also possible to deposit undoped amorphous silicon or polysilicon, and to introduce impurities into this later to impart conductivity. This is the same for the other embodiments described below. [Second Embodiment] FIG. 4 is a diagram showing a DR according to a second embodiment of the present invention.
2 shows a configuration of an AM memory cell. However, in FIG. 4, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 4, in the present embodiment, substantially hemispherical polysilicon grains (HSG) are formed on the surfaces of the storage electrode patterns 29A and 29B.
A rough surface structure 290 made of ysilicon) is formed, and the capacitor dielectric film 30 is formed so as to cover the rough surface structure 290. By forming the rough surface structure 290, the surface area of the storage electrode pattern 29A or 29B increases, and as a result, the capacitance of the memory cell capacitor increases.

Such hemispherical polysilicon grains are not generally geometrically perfect hemispherical shapes,
Although it has an irregular shape such as being distorted or having a mushroom-like base constriction, in the present invention, these irregular polysilicon grains are also referred to as hemispherical polysilicon grains. Such a rough surface structure 290
For example, the storage electrode pattern is formed in an amorphous silicon state, and a polysilicon film is
It is formed by depositing iH ₄ at a temperature of about 570 ° C. Depositing the polysilicon film on the amorphous silicon film causes non-uniform nucleation on the amorphous silicon surface, resulting in non-uniform growth of hemispherical polysilicon grains on the storage electrode pattern 29A or 29B. Regarding the formation of such a rough surface structure, for example, Tatsumi et al., "Hemispherical Grain Polysilicon Formation Mechanism", Applied Physics Vol.
The year is listed. Third Embodiment Next, a DRA according to a third embodiment of the present invention will be described.
FIGS. 5A to 5C show a method of manufacturing an M memory cell.
This will be described with reference to FIGS. 6 (D) to 6 (F). However, FIGS. 5 (A) to 5 (C) and FIGS. 6 (D) to 6 (F)
Among them, parts corresponding to the parts described above are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, only the portion including the diffusion region 21C and the conductor plug 27B in the structure described above will be described.

Referring to FIG. 5A, the interlayer insulating film 26 in this embodiment also includes the above-described insulating film 24,
A polysilicon conductive film 27A is formed between the etching stopper layer 27 and the insulating film. Therefore, in the present embodiment, the contact holes 26B are formed in the layers 26, 27, 2
7A and 28 extend through the conductor plug 27
B fills a contact hole 26B passing through such layers 26, 27, 27A and 28.

Next, in the step of FIG. 5B, FIG.
As in the step (D), the insulating film 28 is
A is removed by selective etching with respect to
The conductive layer protruding from the film 27A is formed on the conductive film 27A.
SiO 2 so as to cover the lug 27B. _TwoFilm 32 is CVD
More deposited. Next, in the step of FIG.
O_TwoThe film 32 is formed substantially perpendicular to the substrate 21.
Apply a dry etching process to use the conductive film 27A
The dry etching process until the
Therefore, the SiO 2 is formed only on the side wall surface of the pillar 27B._TwoMembrane 3
2 in the form of a sleeve 32A.

Further, in the step of FIG.
On the structure of FIG. 6C, a conductive film 33 made of polysilicon or amorphous silicon is deposited by a CVD method, and in the step of FIG.
Anisotropic etching that acts substantially perpendicular to the main surface of the substrate 21 is performed until the etching stopper layer 27 is exposed, and the conductive film 33 is removed from the insulating sleeve 3.
Only in the outside of 2A is left in the form of a conductive sleeve 33A.

Next, in the step of FIG.
The structure of (E) is immersed in an aqueous HF solution, and the insulating sleeve 3
Dissolve and remove 2A. As a result of the removal of the insulating sleeve 32A, the conductive pillar 27B and the conductive sleeve 33A
In this embodiment, the capacitor dielectric film 30 is formed on the exposed surfaces of the conductive pillar 27B and the conductive sleeve 30. The conductive pillar 27B and the conductive sleeve 33A are electrically connected to each other by the conductive film that has been a part of the conductive film 27A.

Further, in the step of FIG. 6F, the conductive film made of polysilicon or amorphous silicon is deposited as the counter electrode 31 on the capacitor dielectric film 30 so as to fill the gap. . A memory cell capacitor having a similar configuration is formed also for diffusion region 21A. In this embodiment, the surface area of the memory cell capacitor, and thus the capacitance, can be increased without using a mask process. [Fourth Embodiment] FIG. 7 shows a DR according to a fourth embodiment of the present invention.
2 shows a part of an AM memory cell. However, FIG. 7 shows only the configuration of the memory cell capacitor connected to the diffusion region 21C as in the previous embodiment. In addition, the same reference numerals are given to portions corresponding to the portions described above, and description thereof will be omitted.

Referring to FIG. 7, in the present embodiment, another conductive sleeve 36A is formed outside the conductive sleeve 33A at a distance from the sleeve 33A, and the capacitor dielectric film 30 is formed of the conductive pillar. It is formed not only on the exposed surface of the conductive sleeve 33A but also on the exposed surface of the conductive sleeve 36A. However, the conductive sleeve 36A is attached to the conductive sleeve 33A and the conductive pillar 27B by the etching stopper layer 27.
It is electrically connected by the upper conductive film made of polysilicon or amorphous silicon. In addition, the counter electrode 31 includes the conductive sleeves 33A and 36A.
Is deposited so as to also fill the gap between them.

In this embodiment, the number of conductive sleeves constituting the memory cell capacitor can be increased, and as a result, the area of the capacitor dielectric film, and hence the capacitance, can be increased. Next, a method of manufacturing the capacitor structure of FIG. 7 will be described with reference to FIGS. 8 (A) and (B) and FIGS.
This will be described with reference to FIG. However, in the drawings, the same parts as those described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 8A, a conductive film 34 made of polysilicon or amorphous silicon and an insulating film 35 made of SiO ₂ are formed on the structure shown in FIG.
8B, and anisotropically etching the insulating film 35 in a direction substantially perpendicular to the main surface of the substrate 21 in the step of FIG.
Act until is exposed. As a result of such anisotropic etching, an insulating sleeve 35A is formed from the insulating film 35 so as to surround the conductive film 34 from outside.

Further, in the step of FIG.
Another conductive film 36 made of polysilicon or amorphous silicon is deposited on the structure shown in FIG.
In the step (D), the etching stopper layer 27 performs anisotropic etching on the conductive film 36 and the conductive film 34 thereunder, which acts substantially perpendicularly to the main surface of the substrate 21. By running until exposed, FIG.
The structure of (D) is obtained. In the structure of FIG. 9D, as a result of the anisotropic etching, the conductive film 34 forms a conductive sleeve 34A sandwiched between an insulating sleeve 35A and a conductive sleeve 33A. The outermost conductive sleeve 36A is formed.

The structure shown in FIG. 9D is further immersed in an aqueous HF solution to remove the insulating sleeves 32A and 35A by selective etching. The dielectric film 30 is deposited on the resulting structure, By depositing 31, a capacitor having the structure of FIG. 7 is obtained. [Fifth Embodiment] FIG. 10 is a block diagram of a fifth embodiment of the present invention.
2 shows a part of a RAM memory cell. However, FIG. 10 shows only the configuration of the memory cell capacitor connected to the diffusion region 21C as in the previous embodiment. In addition, the same reference numerals are given to portions corresponding to the portions described above, and description thereof will be omitted.

Referring to FIG. 10, the memory cell capacitor according to the present embodiment has the same configuration as that of the memory cell capacitor of FIG. 7, except that the conductive pillar 27B is a hollow sleeve. Accordingly, the capacitor dielectric film 30 is formed so as to cover not only the outer side wall surface but also the inner side wall surface and the bottom surface of the conductive pillar.
In such a configuration, since the area of the capacitor dielectric film 30 is increased, a preferable feature that the capacitance is increased can be obtained.

FIGS. 11A to 11C and FIG. 12D
(F) shows a method for forming the structure of FIG. However, in the drawings, the same parts as those described above are denoted by the same reference numerals, and description thereof will be omitted. Referring to FIG. 11A, in the present embodiment, contact holes 2 penetrating layers 26 to 28 are formed.
6B, a conductive sleeve 27B is deposited instead of the conductive pillar in the step of FIG. 5A so as to cover the inner wall surface of the contact hole 26 and the surface of the diffusion region 21C exposed at the bottom of the contact hole 26. ,further,
In the step of FIG. 11B, after removing the insulating film 28 by selective etching in HF, the SiO ₂ film 3 is removed.
2 are deposited so as to fill the space inside the conductive sleeve 27B.

Furthermore, in the step of FIG. 11 (C), SiO ₂
Anisotropic etching is performed on the film in a direction substantially perpendicular to the main surface of the substrate 21 until the conductive film 27A is exposed, and the conductive sleeve shown in FIG. 27B is filled with SiO ₂ plug 32C,
Further, a structure in which the outside is covered with an insulating sleeve 32A made of SiO ₂ is obtained.

Next, in the step of FIG.
A conductive film 33 made of polysilicon or amorphous silicon is deposited on the structure shown in FIG.
In the step (E), anisotropic etching is performed on the conductive film 33 in a direction substantially perpendicular to the main surface of the substrate 21 until the etching stopper layer 27 is exposed. The structure shown in (E) in which the conductive sleeve 33A is formed outside the insulating sleeve 32A is obtained.

The structure of FIG. 12E is immersed in an aqueous HF solution to dissolve and remove the SiO ₂ plug 32C and the insulating sleeve 32A, further deposit a capacitor dielectric film 30, and further form a counter electrode 31 thereon. The structure shown in FIG. 12F is obtained by the deposition. FIG.
8 (A), (B), FIG. 9 (C),
By performing the step shown in (D), the number of conductive sleeves surrounding the conductive sleeve 27B and forming the storage electrode together with the conductive sleeve 27B can be arbitrarily increased.

In the third and subsequent embodiments of the present invention, since the conductive film 27A serves as an etching stopper for the insulating film 28, the SiN etching stopper layer 27 is not necessarily required and may be omitted. In the present invention, the interlayer insulating films 24 and 26 are BPSG. However, other planarizing insulating films such as SiO ₂ or polyimide deposited in high-density plasma may be used.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications and changes are possible within the scope of the appended claims. is there.

[0039]

According to the present invention, the method of manufacturing a semiconductor device having a capacitor includes the steps of: (A) forming an insulating film on a substrate;
(B) a step of forming a conductive pillar so as to protrude upward from the insulating film; and (C) a step of depositing a first conductive film on the insulating film so as to cover the conductive pillar. And (D) applying anisotropic etching to the first conductive film substantially perpendicular to the main surface of the substrate to form a capacitor electrode; and (E) forming the capacitor electrode. Depositing a dielectric film on the electrode; and (F) depositing a second conductive film on the dielectric film to form a capacitor, thereby forming a large number of capacitors in a mask. It can be formed in a self-aligned manner, and thus with minimal inter-spacing, without using a process and without the resolution constraints associated with the mask process. Along with this, it is possible to minimize the decrease in the capacitor area and therefore the capacitance due to miniaturization. Further, in the present invention, since a mask process is not used, the throughput in manufacturing a semiconductor device is greatly improved.

According to the fifth and eleventh aspects of the present invention, a step of forming hemispherical polysilicon grains on the electrode pattern is further performed. In the step (E), the dielectric film comprises: By performing so as to cover such hemispherical polysilicon grains, the surface area and capacitance of the formed capacitor can be increased.

According to a sixth aspect of the present invention, a method of manufacturing a semiconductor device having a capacitor includes the steps of: forming an interlayer insulating film on a substrate; Forming a first conductive film; forming a conductive pillar through the conductive film and the interlayer insulating film so as to protrude upward from a surface of the first conductive film; Depositing a first insulating film on the conductive pillar along the shape of the conductive pillar;
Applying a first anisotropic etching, which acts substantially perpendicularly to the main surface of the substrate, to the first insulating film until the top surface of the pillar and the first conductive film are exposed; ,
Forming a first insulating sleeve with the first insulating film; and after the first anisotropic etching step, forming the first insulating sleeve and the pillar on the first conductive film. Depositing a second conductive film so as to cover the top surface of the substrate; and a second anisotropic etching that acts on the second conductive film substantially perpendicularly to the main surface of the substrate. To
Apply until the surface of the interlayer insulating film is exposed,
Forming a first conductive sleeve outside of the insulating sleeve of step (a), removing the first insulating sleeve by selective etching, and removing the pillar and the first conductive sleeve from the first conductive sleeve. Leaving a pillar so as to surround the pillar; and depositing a dielectric film on the surface of the pillar and the surface of the first conductive sleeve; and forming a counter electrode film on the dielectric film. And a step of depositing a third conductive film to form a storage electrode that forms a capacitor without using a masking step, the conductive pillar and a plurality of conductive sleeves surrounding the conductive pillar. It can be configured in a self-aligned manner, and the surface area of the capacitor dielectric film, and hence the capacitance of the capacitor, is greatly increased.

According to the present invention, by forming the pillar as a hollow sleeve, the capacitance of the capacitor can be further increased. According to a feature of the present invention, a fourth conductive film and a second conductive film are formed on the interlayer insulating film after the second anisotropic etching step and before the selective etching step. An insulating film is sequentially deposited so as to include the pillar and the first conductive sleeve and the first insulating sleeve surrounding the pillar, and is disposed on the main surface of the substrate with respect to the second insulating film. Applying a third anisotropic etching that acts substantially perpendicularly to the fourth conductive film until the fourth conductive film is exposed, forming a second insulating sleeve with the second insulating film; On the conductive film of No. 4, so as to include the second insulating sleeve, the fourth conductive film and the pillar,
Depositing a fifth conductive film, and performing an anisotropic etching process on the fifth and fourth conductive films substantially perpendicular to the main surface of the substrate, by exposing the surface of the interlayer insulating film; The second conductive sleeve is formed by the fourth conductive film in close contact with the first conductive sleeve, and the second insulating film is formed by the second insulating film. Forming a second insulating sleeve surrounding the second conductive sleeve, further forming a third conductive sleeve surrounding the second insulating sleeve with the fifth conductive film,
In the selective etching step, by removing the second insulating sleeve substantially simultaneously with the first insulating sleeve, the number of conductive sleeves surrounding the conductive pillar can be reduced without using a masking step. Self-consistently
It becomes possible to increase it freely.

According to a feature of the present invention as set forth in claim 16,
A semiconductor substrate, a word line electrode formed on the surface of the semiconductor substrate with a gate oxide film therebetween corresponding to a channel region, and a second electrode formed in the semiconductor substrate corresponding to one end of the channel region. A second diffusion region formed in the semiconductor substrate corresponding to the other end of the channel region; and a second diffusion region formed on the semiconductor substrate, the gate electrode and the first and second diffusion regions. An interlayer insulating film covering the diffusion region; a first contact hole formed in the interlayer insulating film to expose the first diffusion region; and a second diffusion region formed in the interlayer insulating film. A second contact hole that exposes the first diffusion region, a memory cell capacitor that contacts the first diffusion region through the first contact hole, and the second diffusion hole through the second contact hole. A memory cell capacitor extending in the first contact hole, one end of which contacts the first diffusion region, and the other end of which is the interlayer insulating film. A conductive pillar forming a protrusion protruding on the film; a storage electrode formed on the interlayer insulating film and in close contact with the protrusion of the pillar; and a capacitor dielectric formed to cover the storage electrode. By using a body film and a counter electrode formed on the capacitor dielectric film, a DRAM memory cell in which the capacitance of a memory cell capacitor is small even when miniaturized can be formed without using a mask process. It can be formed in a consistent manner.

[Brief description of the drawings]

FIGS. 1A to 1C are diagrams illustrating the principle of the present invention.

FIGS. 2A to 2D are diagrams (part 1) for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIGS. 3E to 3G are diagrams illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention (part 2); FIGS.

FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5C are diagrams (part 1) for explaining a manufacturing process of a semiconductor device according to a third embodiment of the present invention;

FIGS. 6D to 6F are diagrams (part 2) for explaining a manufacturing process of the semiconductor device according to the third embodiment of the present invention;

FIG. 7 is a diagram showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 8A and 8B are diagrams (part 1) for explaining a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention;

FIGS. 9 (C) and 9 (D) are diagrams (part 2) for explaining a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention;

FIG. 10 is a diagram showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIGS. 11A to 11C are diagrams (part 1) for explaining a manufacturing process of a semiconductor device according to a fifth embodiment of the present invention;

FIGS. 12D to 12F are diagrams (No. 2) illustrating the steps of manufacturing the semiconductor device according to the fifth embodiment of the present invention;

FIGS. 13A to 13C are diagrams (part 1) illustrating a process for manufacturing a conventional semiconductor device.

FIGS. 14 (D) and (E) are diagrams (part 2) illustrating a process for manufacturing a conventional semiconductor device.

FIG. 15 is a plan view showing a shape of a memory cell capacitor formed in a conventional process.

[Explanation of symbols]

1,11,21 substrate 1A, 1B, 1C, 11A, 11B, 21A, 21B,
21C Diffusion region 2,22 Gate oxide film 2A, 22A Field oxide film 3,23 Gate electrode (word line) 3A, 23A Insulation film 4,6,24,26 Interlayer insulation film 5,25 Bit line 6A, 12A, 12B, 26A, 26B Contact hole 7, 13, 29 Conductive layer 7A, 13A, 13B, 29A, 29B Storage electrode pattern 8, 14, 30 Dielectric film 10, 15, 31 Counter electrode 12A, 12B, 27A, 27B Conductive pillar 12C , 27 Etching stopper 28 Insulating film 290 Rough surface structure 32, 35 Insulating film 32A, 35A Insulating sleeve 32C Insulating plug 33, 34, 36 Conductive film 33A, 34A, 36A Conductive sleeve

Claims (16)

[Claims] 1. A method for manufacturing a semiconductor device having a capacitor, comprising: (A) a step of forming an insulating film on a substrate; and (B) a step of forming a conductive pillar so as to protrude upward from the insulating film. (C) depositing a first conductive film on the insulating film so as to cover the conductive pillar; and (D) forming a first conductive film on the first conductive film with respect to a main surface of the substrate. Applying an anisotropic etching that acts substantially vertically,
Forming a capacitor electrode; (E) depositing a dielectric film on the capacitor electrode; and (F) depositing a second conductive film on the dielectric film;
A method of manufacturing a semiconductor device, comprising: forming a capacitor. 2. The method of claim 1, wherein the conductive pillar penetrates the insulating film and makes electrical contact with a diffusion region formed on the substrate. 3. The method according to claim 1, wherein in the step (D), the anisotropic etching is continued until the capacitor electrode is spatially separated from an adjacent capacitor electrode. . 4. Between the step (A) and the step (B),
Further, a step of covering the surface of the insulating film with an etching stopper layer serving as a stopper for etching acting on the insulating film is provided. In the anisotropic etching in the step (D), the etching stopper layer is exposed. The method according to any one of claims 1 to 3, wherein the method is performed until the operation is performed. 5. The method according to claim 1, further comprising the step of forming hemispherical polysilicon particles on the electrode pattern.
5. The method according to any one of claims 1 to 4, wherein the step is performed such that the dielectric film covers such hemispherical polysilicon grains. 6. A method for manufacturing a semiconductor device having a capacitor, comprising: a step of forming an interlayer insulating film on a substrate; a step of forming a first conductive film on the interlayer insulating film; Forming a conductive pillar through the conductive film and the interlayer insulating film so as to protrude upward from the surface of the conductive film; and forming a first insulating film on the conductive pillar, Depositing along the shape of a conductive pillar; and performing a first anisotropic etching on the first insulating film substantially perpendicular to the main surface of the substrate, Applying the first conductive film until the first conductive film is exposed, forming a first insulating sleeve with the first insulating film; and after the first anisotropic etching step, forming the first conductive film. The first insulating sleeve and the pillar on the conductive film. Depositing a second conductive film so as to cover the surface; and performing a second anisotropic etching on the second conductive film substantially perpendicular to the main surface of the substrate; Applying until the surface of the interlayer insulating film is exposed to form a first conductive sleeve outside the first insulating sleeve; removing the first insulating sleeve by selective etching; The first conductive sleeve,
Leaving the first conductive sleeve to surround and surround the pillar; and depositing a dielectric film on the surface of the pillar and the surface of the first conductive sleeve;
Depositing a third conductive film constituting a counter electrode film on the dielectric film. 7. The method according to claim 1, wherein the pillar is formed of a hollow sleeve, and the step of depositing the dielectric film is performed so that the dielectric film also covers an inner wall surface of the hollow sleeve. 6. The method according to 6. 8. After the second anisotropic etching step,
Prior to the selective etching step, a fourth conductive film and a second insulating film are formed on the interlayer insulating film by forming the pillar, the first conductive sleeve surrounding the pillar, and the first insulating film. Sequentially depositing so as to include a sleeve, and performing a third anisotropic etching on the second insulating film substantially perpendicular to the main surface of the substrate by the fourth conductive film. Forming a second insulating sleeve with the second insulating film by applying the film until the film is exposed; and forming the second insulating sleeve and the fourth insulating film on the fourth conductive film.
Depositing a fifth conductive film so as to include the conductive film and the pillar, and acting on the fifth and fourth conductive films substantially perpendicularly to the main surface of the substrate. Anisotropic etching step is sequentially and continuously performed until the surface of the interlayer insulating film is exposed, and the second conductive sleeve adhered to the first conductive sleeve by the fourth conductive film. And forming a second insulating sleeve surrounding the second conductive sleeve with the second insulating film, and forming a third insulating sleeve surrounding the second insulating sleeve with the fifth conductive film. Forming a conductive sleeve, wherein the second insulating sleeve is removed substantially simultaneously with the first insulating sleeve in the selective etching step. the method of. 9. A substrate having a diffusion region formed thereon, an interlayer insulating film formed on the substrate, a contact hole formed in the interlayer insulating film and exposing the diffusion region, Wherein the capacitor extends in the contact hole, and wherein the capacitor contacts the diffusion region.
A conductive pillar having one end in contact with the diffusion region and the other end forming a protrusion projecting from the interlayer insulating film; a storage electrode electrically contacting the protrusion of the conductive pillar; And a counter electrode formed on the capacitor dielectric film. 10. The semiconductor device according to claim 9, wherein an etching stopper layer capable of substantially preventing etching of a material forming the interlayer insulating film is formed on the surface of the interlayer insulating film. 11. The semiconductor device according to claim 9, wherein a surface of said storage electrode has an irregular shape. 12. The conductive pillar according to claim 9, wherein the conductive pillar comprises a hollow sleeve defined by an inner wall surface, and the capacitor dielectric film covers the inner wall surface of the conductive pillar. The semiconductor device according to any one of the above. 13. The semiconductor device according to claim 9, wherein said storage electrode is in close contact with a protrusion of said pillar. 14. The storage electrode includes the conductive pillar itself and one or more conductive sleeves surrounding the conductive pillar, and the capacitor dielectric film includes the conductive pillar protrusion and the one or more conductive sleeves. 10. The semiconductor device according to claim 9, wherein the surface of the conductive sleeve is covered. 15. The conductive pillar and the one or more conductive sleeves are electrically connected to each other via a conductive film formed on a surface of the interlayer insulating film. 13. The semiconductor device according to claim 1. 16. A semiconductor substrate, a word line electrode formed on a surface of the semiconductor substrate with a gate oxide film interposed therebetween corresponding to a channel region, and one end of the channel region in the semiconductor substrate corresponding to one end of the channel region. A first diffusion region formed in the semiconductor substrate, a second diffusion region formed in the semiconductor substrate corresponding to the other end of the channel region, and a second diffusion region formed on the semiconductor substrate; First and second
An interlayer insulating film covering the diffusion region; a first contact hole formed in the interlayer insulating film to expose the first diffusion region; and a second diffusion region formed in the interlayer insulating film. A second contact hole exposing the first contact hole, a memory cell capacitor contacting the first diffusion region through the first contact hole, and a contact with the second diffusion region through the second contact hole In the semiconductor device comprising a bit line electrode, the memory cell capacitor extends in the first contact hole, one end of the memory cell capacitor is in contact with the first diffusion region, and the other end is on the interlayer insulating film. A conductive pillar forming a protruding protrusion, and a storage electrode formed on the interlayer insulating film and in close contact with the protrusion of the pillar,
A semiconductor device comprising: a capacitor dielectric film formed so as to cover the storage electrode; and a counter electrode formed on the capacitor dielectric film.