KR100471136B1 - Line repetition print circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laser beam printer, and more particularly, to a line repeating print circuit of a laser beam printer. The data repeating output unit 210, a memory address generation and boundary detection unit 220, and a control The logic 230 may be used to repeat line printing of image data having an arbitrary boundary, thereby reducing the memory and burden of software.

Description

LINE REPETITION PRINT CIRCUIT}

TECHNICAL FIELD The present invention relates to a laser beam printer, and more particularly, to a line repeating printed circuit of a laser beam printer.

Currently, as an output device used in connection with a computer system, a printer usually prints in a dot method. The printer is used in various ways depending on the printing method. For example, an ink jet printer (generally referred to as an ink jet printer) in which ink is ejected in small droplets and printed. And a laser beam scanning printer (generally referred to as a laser beam printer) for printing by scanning of a laser beam. And printers that print in many other ways are being used.

The resolution of a laser beam printer is expressed in dots per inch (dpi) in the same way as the resolution of a general printer. dpi indicates how many dots are printed within 1 inch. When the image data generated by the host is 600 dpi data, the same line must be printed twice in order to print with a 300 dpi engine. In addition, a 150dpi engine requires four prints. If you want to support this in software, you need twice as much memory, which puts a strain on the software. In order to solve this problem, a line repeating printed circuit has been proposed.

1 is a circuit diagram of a line repeating printed circuit in a conventional laser beam printer.

As shown in FIG. 1, the conventional line repeating print circuit includes a data repeating output unit 110, a memory address generating unit 120, and a control logic 130. The data repeating output unit 110 includes a shift register 111, a line dot counter 113, and a line dot counter register 115. do. The memory address generator 120 includes a line counter 121, an address buffer register 124, a multiplexer 125, an address register 126, A next address generator 127, a NOR gate 122, and an end gate 123 are included.

The memory address generator 120 generates a corresponding data address of a memory (not shown) in which print data is stored, and the data repeating output unit 210 transmits data stored in the memory through a data bus. Receives an input and repeats it for the corresponding number of times This series of operations proceeds sequentially according to the control signal generated by the control logic 130.

However, the conventional line repeating print circuit as described above reduces the memory and software burden to some extent, but does not obtain a great effect. In particular, when the laser beam printer does not have a line repeat printing function, even if a dot to be printed in any boundary ends, printing continues on the next line, and thus no problem occurs. However, when the line repeating printing function is provided as described above, a line dot size must be correct in units of Byte, Half Word, and Word, but a problem has not occurred. Therefore, in order to overcome this problem, conventionally, only the remaining part has to be filled with dummy data.

Accordingly, an object of the present invention is to provide a line repetitive print circuit capable of line repetitive printing on image data having any boundary as proposed to solve the above-mentioned problems.

According to a feature of the present invention for achieving the object of the present invention as described above, a line repeating print circuit for printing an image of a higher resolution than the resolution supported by the printer: A data repetition output unit for repeatedly outputting input image data corresponding to the resolution of the image when data is input; A memory address generation and boundary detection unit which sequentially generates an address of a memory in which the image data is stored, and detects a boundary of the image and outputs a plurality of control signals; A control logic for inputting a plurality of control signals to the memory address generation and boundary detection unit, and inputting a plurality of control signals generated according to the boundary detection from the memory address generation and boundary detection unit and controlling the data repetition output unit in response thereto Including the line repeating for the image having any boundary.

In this embodiment, the data repeat output unit comprises: a buffer for latching the image data; A multiplexer for selectively outputting between the input of the image data and the input of the buffer; And a shift register configured to input and output an output of the multiplexer.

In this embodiment, the memory address generation and boundary detection unit includes: a dot unit counter for counting the number of dots of a print line and outputting the dot number as a first signal when an overflow occurs; A one-bit register reset to said first signal and outputting a second signal in synchronization with a line synchronization signal provided from said control logic; A line counter that counts in synchronization with the output of the synchronization signal; And a logic circuit configured to NAND-operate the count result of the line counter to output a third signal, wherein the control logic outputs a plurality of control signals in response to input of the first to third signals to correspond to an arbitrary boundary. Perform line repeat print.

According to the present invention as described above, line repetition printing is possible for image data having arbitrary boundaries, which reduces the memory and the software burden.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a line repeating printed circuit of a laser beam printer according to an embodiment of the present invention.

As shown in FIG. 2, the novel line repeat print circuit of the present invention largely includes a data repeat output unit 210, a memory address generation and boundary detection unit 220, and control logic 230.

The data repeating output unit 210 includes a buffer 211, a first multiplexer 213, and a shift register 215. The buffer 211 stores data provided from the data bus. The mux 213 inputs data from the buffer 211 and the data bus, respectively, and selectively shifts the shift register 215 in response to an input of the first selection signal Select1 provided from the control logic 230. ) The shift register 215 shifts and outputs the input data in response to the first write signal Write1 provided from the control logic 230.

The memory address generation and boundary detection unit 220 includes a dot unit counter 221, a 1 bit register 222, a line counter 223, and an address. An address buffer buffer 226, a second multiplexer 227, an address register 228, a next address generator 229, and a NOR gate. 224 and an AND gate 225.

The dot unit counter 221 receives a dot clock from the control logic 230 and counts the signal. When the overflow occurs, a signal 1 is generated and provided to the control logic 230. The counter signal is cleared by receiving a clear signal from the control logic 230.

The 1-bit register 222 is configurable as a D flip-flop, and the input terminal is pulled-up to the power supply voltage VDD. The signal is reset according to the output of Signal1 and outputs Singal2 to the control logic 230 in synchronization with the input of the line synchronization signal LSync provided from the control logic 230.

The line counter 223 performs counting in synchronization with the line synchronization signal LSync, and a counting result is input to the NAND gate 224 to perform an NAND operation to output a Signal3. This is input to the control logic 230. The end gate 225 inputs the output of the NAND gate 224 and the line synchronization signal LSync to perform an end operation, and outputs the result to the address buffer register 226.

The second multiplexer 227 inputs an output of the address buffer register 226 and an output of the subsequent address generator 229, and inputs a second select signal Select2 provided from the control logic 230. Responsive to the address register 228. The address register 228 outputs an address of a memory in which data to be printed is stored. The subsequent address generator 229 inputs the output of the address register 228 to generate an address of a subsequent memory in which data to be printed is stored.

The control logic 230 inputs Signal1, Signal2, and Signal3 provided from the memory address generation and boundary detector 220 to detect boundaries of an image to be currently printed and output a plurality of control signals.

The operation of the line repeating printed circuit according to the embodiment of the present invention as described above is as follows.

The buffer 211 stores the data input to the shift register 213 in the same manner. When counting of the line counter 223 is completed for the first line, the last data is latched. In this case, when the dot unit counter 221 overflows and the signal 1 is generated, the data latched in the buffer 211 is not used. The Select2 signal allows the first repeated data of the next line to be taken from the buffer. Signal2 also represents the first data section of the repeating line. The dot clock is a clock for determining the dot ratio of the print data, and the clear signal is a signal for returning to the original state when the first line of the printed page is printed. Signal3 represents the last line of the repeating line, allowing this signal to latch the last data of all lines. Since the number of dots of one line in a page to be printed is constant, a separate buffer for the dot unit counter 221 is not required to be provided and is used for each line.

According to the present invention as described above, it is possible to repeat line printing on image data having an arbitrary boundary, thereby reducing the memory and the burden of software.

1 is a circuit diagram of a line repeating printed circuit in a conventional laser beam printer;

2 is a circuit diagram of a line repeating printed circuit of a laser beam printer according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110, 210: data repeat output unit 120, 220: memory address generator

130, 230: control logic

Claims (3)

In a line-repeated print circuit for printing images with higher resolution than the printer supports: A data repetition output unit 210 which repeatedly outputs input image data corresponding to the resolution of the image when data of an image having a resolution higher than that supported by the printer is input; A memory address generation and boundary detection unit 220 sequentially generating an address of a memory in which the image data is stored, and detecting a boundary of the image and outputting a plurality of control signals; Input a plurality of control signals to the memory address generation and boundary detection unit 220, input a plurality of control signals generated in response to the boundary detection from the memory address generation and boundary detection unit 220 and repeat the data in response thereto A line repeating print circuit comprising line repeating printing on an image having an arbitrary boundary, including control logic (230) for controlling the output unit (210). The method of claim 1, The data repeat output unit 210 A buffer 211 for latching the image data; A multiplexer (213) for selectively outputting between the input of the image data and the input of the buffer (211); And a shift register (215) for inputting and outputting the output of the multiplexer (213). The method of claim 1, The memory address generation and boundary detection unit 220 A dot unit counter 221 which counts the number of dots of the print line and outputs it as a first signal Signal1 when an overflow occurs; A one-bit register 222 reset to the first signal Signal1 and outputting a second signal Signal2 in synchronization with the line synchronization signal LSync provided from the control logic 230; A line counter 223 for counting in synchronization with the output of the synchronization signal LSync; A logic circuit 224 for NAND-operating the count result of the line counter 223 to output a third signal Signal3; The control logic 230 outputs a plurality of control signals in response to the input of the first to third signals Signal1 to Signal3 to perform line repetition printing corresponding to an arbitrary boundary. Printed circuit.

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