KR100470516B1 - 분포된태그캐시메모리시스템및그것에데이터를저장하기위한시스템 - Google Patents

분포된태그캐시메모리시스템및그것에데이터를저장하기위한시스템 Download PDF

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KR100470516B1
KR100470516B1 KR1019970059183A KR19970059183A KR100470516B1 KR 100470516 B1 KR100470516 B1 KR 100470516B1 KR 1019970059183 A KR1019970059183 A KR 1019970059183A KR 19970059183 A KR19970059183 A KR 19970059183A KR 100470516 B1 KR100470516 B1 KR 100470516B1
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South Korea
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instruction
cache
tag
loop
array
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KR1019970059183A
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Korean (ko)
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KR19980042269A (ko
Inventor
윌리암 씨. 모에르
레황 리
죤 아르엔즈
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
KR1019970059183A 1996-11-14 1997-11-11 분포된태그캐시메모리시스템및그것에데이터를저장하기위한시스템 Expired - Fee Related KR100470516B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8/748,856 1996-11-11
US08/748,856 1996-11-14
US08/748,856 US5920890A (en) 1996-11-14 1996-11-14 Distributed tag cache memory system and method for storing data in the same

Publications (2)

Publication Number Publication Date
KR19980042269A KR19980042269A (ko) 1998-08-17
KR100470516B1 true KR100470516B1 (ko) 2005-05-19

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KR1019970059183A Expired - Fee Related KR100470516B1 (ko) 1996-11-14 1997-11-11 분포된태그캐시메모리시스템및그것에데이터를저장하기위한시스템

Country Status (3)

Country Link
US (1) US5920890A (https=)
JP (1) JPH10232830A (https=)
KR (1) KR100470516B1 (https=)

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US5983310A (en) * 1997-02-13 1999-11-09 Novell, Inc. Pin management of accelerator for interpretive environments
US6662216B1 (en) * 1997-04-14 2003-12-09 International Business Machines Corporation Fixed bus tags for SMP buses
US6247098B1 (en) * 1998-02-17 2001-06-12 International Business Machines Corporation Cache coherency protocol with selectively implemented tagged state
US6519684B1 (en) * 1999-11-23 2003-02-11 Motorola, Inc. Low overhead method for selecting and updating an entry in a cache memory
JP2001195302A (ja) * 1999-11-30 2001-07-19 Texas Instr Inc <Ti> 命令ループ・バッファ
US6963965B1 (en) 1999-11-30 2005-11-08 Texas Instruments Incorporated Instruction-programmable processor with instruction loop cache
US6950929B2 (en) * 2001-05-24 2005-09-27 Samsung Electronics Co., Ltd. Loop instruction processing using loop buffer in a data processing device having a coprocessor
US20040088682A1 (en) * 2002-11-05 2004-05-06 Thompson Ryan C. Method, program product, and apparatus for cache entry tracking, collision detection, and address reasignment in processor testcases
US8386712B2 (en) * 2006-10-04 2013-02-26 International Business Machines Corporation Structure for supporting simultaneous storage of trace and standard cache lines
US7934081B2 (en) * 2006-10-05 2011-04-26 International Business Machines Corporation Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
US20080250206A1 (en) * 2006-10-05 2008-10-09 Davis Gordon T Structure for using branch prediction heuristics for determination of trace formation readiness
JP2010066892A (ja) * 2008-09-09 2010-03-25 Renesas Technology Corp データプロセッサ及びデータ処理システム
KR101645003B1 (ko) * 2010-02-12 2016-08-03 삼성전자주식회사 메모리 제어기 및 그 메모리 제어기가 탑재된 컴퓨팅 장치
JP2012221086A (ja) * 2011-04-06 2012-11-12 Fujitsu Semiconductor Ltd 情報処理装置
US9183155B2 (en) 2013-09-26 2015-11-10 Andes Technology Corporation Microprocessor and method for using an instruction loop cache thereof
US10423423B2 (en) 2015-09-29 2019-09-24 International Business Machines Corporation Efficiently managing speculative finish tracking and error handling for load instructions
US10180839B2 (en) * 2016-03-04 2019-01-15 Silicon Laboratories Inc. Apparatus for information processing with loop cache and associated methods
US20240385944A1 (en) * 2023-05-19 2024-11-21 Zoho Corporation Private Limited Concurrency-enabled loop constructs using state variable mutation principle

Citations (6)

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Publication number Priority date Publication date Assignee Title
KR870011536A (ko) * 1986-05-02 1987-12-24 원본미기재 변환색인 버퍼 셧다운 기구
JPH04127339A (ja) * 1990-09-19 1992-04-28 Hitachi Ltd キヤツシユメモリシステム
JPH0512119A (ja) * 1991-07-04 1993-01-22 Nec Corp キヤツシユメモリ回路
JPH07160577A (ja) * 1993-12-10 1995-06-23 Matsushita Electric Ind Co Ltd キャッシュメモリ制御装置
JPH09160828A (ja) * 1995-12-06 1997-06-20 Fujitsu Ltd 多重アクセス方法および多重アクセスキャッシュメモリ装置
KR100350567B1 (ko) * 1994-08-22 2002-12-18 모토로라 인코포레이티드 캐시태그랜덤액세스메모리및,그메모리에서의다수의유효비트무효화방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763253A (en) * 1986-09-26 1988-08-09 Motorola, Inc. Microcomputer with change of flow
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
JPH06243036A (ja) * 1993-02-12 1994-09-02 Hitachi Ltd キャッシュ制御システム
US5510934A (en) * 1993-12-15 1996-04-23 Silicon Graphics, Inc. Memory system including local and global caches for storing floating point and integer data

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR870011536A (ko) * 1986-05-02 1987-12-24 원본미기재 변환색인 버퍼 셧다운 기구
JPH04127339A (ja) * 1990-09-19 1992-04-28 Hitachi Ltd キヤツシユメモリシステム
JPH0512119A (ja) * 1991-07-04 1993-01-22 Nec Corp キヤツシユメモリ回路
JPH07160577A (ja) * 1993-12-10 1995-06-23 Matsushita Electric Ind Co Ltd キャッシュメモリ制御装置
KR100350567B1 (ko) * 1994-08-22 2002-12-18 모토로라 인코포레이티드 캐시태그랜덤액세스메모리및,그메모리에서의다수의유효비트무효화방법
JPH09160828A (ja) * 1995-12-06 1997-06-20 Fujitsu Ltd 多重アクセス方法および多重アクセスキャッシュメモリ装置

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Publication number Publication date
US5920890A (en) 1999-07-06
KR19980042269A (ko) 1998-08-17
JPH10232830A (ja) 1998-09-02

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