KR100470124B1 - Method for manufacturing silicide anneal block layer/shallow trench isolation block layer of semiconductor device - Google Patents
Method for manufacturing silicide anneal block layer/shallow trench isolation block layer of semiconductor device Download PDFInfo
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- KR100470124B1 KR100470124B1 KR10-2002-0053615A KR20020053615A KR100470124B1 KR 100470124 B1 KR100470124 B1 KR 100470124B1 KR 20020053615 A KR20020053615 A KR 20020053615A KR 100470124 B1 KR100470124 B1 KR 100470124B1
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- block layer
- trench isolation
- shallow trench
- silicide anneal
- nitride
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- 238000002955 isolation Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 26
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자(semiconductor device)의 제조 공정에 있어서 실리사이드 어닐 블록층(silicide anneal block layer)과 샐로우 트렌치 아이솔레이션 블록층(shallow trench isolation block layer)을 동시에 형성하는 방법에 관한 것이다. 본 발명은 측벽(side wall) 형성을 위해 나이트라이드 식각(nitride etch) 시 콘택(contact) 근처의 위크 디자인 룰(weak design rule) 지역 즉, 샐로우 트렌치 아이솔레이션 영역의 표면에 샐로우 트렌치 아이솔레이션 블록층을 형성시켜 콘택 형성 시 문제되는 IDDQ 리키지 페일을 개선하고 콘택 저항을 개선함으로써 웨이퍼 수율이 향상되는 효과가 있다.The present invention relates to a method of simultaneously forming a silicide anneal block layer and a shallow trench isolation block layer in a manufacturing process of a semiconductor device. The present invention provides a shallow trench isolation block layer on the surface of a weak design rule region near the contact during the nitride etch, that is, the shallow trench isolation region, for forming side walls. By improving the contact resistance by forming an IDDQ solution fail to form a contact and improve the contact resistance there is an effect that the wafer yield is improved.
Description
본 발명은 반도체 소자(semiconductor device)의 실리사이드 어닐 블록층(silicide anneal block layer)과 샐로우 트렌치 아이솔레이션 블록층(shallow trench isolation block layer) 제조 방법에 관한 것으로, 특히, 반도체 소자의 제조 공정에 있어서 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층을 동시에 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicide anneal block layer and a shallow trench isolation block layer of a semiconductor device, and more particularly, to a silicide in a manufacturing process of a semiconductor device. A method of simultaneously forming an anneal block layer and a shallow trench isolation block layer.
반도체 소자의 집적화에 따른 공정 마진(process margin) 및 소자 특성의 중요성이 더욱 대두되고 있으며 이러한 소자 오동작의 가장 큰 원인 중의 하나가 리키지(leakage)이다.Process margins and device characteristics are becoming more important due to the integration of semiconductor devices, and one of the biggest causes of such device malfunctions is leakage.
반도체 소자의 집적화에 따른 콘택(contact)과 샐로우 트렌치 아이솔레이션 사이의 마진이 제로 마진(zero margin)에 가까워 콘택 패턴(contact pattern) 형성 시 미스-얼라인(mis-align)이 불가피하게 발생된다.Since the margin between contact and shallow trench isolation due to the integration of semiconductor devices is close to zero margin, misalignment occurs inevitably when forming a contact pattern.
콘택 식각(contact etch) 시 이를 보완하기 위한 목적으로 산화막과 선택비가 좋은 나이트라이드(nitride)를 실리사이드 한 후 얇게 형성시켜 PMD(PSG/BPSG)와 버퍼(buffer) 역할 및 콘택 식각 시 고 선택비를 이용한 블록층으로 사용하고 있다.In order to compensate for contact etch, an oxide layer and a nitride having a good selectivity are silicided and then thinly formed to form a PMD (PSG / BPSG), a buffer, and a high selectivity at the time of contact etching. It is used as the used block layer.
문제는 PMD 라이너 나이트라이드(liner nitride) 두께가 너무 얇아 콘택 식각 시 선택비가 높지 않고 미스-얼라인이 발생하였을 경우 오버 식각(over etch)에 의한 샐로우 트렌치 아이솔레이션 필드 옥사이드 스파이킹(shallow trench isolation field oxide spiking) 현상이 발생한다.The problem is that the shallow trench isolation field caused by over etch when the PMD liner nitride thickness is too thin and the selectivity is not high during contact etching and miss-alignment occurs. oxide spiking) occurs.
이는 IDDQ 페일(fail)과 같은 치명적인 수율 저하(yield drop)의 원인이 되기도 한다.This can also cause fatal yield drops such as IDDQ failures.
PMD 라이너 두께를 두껍게 하는 것도 하나의 방법이지만 다른 특성에 영향을 줄 수 있고 콘택 식각 시 작은 홀 보텀(hole bottom)에 있는 나이트라이드를 클리어(clear)하게 제거하는 것도 쉽지 않다.Thickening the PMD liner thickness is one method, but it can affect other properties and it is not easy to clear the nitride at the small hole bottom during contact etching.
콘택 저항 관련 보텀층의 나이트라이드를 제거하기 위해 산화막과 선택비가 좋은 CH2F2 등의 가스를 사용하기는 하지만 CD가 작아지고 애스펙트 레이쇼(aspect ratio)가 커지면서 홀 보텀 폴리머(hole bottom polymer) 및 나이트라이드를 제거하는데도 많은 어려움이 있다.Although oxides and gases such as CH2F2 with good selectivity are used to remove the nitrides of the contact resistance-related bottom layer, hole bottom polymers and nitrides are reduced as the CD becomes smaller and the aspect ratio becomes larger. There are also many difficulties in eliminating it.
상기한 바에 의하여 안출된 본 발명은, 게이트 영역 표면의 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 영역 표면의 샐로우 트렌치 아이솔레이션 블록층을 동시에 형성함으로써, 공정을 간소화시킴과 아울러 콘택 미스-얼라인으로 인한 샐로우 트렌치 아이솔레이션 스파이킹 현상을 방지하여 리키지 소스(leakage source) 부분을 완화하는 데 그 목적이 있다.본 발명의 다른 목적은 시키는데 샐로우 트렌치 아이솔레이션 블록층을 나이트라이드로 형성하여 종래 기술에 의한 후속의 PMD 라이너 나이트라이드 공정을 PMD 라이너 산화막 공정으로 대체하여 콘택 저항을 개선하는 데 있다.The present invention devised by the above-described method, by simultaneously forming a silicide anneal block layer on the gate region surface and a shallow trench isolation block layer on the surface of the shallow trench isolation region, simplifies the process and is caused by contact miss-alignment. Its purpose is to mitigate leaky source portions by preventing shallow trench isolation spikes. Another object of the present invention is to form a shallow trench isolation block layer by nitride and Subsequent PMD liner nitride processes are replaced with PMD liner oxide processes to improve contact resistance.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층 제조 방법의 일 실시예를 공정 단계별로 나타낸 단면도.1A to 1D are cross-sectional views showing one embodiment of a method for manufacturing a silicide anneal block layer and a shallow trench isolation block layer of a semiconductor device according to the present invention.
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층 제조 방법의 일 실시예를 공정 단계별로 나타낸 단면도이다.1A to 1D are cross-sectional views illustrating one embodiment of a method of manufacturing a silicide anneal block layer and a shallow trench isolation block layer of a semiconductor device according to the present invention.
먼저, 도 1a와 같이 상측 특정 영역에 샐로우 트렌치 아이솔레이션이 형성되고 표면에 게이트가 선택적으로 형성된 전 표면에 나이트라이드가 형성된 기판에 있어서, 형성될 콘택에 인접한 게이트 영역의 나이트라이드 표면에 실리사이드 어닐 블록층을 패터닝하고 샐로우 트렌치 아이솔레이션 영역의 나이트라이드 표면에 샐로우 트렌치 아이솔레이션 블록층을 패터닝한다. 여기서 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층은 나이트라이드로 형성한다.First, in a substrate in which shallow trench isolation is formed in an upper specific region and nitride is formed on an entire surface on which a gate is selectively formed on a surface, as shown in FIG. 1A, a silicide anneal block is formed on a nitride surface of a gate region adjacent to a contact to be formed. The layer is patterned and the shallow trench isolation block layer is patterned on the nitride surface of the shallow trench isolation region. The silicide anneal block layer and the shallow trench isolation block layer are formed of nitride.
도 1b와 같이 식각 공정을 수행하여 게이트 영역과 샐로우 트렌치 아이솔레이션 영역 및 기판 표면에 형성된 나이트라이드 중에서 게이트에 측벽으로 형성된 나이트라이드를 제외한 나머지 나이트라이드를 모두 제거한다. 여기서 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층도 함께 식각되는데, 기판 표면이 노출될 때에 식각을 정시시키면 잔존하는 실리사이드 어닐 블록층과 샐로우 트렌치 아이솔레이션 블록층이 게이트 영역 표면 및 샐로우 트렌치 아이솔레이션 영역 표면에 각각 형성된다. 이때, 식각 공정의 환경에 의해 게이트의 측벽으로 형성된 나이트라이드의 두께와 실리사이드 어닐 블록층의 두께, 샐로우 트렌치 아이솔레이션 블록층의 두께는 1000 내지 1300Å로서 모두 동일하게 된다.The etching process is performed as shown in FIG. 1B to remove all nitrides except nitrides formed as sidewalls of the gate from the nitrides formed on the gate region, the shallow trench isolation region, and the substrate surface. Here, the silicide anneal block layer and the shallow trench isolation block layer are also etched. When the etching is performed when the substrate surface is exposed, the remaining silicide anneal block layer and the shallow trench isolation block layer are formed on the gate region surface and the shallow trench isolation region. It is formed on the surface respectively. At this time, the thickness of the nitride formed on the sidewall of the gate, the thickness of the silicide anneal block layer, and the thickness of the shallow trench isolation block layer are the same as those of the etching process.
도 1c와 같이 전 표면에 PMD 라이너 산화막을 형성한다. 즉, 종래 기술에서 후속으로 수행하던 PMD 라이너 나이트라이드 공정을 PMD 라이너 산화막 공정으로 대체한다. 앞 공정에서 샐로우 트렌치 아이솔레이션 영역에 나이트라이드 블록층이 이미 형성되어 있으므로 위 PMD 라이너 산화막은 단지 버퍼층 역할만 수행한다.A PMD liner oxide film is formed on the entire surface as shown in FIG. 1C. That is, the PMD liner nitride process, which is subsequently performed in the prior art, is replaced with the PMD liner oxide film process. In the previous process, since the nitride block layer is already formed in the shallow trench isolation region, the PMD liner oxide layer serves only as a buffer layer.
도 1d와 같이 전 표면에 PMD(PSG/BPSG)를 형성하는 등의 공정을 수행한 후 선택적으로 콘택홀을 형성한다.After forming a PMD (PSG / BPSG) on the entire surface as shown in Figure 1d and selectively forming a contact hole.
상기 두 블록층을 나이트라이드로 측벽 두께인 1000 내지 1300Å의 두께로 형성하기 때문에, 콘택 식각 시 충분한 마진을 가질 수 있고 PMD 라이너를 굳이 나이트라이드로 하지 않아도 된다. 따라서, PMD 라이너를 산화막으로 사용할 수 있기 때문에, 추가로 콘택 식각 시 나이트라이드 식각 공정이 필요없으므로 코스트 세이브(cost save)의 효과가 있다.Since the two block layers are formed of nitride to a thickness of 1000 to 1300 mm, the sidewalls may have sufficient margin when etching the contact, and the PMD liner does not have to be nitrided. Therefore, since the PMD liner can be used as the oxide film, since the nitride etching process is not necessary at the time of contact etching, there is an effect of cost saving.
이상에서 설명한 바와 같이, 본 발명은 측벽 형성을 위해 나이트라이드 식각 시 콘택 근처의 위크 디자인 룰(weak design rule) 지역 즉, 샐로우 트렌치 아이솔레이션 영역의 표면에 샐로우 트렌치 아이솔레이션 블록층을 형성시켜 콘택 형성 시 문제되는 IDDQ 리키지 페일을 개선하고 콘택 저항을 개선함으로써 웨이퍼 수율이 향상되는 효과가 있다. 콘택 패턴 형성 시에도 보텀 CD에 대한 충분한 마진을 가질 수 있는 장점이 있다. 콘택 형성 시 PMD 나이트라이드층을 제거하기 위한 가스의 사용이 필요없다. 실리사이드 어닐 블록층 공정을 별도로 추가하지 않고도 샐로우 트렌치 아이솔레이션 블록층의 형성 시 실리사이드 어닐 블록층을 동시에 형성시키므로 공정이 간소화 되고 원가가 절감되는 효과가 있다. 아울러, 별도의 실리사이드 어닐 블록층 공정을 진행하지 않기 때문에, 별도의 실리사이드 어닐 블록층 공정에 필요한 산화막 증착 및 애싱(ashing), 클리닝(cleaning) 공정까지 스킵시킬 수 있다.As described above, the present invention forms a contact trench isolation layer by forming a shallow trench isolation block layer on a surface of a weak design rule region, that is, a shallow trench isolation region, in the vicinity of a contact during etching of nitride to form sidewalls. The wafer yield can be improved by improving IDDQ leakage fail and improving contact resistance. Even when forming the contact pattern, there is an advantage of having sufficient margin for the bottom CD. There is no need to use a gas to remove the PMD nitride layer during contact formation. Without the addition of the silicide anneal block layer process, the silicide anneal block layer is simultaneously formed when the shallow trench isolation block layer is formed, thereby simplifying the process and reducing the cost. In addition, since the separate silicide anneal block layer process is not performed, the oxide film deposition, ashing, and cleaning processes required for the separate silicide anneal block layer process may be skipped.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0314241A (en) * | 1989-06-13 | 1991-01-22 | Sharp Corp | Manufacture of semiconductor device |
| KR970072203A (en) * | 1996-04-24 | 1997-11-07 | 김광호 | Polycide gate formation method |
| JP2001085683A (en) * | 1999-09-10 | 2001-03-30 | Denso Corp | Semiconductor device and its manufacturing method |
| KR20020010795A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Manufacturing method for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0314241A (en) * | 1989-06-13 | 1991-01-22 | Sharp Corp | Manufacture of semiconductor device |
| KR970072203A (en) * | 1996-04-24 | 1997-11-07 | 김광호 | Polycide gate formation method |
| JP2001085683A (en) * | 1999-09-10 | 2001-03-30 | Denso Corp | Semiconductor device and its manufacturing method |
| KR20020010795A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Manufacturing method for semiconductor device |
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