KR100467581B1 - Velocity measurement apparatus and method using quantization error - Google Patents

Abstract

The present invention relates to a speed measuring device and a method using the quantization error, and more particularly, to obtain the optimal reference clock frequency and the number of output bits of the counter from the maximum and minimum speed measurable, and to measure the speed using the same An apparatus and a method thereof are provided.

To this end, the present invention aims to measure the speed during every pulse generated by the encoder 100 according to a predetermined interrupt signal or at a predetermined number of pulse intervals determined by the counter 1 (130). The fixed frequency generated by the clock generator 120 counts the number of reference clocks through the reference clock scaler 170, receives the counted reference clock and the counted encoder pulses, and calculates the speed of the motor in the controller 160. In the speed measuring apparatus, the reference clock of the fixed frequency is input from the reference clock generator 120 to scale the frequency of the reference clock to satisfy the limit condition of the quantization error to the second counter 50. Characterized in that it further comprises a reference clock scaler 170 to deliver.

Description

Velocity measurement apparatus and method using quantization error

The present invention relates to a speed measuring device and a method using the quantization error, and more particularly, to obtain the optimal reference clock frequency and the number of output bits of the counter from the maximum and minimum speed measurable, and to measure the speed using the same An apparatus and a method thereof are provided.

The process of converting an analog signal into a digital signal is called simply A / D (Analog / Digital) conversion. The key to this A / D conversion process is to split the continuous signal into a certain unit of time and to step the magnitude of the signal in each unit. This process of discretely sizing the magnitudes of the sampled signal is called quantization. As the continuous signal is stepped as described above, an error occurs to some extent. The error between the original signal and the quantized signal is called a quantization error. That is, in order to prevent distortion of the original signal in the process of converting an analog signal, which is a motor rotation speed, into a digital encoder signal, it is necessary to maintain an appropriate level of quantization error by adjusting the number of digital levels to be quantized according to the nature and state of the signal. There is.

1 is a view showing the components of a conventional speed detection apparatus using the above-described encoder. Referring to FIG. 1, a conventional apparatus for measuring a motor speed includes an encoder 10 for generating an encoder pulse, a sampling time counter 20 for generating a speed control period Ts, and the encoder pulse. And an AND gate 60 which multiplies the output of the sampling time counter 20 to generate an interrupt signal every predetermined period, and a reference clock generator 30 which generates a reference clock for counting the interval between the encoder pulses. And counting the number of encoder pulses (m1) output from the encoder (10), and transmitting the number (m1) of the encoder pulses to the controller (70) according to the interrupt signal and again from the beginning of the encoder pulses. The first counter 40 to count the number and the number (m2) of the reference clock, and the number (m2) of the encoder pulse in accordance with the interrupt signal to the control unit 70 and the first part Control unit 70 for measuring the speed based on the second counter 50 for counting the number of the reference clock and the number of encoder pulses (m1) and the number of the reference clock (m2) transmitted according to the interrupt signal It consists of).

Hereinafter, the speed measurement process will be described in detail with reference to FIGS. 1 and 2.

1 and 2, the encoder 10 according to the present invention generates an encoder pulse train in accordance with the rotation of the motor, the first counter 40 counts the pulse train of the encoder 10 When the interrupt signal (INT) generated by multiplying the 'count pull' signal and the encoder pulse of the sampling time counter 20 is generated, the counted value m1 is transmitted to the controller 70, and the encoder pulse is transmitted again from the beginning. Count. The interrupt signal is generated when the speed sampling period (Ts) ends and the first encoder pulse is input.

The sampling time counter 20 is a counter for generating the speed control period Ts. When the count reaches a predetermined count value, the sampling time counter 20 generates a 'count pull' signal and starts counting again from the beginning. 30 continues to generate the reference clock, and the second counter 50 counts the reference clock. The interrupt signal INT generated by performing a logical multiplication of the 'count pull' signal and the encoder pulse of the sampling time counter 20. When is generated, the counted value m2 is transmitted to the controller 70 and the reference clock is counted again from the beginning.

The control unit 70 has the number of encoders (m1) and the reference clock (m2) received from the first counter 40 and the second counter 50 and the speed of the motor based on the following equations (1) to (3): w) is measured.

w = dx / dt = Fref × L / m2 (for strip encoder)

Here, ppr is the number of pulses generated per revolution of the encoder 10, and Fref refers to the reference clock frequency.

However, in the prior art, since the reference clock frequency is fixed, it is not possible to actively cope with the speed change of the encoder. That is, there is no reference to the optimal reference clock frequency selection and the reference of the number of bits in the output counter that limit the quantization error to the value of a given level for the maximum and minimum speeds of the measurable motor relative to the reference clock. .

In addition, in Japanese Patent Application Laid-Open No. Hei 8-032425, when a data signal is read by an identification clock signal, a DC bias current of an external clock inputted to a comparator for generating an internal clock is changed or a reference voltage is applied. A data read timing variable circuit for changing a read timing of data by varying and generating a phase shifted internal clock is disclosed. Also, Korean Patent Laid-Open No. 1999-032133 measures the displacement generated by the rotation of a drum to accelerate the displacement. A rotor speed control state inspection apparatus is disclosed, which makes it possible to check the speed control state of a drum from the converted data by FFT-converting acceleration data, and Japanese Patent Laid-Open No. 09-281125 discloses First signal processing means to which an output signal is input, a control unit connected to each series, a current rectifier, and a low pass Filter, the second signal processing but is a rotational speed measuring device disclosed consists of a means or the like, which method also does not guarantee that in the quantization error a measurement error given.

The present invention has been made to solve the above problems, the reference clock frequency selection and the number of bits of the output counter for satisfying the quantization error constraints for the maximum and minimum speed of the measurable motor with respect to the reference clock It is an object of the present invention to provide an apparatus and method for measuring a differential amount such as the speed of a motor by providing a.

1 is a block diagram for measuring the speed according to the prior art,

2 is a view for explaining the input-output relationship of the main components shown in FIG.

3 is a block diagram for speed measurement according to the present invention.

<Explanation of symbols for the main parts of the drawings>

140: second counter

160: control unit

170: reference clock scaler

According to an embodiment of the present invention to achieve the above object, the present invention counts the reference clock of the reference clock generator 120 in the first counter 130 in accordance with a predetermined interrupt signal, the encoder 100 is In the speed measuring device for counting the encoder pulse generated in accordance with the rotation of the motor in the second counter 140 to receive the counted reference clock and the counted encoder pulse to calculate the speed of the motor in the control unit 160, The reference clock scaler 170 which receives the reference clock of a fixed frequency from the reference clock generator 120 and scales the frequency of the reference clock to satisfy the constraint condition of the quantization error and transmits the frequency of the reference clock to the second counter 50. It further comprises a).

Preferably, the number of output bits of the second counter 140 is adjustable by a program.

Preferably, the control unit 160 further includes calculating the number of output bits of the second counter 140 to program the second counter 140 so as to satisfy the constraint of the given quantization error. do.

According to another embodiment of the present invention, there is provided a speed measurement method using a quantization error. The reference clock of the reference clock generator 120 is counted by the first counter 130 according to a predetermined interrupt signal, and the encoder 100 is counted. ) Counts encoder pulses generated by the rotation of the motor at the second counter 140 and receives the counted reference clock and the counted encoder pulses to calculate the speed of the motor in the controller 160. In this case, the frequency of the reference clock is obtained by the formula Fref = (B x Vmax) / L so as to satisfy the limitation condition of the quantization error, and the number of output bits of the second counter 140 for counting the reference clock is formula m. = ceil [lg (DR + 1)].

Hereinafter, with reference to the accompanying drawings will be described a speed measurement system and method using the present invention encoder.

Referring to Figure 3, the components of the system according to the present invention are identical except for the prior art and reference clock scaler (170). That is, the encoder 100, the sampling time first counter 110, the reference clock generator 120, the first counter 130, the second counter 140, the controller 160, the AND gate 150, and the reference clock. It consists of a scaler 170. The method for obtaining the operation and the speed of each part is the same as the conventional art described above, and the method for obtaining the reference clock frequency and the number of bits of the second counter 140 satisfying the limit value of the quantization error will be described.

Hereinafter, referring to FIGS. 2 and 3, the selection criteria of the reference clock frequency Fref and the number of output bits m of the second counter 140 for measuring the rotational speed of the motor according to the present invention are presented.

Referring to FIG. 2, the speed measurement is started by measuring the number of reference clocks, and the number of output bits of the second counter 140 is m bits. The number of reference clocks within one period of the encoder pulse is a (where a ∈ {0, 1, .. }), And if the length between the markings of the encoder is L (not shown), the measured speed V 'is expressed by the following equation (4).

Here, Fref is the reference clock frequency and Vlimit is the theoretical maximum value that can measure the speed of the reference clock.

On the other hand, if the maximum speed given is Vmax, the corresponding value of the counter for the maximum speed Vmax is B {B ∈ {0, 1, .. }, And the upper and lower bounds of the maximum speed Vmax are as shown in Equation 5 when the quantization error becomes maximum at the maximum speed Vmax.

On the other hand, the quantization error Eq is defined by equation (6).

On the other hand, since Vlimit = B · Vmax, the quantization error of Equation 6 is expressed by Equation 7.

That is, as can be seen in Equation 7, the higher the measurement speed, the smaller the B, the larger the quantization error.

On the other hand, if the upper boundary of the quantization error limit value is r, equation (7) is as follows.

That is, in Equation 8, from the limit value r of the quantization error to the maximum value Vmax of the counter from 0 (from 0), Can be obtained.

At this time, the optimum design of the present invention can be achieved by selecting the minimum integer value of B satisfying Equation (8).

In another aspect, the quantization error is given by the following equation.

{Eq = [Vlimit / B-Vlimit / (B + 1)]} ≤ r, and thus, Equation (9).

Meanwhile, the dynamic ratio (DR) is defined as follows.

In Equation 10, Vpre denotes the accuracy of the speed meter, and the number of output bits m of the second counter is related to the minimum measurable speed Vmin.

From the above Equation 11, the number of output bits m of the second counter can be obtained from the following equation.

On the other hand, when the quantization error constraint is satisfied by definition, the counter value B corresponding to the maximum speed Vmax satisfies Equation 13 below.

The reference clock frequency Fref can be obtained from Equation 13 as shown in Equation 14.

The above process will be described with an example.

Let the length L between the marking sensors on the encoder be 1/100 m, the minimum speed Vmin to be measured 0.1 m / s, and the minimum speed Vmax to be measured 30m / s. Then, the count value B corresponding to the approximate maximum speed Vmax that satisfies Equation (9) is 400, and according to Equation (15), the reference clock frequency (Fref) is 1.2 MHz. By this, the number of output bits m of the second counter becomes 17 bits.

As described above, the present invention provides a reference clock frequency selection that satisfies the quantization error constraints for the maximum and minimum speeds of the measurable motor with respect to the reference clock for speed measurement of the motor, and an optimal selection criterion for the number of bits of the output counter. To provide.

When using relatively inexpensive incremental encoders with the optimized speedometer or microdifferentiator of the present invention, the flexible structure of the present invention allows the quality of consumer products to be mass-produced through the optimized speedometer or microdifferential through standardization of the product. Each can contribute to cost savings without lowering.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. For example, replacing θ in a rotary encoder or x in a strip encoder with w and dx / dt measured in the above-described method can be transformed into a higher-order higher derivative such as angular acceleration or linear acceleration in a similar manner. will be. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

Claims (4)

The reference clock of the reference clock generator 120 is counted by the first counter 130 according to a predetermined interrupt signal, and the encoder pulse generated by the encoder 100 according to the rotation of the motor is counted by the second counter 140. In the speed measuring device for receiving the counted reference clock and the counted encoder pulse to calculate the speed of the motor in the control unit 160, The number of output bits of the second counter 140 is adjustable by a program, and receives the reference clock of a fixed frequency from the reference clock generator 120 so as to satisfy the limitation condition of the quantization error. And a reference clock scaler (170) for scaling the frequency and transmitting the scaled frequency to the second counter (50). delete The method of claim 1, wherein the controller 160 In addition, the speed measuring device, characterized in that to calculate the number of output bits of the second counter (140) to satisfy the given constraint of the quantization error is programmed in the second counter (140). The reference clock of the reference clock generator 120 is counted by the first counter 130 according to a predetermined interrupt signal, and the encoder pulse generated by the encoder 100 according to the rotation of the motor is counted by the second counter 140. In the speed measuring method for receiving the counted reference clock and the counted encoder pulse to calculate the speed of the motor in the control unit 160, The number of output bits of the second counter 140 is adjustable by a program, and the frequency of the reference clock is obtained by the formula Fref = (B × Vmax) / L so as to satisfy the limitation condition of the quantization error, and the reference clock The number of output bits of the second counter 140 for counting is based on the formula m = ceil [lg (DR + 1)].