KR100461634B1 - The organic electro-luminescence device and method for fabricating of the same - Google Patents

Abstract

The present invention relates to an organic light emitting device, and more particularly, to a structure of the organic light emitting device for improving the aperture ratio and a manufacturing method thereof.

The structure of the organic light emitting device according to the present invention is to form a power supply wiring (V _DD line) for supplying current to the light emitting layer in the same layer in parallel with the gate wiring.

In this way, a short circuit defect does not occur between the gate wiring and the power supply wiring. In addition, the mask process can be reduced, saving time and money.

Description

The organic electroluminescent device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting device, and more particularly, to a configuration of an organic light emitting device for improving an aperture ratio and a manufacturing method thereof.

In general, organic light emitting diodes inject electrons and holes into the light emitting layer from the electron injection electrodes and the hole injection electrodes, respectively, to inject the injected electrons. ) Is a device that emits light when the exciton, which is a combination of holes and holes, drops from the excited state to the ground state.

Due to this principle, unlike a conventional thin film liquid crystal display device, since a separate light source is not required, there is an advantage in that the volume and weight of the device can be reduced.

The method of driving the organic light emitting device may be divided into a passive matrix type and an active matrix type.

The passive matrix type organic light emitting device has a simple structure and a simple manufacturing method. However, the passive matrix type organic light emitting device has a high power consumption and a large area of the display device, and the opening ratio decreases as the number of wirings increases.

Therefore, the passive matrix type organic light emitting display device is used for a small display device, whereas the active matrix type organic light emitting display device is used for a large display device.

Hereinafter, a configuration of a conventional active matrix device will be described with reference to FIG. 1.

1 is a plan view schematically showing one pixel of a conventional organic light emitting diode.

In general, the active matrix organic light emitting diode 9 includes a switching element T _S , a driving element T _D , and a storage capacitor C for each of a plurality of pixels defined in the substrate 10. According to the characteristics of the operation, the switching element T _S or the driving element T _D may be formed of a combination of one or more thin film transistors, respectively.

In this case, the substrate 10 uses a transparent insulating substrate, and the material may be, for example, glass or plastic.

As illustrated, a plurality of gate wires 24 formed in one direction spaced apart from each other by a predetermined distance on the substrate 10 and data wires 48 intersecting each other with the gate wires 24 and the insulating film interposed therebetween. It is composed.

At the same time, the power supply wiring 28 is configured in one direction at a position spaced parallel to the data wiring.

In this case, the single pixel includes a switching element T _S , a driving element T _D , and a storage unit C _ST , and each of the switching element T _S and the driving element T _D is a gate electrode 20. And a thin film transistor including an active layer (12, 14), a source electrode (40, 44) and a drain electrode (42, 46).

In the above-described configuration, the gate electrode 20 of the switching element T _S is connected to the gate line 12, and the source electrode 40 is connected to the data line 48.

The drain electrode 42 of the switching element T _S is connected to the gate electrode 22 of the driving element T _D through the contact hole 38.

The source electrode 44 of the driving element T _D is connected to the power line 28 and the contact hole 36.

In addition, the drain electrode 46 of the driving element T _D is configured to contact the first electrode 54 formed in the pixel portion P, which is a partial region between the power supply wiring 28 and the data wiring 48. do.

At this time, the power line 28 and the lower portion of the first electrode 15 overlap with each other to form a storage capacitor C _ST .

A schematic configuration of a conventional active matrix type organic light emitting diode configured as described above will be described below with reference to FIG. 2.

FIG. 2 is a view schematically showing a wiring formed in a conventional organic light emitting device.

As shown in the figure, a first data pad part 60a and a second data pad part 60b are formed on the upper and lower portions of the substrate 10, respectively. The gate pad part 62 is formed at one side which is not parallel.

The first data pad portion (upper) 60a is connected to an odd or even number data line 48, and the second data pad portion (lower) 60b is an even or odd number data line 48 Connected with

A power line (V _DD line) 28 is formed in parallel with the data line 48, and the power line 28 and the data line 48 are formed to cross the gate line 12. .

In the above configuration, in the portion A where the gate wiring 12 and the power wiring 28 intersect with each other, a defect in which the two wirings are shorted may occur due to a poor deposition of an insulating film formed between the two wirings.

The gate wiring 24 and the data wiring 48 are formed with two layers of insulating films interposed therebetween, and the power wiring 28 has a thin film of insulating film interposed therebetween. Short circuit defects are likely to occur.

Hereinafter, a detailed description will be given with reference to FIGS. 3A to 3H.

3A to 3H are cross-sectional views taken along the line III-III ′ and IV-IV ′ of FIG. 1 and shown in a conventional process sequence.

3A to 3H illustrate a conventional manufacturing process in the order of a mask process, and the mask process means a process of patterning a thin film layer formed on a substrate in the order of exposure-development-etching.

First, FIG. 3A is a first mask process step, and defines a switching unit S, a driving unit D, and a storage unit C on the substrate 10 prior to the process.

Subsequently, after depositing amorphous silicon (a-Si: H) on the entire surface of the substrate 10, a polysilicon layer (not shown) is formed through a dehydrogenation process and a crystallization process using heat.

The polysilicon layer is patterned using a first mask process, and the first and second active patterns 12 and 14 are formed in the switching unit S and the driving unit D, and a third active pattern is formed in the storage unit S. The first electrode 15 is formed. The first electrode is ion-doped separately to the third active pattern.

The first and second active patterns 12 and 14 formed in the switching unit S and the driving unit D are defined as first active regions 12a and 14a and second active regions 12b and 14b, respectively.

Subsequently, an insulating material is deposited on the entire surface of the substrate 10 on which the first and second active patterns 12 and 14 are formed to sequentially form a gate insulating layer 16 and a first metal layer 18, which are first insulating layers.

FIG. 3B is a second mask process step, wherein the first metal layer is patterned by a second mask process, so that the gate electrodes 20 are formed in the first active regions 12a and 14a of the switching unit S and the driving unit D, respectively. And a gate wiring (24 of FIG. 1) connected to the gate electrode 20 of the switching unit S is formed.

Next, p + or n + is doped into the second active region 12b of the switching unit and the second active region 14b of the driving unit D using the gate electrodes 20 and 22 as anti-doping films. The second active region is an ohmic contact region.

Subsequently, an interlayer insulating film 26 serving as a second insulating film is formed on the entire surface of the substrate on which the gate electrodes 20 and 22 and the gate wirings (24 of FIG. 1) are formed.

3c is a third mask process step to form a power supply line (V _DD line).

After forming the second metal layer on the entire surface of the substrate 10 on which the interlayer insulating film 26 is formed, the pattern is formed by a third mask process and extends in a second direction crossing the gate wiring (14 of FIG. 1). Form 28.

3D illustrates a fourth mask process step. After forming the protective film 30, which is a third insulating film, on the entire surface of the substrate 10 on which the power wiring 28 is formed, the pattern is patterned by the fourth mask process. The first contact hole 32a and the second contact hole 32b exposing the second active regions 12b on both sides of the gate electrode 20 formed at A third contact hole 34a and a fourth contact hole 34b exposing second active regions on both sides of the gate electrode 22, and a fifth contact hole exposing a part of the power line 28. 36 and a sixth contact hole 38 exposing a part of the gate electrode 22 of the driving unit D.

3E illustrates a fifth mask process step, wherein a third metal layer is formed on an entire surface of a substrate (not shown) on which the third insulating layer 30 on which the plurality of contact holes are formed is formed, and is patterned using a fifth mask process. A source electrode 40 and a drain electrode 42 connected to the exposed second active region 12b of S, respectively, and a data line 48 connected to the source electrode 40 are formed.

At the same time, the source electrode 44 and the drain electrode 46 connected to the exposed second active region 12b of the driving unit D are formed.

In this case, the source electrode 44 is connected to the exposed power line 28.

In the process as described above, a switching thin film transistor T _S is formed in the switching unit, and a driving thin film transistor T _D is formed in the driving unit.

3F is a sixth mask process step, and silicon nitride (SiO) is formed on the entire surface of the substrate 10 on which the source electrodes 40 and 44 and the drain electrodes 42 and 46 of the thin film transistors T _S and T _D are formed. ₂ ) and a selected one of a group of organic insulating materials including silicon oxide (SiN _X ) are deposited to form a second passivation layer 50, which is a fourth insulating layer.

The passivation layer 50 is patterned by a sixth mask process to form a sixth contact hole 52 exposing a portion of the drain electrode 46 constituting the driving thin film transistor T _D.

FIG. 3G illustrates a seven-mask process, wherein a transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO) is formed on the entire surface of the substrate 10 on which the second passivation layer 50 is formed. One is deposited and patterned to form a first electrode 54 formed in the pixel region P while contacting the exposed drain electrode 46.

Next, FIG. 3H illustrates an eight mask process in which a fifth insulating layer is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the first electrode 54. The third protective film 56 is formed.

Subsequently, the third protective film 56 is patterned by an eighth mask process to expose the first electrode 54.

In this case, the third passivation layer 56 may insulate between the first electrodes 54 of neighboring pixels, and may be formed to insulate between the transparent terminal electrodes of each pad electrode formed at one end of each wiring line, although not illustrated. .

Although not shown, a light emitting layer (not shown) and a second electrode (not shown) are sequentially formed on the first electrode 54 exposed between the fifth insulating layers.

The second electrode may be formed of one selected from aluminum (Al), calcium (Ca), and magnesium (Mg) or a double metal layer of lithium fluorine / aluminum (LIF / Al).

Through the above-described process, an active matrix organic light emitting diode according to the related art can be manufactured.

However, in the organic EL device according to the conventional structure and method as described above, a defect occurs in which the two wirings are short-circuited at the intersection of the power supply wiring and the gate wiring.

In addition, in order to prevent the short circuit of the power wiring and the data wiring spaced in parallel with each other, a mask process is additionally required since the two wirings are formed in different layers, so that the yield in terms of process time and material cost is improved. There is a problem of deterioration.

The present invention has been made for the purpose of solving the above-described problem, the organic light emitting device according to the present invention is formed with the same layer of the power source wiring and the gate wiring.

In this way, process time can be shortened and a short circuit defect can be prevented between the said power supply wiring and a gate wiring.

1 is a plan view schematically showing one pixel of a conventional organic light emitting diode,

2 is a plan view schematically illustrating an array wiring configuration of a conventional organic light emitting device,

3A to 3H are cross-sectional views taken along the line III-III ′ and IV-IV ′ of FIG. 1 and shown in a conventional process sequence.

4 is a plan view schematically showing an array wiring configuration of an organic light emitting device according to the present invention;

5 is a plan view schematically showing an array wiring configuration of an organic light emitting device according to the present invention;

6A through 6G are cross-sectional views illustrating a process sequence of the present invention cut along the lines VV ′ and VIV of FIG. 5.

<Brief description of the main parts of the drawing>

100 substrate 112 first active pattern

114: second active pattern 115: third active pattern

117: gate wiring 120: gate electrode of the drive element

122: gate electrode of the switching element 124: power supply wiring

126: data wiring 134: source electrode of driving element

136: drain electrode of driving element 138: source electrode of switching element

140: drain electrode of the switching element

The organic light emitting device according to the present invention for achieving the above object includes a gate wiring and a data wiring crossing the substrate to define a pixel portion; A switching element configured at an intersection point of the gate line and the data line, the switching element including a gate electrode, an active layer, a source electrode, and a drain electrode; A drive element including a gate electrode in contact with the drain electrode of the switching element, an active layer formed under the gate electrode, a source electrode and a drain electrode in contact with the active layer; A power supply wiring in parallel with the gate wiring while in contact with the source electrode of the driving element; And a first electrode configured to be in contact with the drain electrode of the driving element.

The power supply wiring and the gate wiring are made of the same material as the same layer.

A light emitting layer and a second electrode are further formed on the first electrode, wherein the first electrode is an anode electrode for injecting holes into the light emitting layer, and the second electrode is a cathode electrode for injecting electrons into the light emitting layer. (cathode electrode).

In this case, the first electrode is formed of indium tin oxide (ITO), and the second electrode is formed of one selected from metals including calcium (Ca), aluminum (Al), and magnesium (Mg).

The third active pattern is used as a first electrode through a process of doping n + or p + ions, and a portion of the first electrode and a power supply wiring overlap to form a storage capacitor.

A part of the power supply wiring overlapping the first electrode serves as a second electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an organic light emitting display device, including: defining a switching unit, a driving unit, a storage unit, and a pixel unit on a substrate; A first mask process step of forming first, second, and third active patterns patterned with a polysilicon layer on the switching unit, the driving unit, and the storage unit; Forming a first insulating film on an entire surface of the substrate on which the first, second, and third active patterns are formed; First and second gate electrodes are formed on the first active pattern and the second active pattern, respectively, a gate wiring connected to the first gate electrode, and a power wiring in parallel to the gate wiring on the third active pattern. A second mask process step of forming a; Forming a source region and a drain region by doping impurities into active patterns on both sides of the first and second gate electrodes, respectively; An interlayer insulating film, which is a second insulating film, is formed on the entire surface of the substrate on which the first and second gate electrodes, the gate wirings, and the power supply wiring are formed, and then patterned to form the source and drain regions of the first and second active patterns; A third mask process step of exposing a portion of the second electrode; A drain in contact with the first active pattern in forming a data line in one direction by connecting a source electrode and a drain electrode in contact with the source and drain regions of the first and second active patterns, and a source electrode of the switching unit, respectively; A fourth mask process step of forming an electrode in contact with a second gate electrode and a source electrode in contact with the second active pattern in contact with a power line; A fifth mask process step of forming a protective film, which is a third insulating film, on the entire surface of the substrate on which the data line and the source and drain electrodes are formed, and then patterning a portion thereof to expose a part of the drain electrode of the driver; And forming a first electrode in contact with the exposed drain electrode while forming the pixel portion.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A feature of the present invention is to form a power line (V _DD line) for supplying current to the light emitting layer with the gate material of the same material and the two wires in parallel.

4 is a diagram schematically illustrating a wiring configuration of an organic light emitting diode according to the present invention.

As illustrated, the organic light emitting device 99 according to the present invention includes a first data pad portion (top) 102a and a second data pad portion (bottom) 102b on one side and the other side of the substrate 100. The gate pad portion 104 is configured on one side that is not parallel to the first and second data pad portions 102a and 102b.

The first and second data pad portions 102a and 102b are formed by connecting even-numbered or odd-numbered data lines 148, respectively, and the gate pad portion 104 is connected to the gate lines 117. .

In the above-described configuration, the power supply wiring 128 is configured to be spaced apart in parallel with the gate wiring 117.

A power pad unit 129 is formed at one end of the power line 128 corresponding to the gate pad unit 104.

The characteristics of the above-described configuration are different from the related art, in which the power source wiring 128, which is configured by crossing the gate wiring 117 with a single insulating film interposed therebetween, is formed in parallel with the gate wiring 117. 117) to prevent short circuit.

Hereinafter, the structure of the organic light emitting diode according to the present invention having the above-described configuration will be described in detail with reference to FIG. 5.

5 is a plan view schematically illustrating one pixel of the organic light emitting diode according to the present invention.

As shown in the drawing, the gate line 117 and the data line 126 intersect on the transparent insulating substrate 100 to define the pixel portion P, and the switching element T _S is located at an intersection point where the two wires intersect. Configure

The switching element T _S includes a gate electrode 120, an active layer 112, a drain electrode 136, a source electrode 134, and a gate electrode 122 in contact with the drain electrode 136. In addition, a driving element T _D including an active layer 114 formed under the gate electrode 122, a source electrode 138 and a drain electrode 140 in contact with the active layer 114, respectively.

The drain electrode 140 of the driving device T _D is configured to contact the first electrode 148 formed in a part of the pixel portion P, and the source electrode 138 of the driving device T _D is It is configured to be connected to the power line 124.

At this time, the power line 124 is spaced apart from each other with the gate line 117 is configured in one direction in parallel.

In the above-described configuration, the power supply wiring 124 intersects with the gate wiring 117, but the insulating layer (interlayer insulating film) existing between the power supply wiring 124 and the gate wiring 117 is very thick and thus short-circuited. There is no possibility of failure.

Hereinafter, a manufacturing process of the organic light emitting device configured as described above will be described with reference to the drawings.

6A through 6H are cross-sectional views taken along the lines VV ′ and VIV of FIG. 5 and according to the process sequence of the present invention.

6A to 6H illustrate a conventional manufacturing process in the order of a mask process, and the mask process refers to a process of patterning a thin film into a predetermined shape through an exposure-developing-etching sequence. A description will be given of a coplanar structure thin film transistor using an active layer of a thin film transistor used as an element as polysilicon.)

First, in FIG. 6A, a switching unit S, a driving unit D, and a storage unit C are defined on a substrate as a first mask process.

Subsequently, after depositing amorphous silicon (a-Si: H) on the entire surface of the substrate 100, a dehydrogenation process and a crystallization process using heat to form a polysilicon layer.

The polysilicon layer is patterned using a first mask process to form first, second, and third active patterns 112, 114, and 115 in the switching unit S, the driving unit D, and the storage unit C, respectively.

In this case, the third active pattern 115 becomes the storage first electrode through ion doping.

The first and second active patterns 112 and 114 may be defined as first active regions 112a and 114a and second active regions 112b and 114b, respectively.

Subsequently, an insulating material is deposited on the entire surface of the substrate 100 on which the first, second, and third active patterns 112, 114, and 115 are formed, and the gate insulating film 116, which is the first insulating film, and the first metal layer 118 are sequentially formed.

The gate insulating layer 116 is formed by depositing one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ), and the first metal layer is formed of aluminum (Al), aluminum alloy, and copper. (Cu), tungsten (W), tantalum (Ta) and molybdenum (Mo), including one selected from the group of conductive metals.

FIG. 6B is a second mask process step, wherein the first metal layer is patterned by a second mask process, and gate electrodes 120 and 122 are formed in the first active regions 112a and 114a of the switching unit S and the driving unit D, respectively. ) And a gate wiring (117 in FIG. 5) connected to the gate electrode 120 of the switching unit S.

At the same time, the power line 124 is formed in a parallel direction to be spaced apart from the gate line 117 of FIG. 5.

In some embodiments, the first insulating layer exposed to the lower portion may be etched using the gate electrode 120, the gate line 117 of FIG. 5, and the power line 124 as an etch stop layer.

Subsequently, p + or n + is doped into the exposed second active region 112b of the switching unit S and the exposed second active region 114b of the driving unit D, and then activated. The active regions 112b and 114b become ohmic contact layers.

Depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate electrode 120 and the gate wiring 117 of FIG. 5 are formed. A second insulating film 126 that is an interlayer insulating film is formed.

The interlayer insulating layer 126 is formed by depositing about 10 times the thickness of the first insulating layer 116.

FIG. 6C illustrates a third mask process step, wherein the first contact hole 128a exposing the second active regions on both sides of the gate electrode 120 formed in the switching unit S and the second contact hole, respectively. A third contact hole 130a and a fourth contact hole 130b exposing the second active regions on both sides of the gate electrode 122 formed in the driver D, and the driver A fifth contact hole 132 exposing a part of the gate electrode 122 of D) and a fifth contact hole 133 exposing a part of the power line 124 are formed.

6D illustrates a fourth mask process step, in which a second metal layer is formed on the entire surface of the substrate 100 on which the interlayer insulating layer 126 is formed and patterned using a fourth mask process to expose the second exposed portion of the switching unit S. The source electrode 134 and the drain electrode 136 respectively connected to the active region 114b and the source electrode 134 while being connected to the power wiring 124 and the gate wiring 117 of FIG. A source electrode 138 and a drain electrode 140 are formed to contact the formed data line 139 and the exposed second active region 114b of the driving unit D, respectively.

In this case, the source electrode 138 of the driving unit D is connected to the exposed power line 124.

In the process as described above, a switching thin film transistor T _S is formed in the switching unit S, and a driving thin film transistor T _D is formed in the driving unit.

6E illustrates a fifth mask process step, in which an insulating film is coated on the entire surface of the substrate 100 on which the source electrodes 134 and 138 and the drain electrodes 136 and 140 of each of the thin film transistors T _S are formed, and thus the protective film 142 as the third insulating film. ).

Subsequently, a sixth contact hole 146 exposing a portion of the drain electrode 140 constituting the driving thin film transistor T _D is formed by patterning the fifth mask process.

FIG. 6F is a sixth mask process and includes one selected from a transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO) on an entire surface of the substrate 100 on which the passivation layer 142 is formed. Is deposited and patterned to form a first electrode 148 formed in the pixel portion P while contacting the exposed drain electrode 140.

The first electrode 148 is a hole injection electrode for injecting a hole.

6G illustrates a process of exposing the first electrode 148 by forming a fourth insulating film 150 on the front surface of the substrate 100 on which the first electrode 148 is formed by a seventh mask process. Proceed.

Although not shown, a light emitting layer is formed on the first electrode 148, and a metal having a low work function such as aluminum (Al) is deposited on the light emitting layer to form a second electrode (not shown). do.

In this case, the material forming the second electrode may be formed of one selected from aluminum (Al), calcium (Ca), and magnesium (Mg) or a double metal layer of lithium fluorine / aluminum (LIF / Al).

Through the process as described above it can be produced an organic light emitting device according to the present invention.

Therefore, since the organic light emitting device according to the present invention as described above is composed of the same material in the same layer in parallel with the gate wiring, it has the effect of saving time and material cost by simplifying the process.

In addition, unlike the conventional art, since the short circuit of the gate wiring and the power supply wiring does not occur, there is an effect of improving the yield.

Claims (18)

Gate wiring and data wiring crossing the substrate to define the pixel portion; A switching element configured at an intersection point of the gate line and the data line, the switching element including a gate electrode, an active layer, a source electrode, and a drain electrode; A drive element including a gate electrode in contact with the drain electrode of the switching element, an active layer formed under the gate electrode, a source electrode and a drain electrode in contact with the active layer; A power supply wiring in parallel with the gate wiring while in contact with the source electrode of the driving element; A first electrode configured in the pixel portion in contact with the drain electrode of the driving element Organic electroluminescent device comprising a. The method of claim 1, The power source line and the gate line are organic light emitting elements consisting of the same layer of the same material. The method of claim 1, The organic light emitting device further comprises a light emitting layer and a second electrode on the first electrode. The method of claim 3, wherein The first electrode is an anode electrode for injecting holes into the light emitting layer, and the second electrode is a cathode electrode for injecting electrons into the light emitting layer. The method of claim 4, wherein The first electrode is an indium tin oxide (ITO) organic light emitting device. The method of claim 4, wherein The second electrode is an organic light emitting device comprising one selected from metals including calcium (Ca), aluminum (Al), magnesium (Mg). The method of claim 1, The third active pattern is an organic light emitting diode doped with n + or p + ions. The method according to any one of claims 1 to 7, And a portion of the third active pattern and a part of the power wiring to form a storage capacitor. Defining a switching unit, a driving unit, a storage unit, and a pixel unit on the substrate; A first mask process step of forming first, second, and third active patterns patterned with a polysilicon layer on the switching unit, the driving unit, and the storage unit; Forming a first insulating film on an entire surface of the substrate on which the first, second, and third active patterns are formed; First and second gate electrodes are formed on the first active pattern and the second active pattern, respectively, a gate wiring connected to the first gate electrode, and a power wiring in parallel to the gate wiring on the third active pattern. A second mask process step of forming a; Forming a source region and a drain region by doping impurities into active patterns on both sides of the first and second gate electrodes, respectively; An interlayer insulating film, which is a second insulating film, is formed on the entire surface of the substrate on which the first and second gate electrodes, the gate wirings, and the power supply wiring are formed, and then patterned to form the source and drain regions of the first and second active patterns; A third mask process step of exposing a portion of the second electrode; A drain in contact with the first active pattern in forming a data line in one direction by connecting a source electrode and a drain electrode in contact with the source and drain regions of the first and second active patterns, and a source electrode of the switching unit, respectively; A fourth mask process step of forming an electrode in contact with a second gate electrode and a source electrode in contact with the second active pattern in contact with a power line; A fifth mask process step of forming a protective film, which is a third insulating film, on the entire surface of the substrate on which the data line and the source and drain electrodes are formed, and then patterning a portion thereof to expose a part of the drain electrode of the driver; Forming a first electrode in contact with the exposed drain electrode while forming the pixel portion; Organic electroluminescent device manufacturing method comprising a. The method of claim 9, The power source wiring and the gate wiring is an organic light emitting device manufacturing method comprising the same material of the same layer. The method of claim 9, The organic light emitting device of claim 1, wherein the light emitting layer and the second electrode are further formed on the first electrode. The method of claim 11, The first electrode is an anode electrode (hole electrode) for injecting a hole in the light emitting layer, the second electrode is a cathode electrode (cathode electrode) for injecting electrons into the light emitting layer (cathode electrode) manufacturing method. The method of claim 11, The first electrode is an indium tin oxide (ITO) manufacturing method of an organic light emitting device. The method of claim 11, The second electrode is a method of manufacturing an organic light emitting device comprising one selected from metals including calcium (Ca), aluminum (Al), magnesium (Mg). The method of claim 9, And the first insulating film, the second insulating film, and the third insulating film comprise silicon nitride and silicon oxide. The method of claim 15, And the second insulating film is about 8 to 10 times thicker than the first insulating film. The method of claim 9, The third active pattern is a method of manufacturing an organic light emitting device doped with n + or p + ions. The method according to any one of claims 9 to 17, And a portion of the third active pattern overlapping the power supply wiring to form a storage capacitor.