KR100457344B1 - Ethernet interface device having function of controlling transmitting frame considering backoff delay time - Google Patents

Abstract

PURPOSE: An Ethernet interface device is provided to generate a backoff clock by calculating a backoff delay time having a maximum delay time according to the number of retransmissions. CONSTITUTION: A decoder(110) enables a first load signal when a number of retransmission is between 0 and 10, enables a second load signal when the number of retransmission is greater than 10, disables the first and second load signals when the number of retransmission is 0, enables a count control signal when the number of retransmission is not 0 and a trial attempt signal is enabled, and disables the count control signal when a third match signal is enabled. A reference counter(120) counts the number of clocks while the current control signal is enabled. A backoff maximum setting member(190) outputs a backoff maximum value. A manipulation controller(150) enables a manipulation signal when the trial attempt signal is enabled, disables the manipulation control signal when first or second match signal is enabled, and enables the third match signal when the first and second match signals are enabled. A manipulator(160) outputs 2¬k when the manipulation control is enabled. A slot comparator(180) enables a backoff clock when the result of a slot counter(210) is equal to output of the manipulator.

Description

Ethernet Interface Apparatus With a Frame Transmission Control Function

The present invention relates to an Ethernet interface device, and more particularly, to frame transmission with a maximum backoff delay in CSMA / CD of IEEE 802.3.

In Carrier Sense Multiple Access With Coolision Detection (CSMA / CD), a communication protocol in a widely used local area network (LAN), carrier sense, which is a collision of transmission lines during transmission of frames, If detected, it will attempt to retransmit after a certain amount of time.

The randomly determined time is defined as a so-called backoff time.

The back off time may be expressed as follows.

0 ≤ n <Attempt_limit (n: Attempt times = Resend attempts)

K = min (n, backoff_limit)

0 ≤ Random Value (N) ≤ 2 ^K

backoff_delay = slot_time X N

In this case, the number of retransmission attempts n is the maximum retransmission attempt defined in the recommendation (Attempt_limit) is "16", so retransmission attempts of "15" are possible, and the variable K is the number of retransmission attempts n and the backoff upper limit defined in the recommendation. (backoff_limit) has the smaller value of "10". N has a random value within the above range, and when the maximum delay time, K is expressed as follows.

If n ≤ 10 then K = n

K = 10 if 11 ≤ n ≤ 15

In addition, since slot_time is 64 bytes (512 bits) defined in the recommendation, if the transmission speed is 10 Mbps (1 bit transmission rate = 100 ns), the maximum delay time is

backoff_delay = it can be expressed by the 51.2ms × 2 ^K.

Accordingly, the present invention is in accordance with the recommendation of IEEE 802.3, and calculates the backoff delay time having the maximum delay time according to the number of retransmission attempts, and has an Ethernet interface apparatus having a frame transmission control function for generating a backoff clock to control retransmission. The purpose is to provide.

1 illustrates an Ethernet interface apparatus having a frame transmission control function according to an embodiment of the present invention;

2 is a circuit diagram showing in detail the decoder shown in FIG. 1;

3 is a circuit diagram showing in detail the operation controller shown in FIG.

4 is a circuit diagram showing in detail the calculator shown in FIG.

FIG. 5 is a timing chart illustrating a maximum delay operation of a backoff clock when a retransmission count is 11 times in an Ethernet interface device having a frame transmission control function according to an embodiment of the present invention; FIG.

6 is a timing chart showing a maximum delay operation of a backoff clock when the number of retransmission attempts is three times in an Ethernet interface device having a frame transmission control function according to an embodiment of the present invention;

<Explanation of symbols for the main parts of the drawings>

110: decoder 120: reference counter

130: retransmission comparator 140: back-off comparator

150: operation controller 160: calculator

180: slot comparator 190: back off upper limit setting unit

210: slot counter

According to a feature of the present invention proposed to achieve the above object, an Ethernet interface device having a frame transmission control function enables the first load signal to load the number of attempts when the number of retransmission attempts is greater than 0 and less than 10. If the number of retransmission attempts is greater than 10, enable the second load signal to load the back off upper limit value. If the number of retransmission attempts is equal to 0, disable the first and second load signals, and try to retransmit. A decoder for enabling the count control signal when the number of attempts is not 0 and enabling the count start signal, and disabling the count control signal when the third coincidence signal is enabled; A reference counter for counting and outputting a clock while the count control signal is enabled; A retransmission comparator enabled by the first load signal of the decoder and enabling the first coincidence signal when the number of retransmission attempts and the count value of the reference counter are the same; A back off upper limit setting unit for outputting a back off upper limit value; A backoff comparator enabled by the second load signal of the decoder and enabling a second coincidence signal when a backoff upper limit value and a count value of the reference counter are equal to each other; Enable the operation control signal if the attempt start signal is enabled, disable the operation control signal if the first coincidence signal of the retransmission comparator or the second coincidence signal of the backoff comparator is enabled, and the first or second coincidence signal An operation controller for enabling the third coincidence signal when is enabled; The operation control signal is enabled, the operator and for outputting a value 2 ^K each time a clock generator; A slot counter for counting a slot clock and outputting a slot count value; It is enabled according to the slot clock, and includes a slot comparator to enable the back-off clock when the slot count value is equal to the operation value of the calculator.

In a preferred embodiment of this aspect, the retransmission number of times consists of 4-bit data.

In a preferred embodiment of this feature, the reference counter includes a four bit hexadecimal counter.

In a preferred embodiment of this aspect, the retransmission comparator is a 4-bit comparator.

In a preferred embodiment of this aspect, the backoff comparator is a 4-bit comparator.

In a preferred embodiment of this aspect, the backoff upper limit setting section is set to 1010hex.

In a preferred embodiment of this aspect, the operator is a 10-bit shifter.

In a preferred embodiment of this aspect, the slot counter is a 1024 binary counter.

In a preferred embodiment of this aspect, the slot comparator is a 10 bit comparator.

In a preferred embodiment of this aspect, the decoder comprises: a JK flip-flop in which a trial start signal is input to the J input terminal, a clock is input to the clock input terminal, and a third coincidence signal is input to the K input terminal; An orgate for ORing each bit of the retry transmission count; An AND gate for performing an AND operation on the output of the JK flip-flop and the output of an or gate to output a count control signal; A first NAND gate which inverts and outputs the inverted second bit, the inverted third bit, and the non-inverted most significant bit of the retransmission attempt count, and then inverts the result; A second NAND gate that performs an AND operation on the inverted least significant bit of the retransmission attempt number, the non-inverted second bit, the inverted third bit, and the non-inverted most significant bit, and outputs the result; A third NAND gate, which is logically multiplied and inverted by the output of the second NAND gate, the output of the first NAND gate, and the non-inverted most significant bit of the number of retransmission attempts, and is output as a first load signal; And a gate of the inverted output of the or gate and the gate of the third NAND gate, which is output as a second load signal.

In a preferred embodiment of this aspect, the arithmetic controller includes a D flip-flop for inputting a trial start signal to a D input terminal, a clock to a clock input terminal, and a reset signal to a reset input terminal; An OR gate for ORing the first match signal from the retransmission comparator and the second match signal from the backoff comparator and outputting a third match signal; The J input terminal is inputted with the output of the D flip-flop, the clock input terminal is inputted with a clock, the K input terminal is inputted with an output of an or gate, the reset input terminal is inputted with a reset signal, and outputs an operation control signal. It includes.

In a preferred embodiment of this aspect, the calculator has a JK input of a control signal to the J input terminal, a clock signal to the clock input terminal, a trial start signal to the K input terminal, and a reset signal to the reset input terminal. Flip-flops; A multiplexer for outputting a high level when the output of the JK flip-flop is disabled and a low level when the output of the JK flip-flop is disabled; A first shift register enabled by an operation control signal and latching data input from the multiplexer; A second shift register enabled by an operation control signal and configured to store data input from the first shift register and to output the data at a next clock; A third shift register enabled by an operation control signal and configured to store data input from the second shift register and output the data at a next clock; A fourth shift register enabled by an operation control signal and configured to store data input from the third shift register and output the data at a next clock; A fifth shift register enabled by an operation control signal and configured to store data input from the fourth shift register and output the data at a next clock; A sixth shift register enabled by an operation control signal and configured to store data input from the fifth shift register and to output the data at a next clock; A seventh shift register enabled by an operation control signal and configured to store data input from the sixth shift register and output the data at a next clock; An eighth shift register enabled by the operation control signal and configured to store data input from the seventh shift register and output the data at a next clock; A ninth shift register enabled by an operation control signal and configured to store data input from the eighth shift register and to output the data at a next clock; And a tenth shift register enabled by the operation control signal and configured to store data input from the ninth shift register and output the data at a next clock.

The present invention relates to an Ethernet interface, wherein a decoder decodes a retransmission attempt count and outputs a load signal and a count control signal, a reference counter counts and outputs a clock according to a count control signal, and a retransmission comparator counts a retransmission attempt count. The backoff comparator compares whether the backoff upper limit value is equal to the counted clock value, the arithmetic controller outputs arithmetic control signal according to the result of the retransmission comparator or backoff comparator, and the arithmetic operator The backoff operation is performed according to the control signal, the slot counter counts the slot, and the slot comparator controls the backoff clock by comparing the counted number of slots with the backoff operation value. According to the present invention configured as described above, the backoff operation can be performed according to the number of retransmission attempts, and the backoff clock can be output to control the time for transmitting the frame based on the backoff operation value and the slot value.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6.

Referring to FIG. 1, the Ethernet interface apparatus having a novel frame transmission control function of the present invention includes a decoder, a reference counter, a retransmission comparator, a backoff upper limit setting unit, a backoff comparator, an operation controller, a calculator, a slot counter, and a slot comparator. Equipped. In the figure, reference numeral Cur_Attempt denotes a challenge start signal, Pclk denotes a clock, Resetb resets, Attempt denotes the number of retransmission attempts, Slot_Time denotes a slot clock, and BackOff_Time denotes a backoff clock. The attempt start signal Cur_Attempt is generated when a frame is attempted to be transmitted. Attempt is a retransmission attempt number (attempt) represents the number of attempted transmission attempts up to now, and consists of a 4-bit hexadecimal number. In addition, the slot clock (Slot_Time) is generated for one slot (for example, 51.2ms at 10Mbps).

First, as shown in the figure, the decoder 110 receives the attempt start signal, the number of retransmission attempts, the clock, the reset signal, and the match signal Same, and the count control signal Cnt_En and the first load signal Load_Attempt. The second load signal Load_MaxB is output.

The decoder 110 decodes the accumulated result Attempt of the number of frame retransmissions attempted so far, and determines whether to use the number of retransmission attempts (for example, n) for the backoff operation or the upper limit for the backoff. Optionally output Here, the backoff upper limit value is a value set in the backoff upper limit setting unit 190, for example, 10dec (decimal value) is set.

Here, the decoder 110 enables the load signal Load_Attempt to load the number of retransmission attempts when the retransmission attempt number Attempt is greater than 0 and 10 or less. On the other hand, when the number of retransmission attempts is greater than 10, the load signal Load_MaxB is enabled to load the backoff upper limit value. In addition, when the retransmission attempt number Attempt is 0, both of the two load signals Load_Attempt and Load_MaxB are disabled. The enable signal uses a high level logic signal and the disable signal uses a low level logic signal.

The decoder 110 outputs a count control signal Cnt_En to control an operation of the reference counter 120 that outputs a clock count value compared with the retransmission attempt number Attempt. As such, the count control signal Cnt_En output from the decoder 110 is enabled when the attempt start signal Cur_Attempt is enabled, and is disabled when the coincidence signal Same from the operation controller 150 is enabled. Is enabled.

2 is a diagram illustrating the decoder 110 in detail.

As shown in the figure, the J input terminal of the JK flip-flop 111 is the trial start signal Cur_Attempt, the clock input terminal CK is the clock Pclk, and the K input terminal is the coincidence signal Same from the operation controller 150. Is input. Therefore, the JK flip-flop 111 enables the output Q when the attempt start signal Cur_Attempt is enabled, and disables the output Q when the coincidence signal Same is enabled.

On the other hand, the oragate 112 logically outputs all bits of the retransmission attempt number Attempt. Therefore, if the retransmission attempt count Attempt is greater than zero, the oragate 112 enables the output. Therefore, when the outputs of the JK flip-flop 111 and the oracle 112 are both enabled, the AND gate 115 enables and outputs the count control signal Cnt_En.

The load signal Load_Attempt is output from four inverters and three NAND gates 113, 114, and 116 having a retransmission attempt number Attempt. The NAND gate 113 performs an AND operation on the inverted signal of the second bit <1> of the retransmission attempt count (Attempt), the inverted signal of the third bit <2>, and the most significant bit <3>, and inverts the result. In addition, the NAND gate 114 converts the inverted signal of the least significant bit <0> of the retransmission attempt count (Attempt), the inverted second bit <1>, the inverted signal of the third bit <2>, and the most significant bit <3>. Inverts and outputs the result. The NAND gate 116 then multiplies the output of the NAND gate 113, the output of the NAND gate 114, and the most significant bit <3> of the retransmission attempt number Attempt by inverting and outputting the result. In this way, the signal output from the NAND gate 116 becomes the load signal Load_Attempt.

Finally, the load signal Load_MaxB is output from the north gate 117. The NOR gate 117 logically sums the inverted signal of the oragate 112 and the output signal of the NAND gate 116 and then inverts the output signal.

Referring back to FIG. 1, when the count control signal Cnt_En from the decoder 110 is enabled, the reference counter 120 counts and outputs a clock Pclk. The reference counter 120 terminates the count operation when the count control signal Cnt_En is disabled. The clock count value output from the reference counter 120 is input to the retransmission comparator 130 and the backoff comparator 140, respectively. The reference counter 120 outputs a count value from 0hex to Fhex as a 4-bit counter.

In the drawing, the retransmission comparator 130 is operated when the retransmission attempt count Attempt is used for the backoff operation, and the backoff comparator 140 is operated when the backoff upper limit value MaxBackOff is used for the backoff operation.

That is, the retransmission comparator 130 is enabled according to the load signal Load_Attempt from the decoder 110, and when the count value input from the reference counter 120 becomes equal to the retransmission attempt count (Same), the coincidence signal (Same) Enable. On the other hand, the backoff comparator 140 is enabled according to the load signal Load_MaxB from the decoder 110, and the match signal (Same) when the count value input from the reference counter 120 is equal to the upper backoff limit MaxBackOff. Enable). Here, the retransmission comparator 130 and the backoff comparator 140 are configured with a 4-bit comparator.

The operation controller 150 enables the operation control signal Shift_En to perform the backoff operation when the attempt start signal Cur_Attempt is enabled, and the match signal or the backoff comparator 140 from the retransmission comparator 130. If the coincidence signal from is enabled, the operation control signal Shift_En is disabled so that the backoff operation is terminated. In addition, the operation controller 150 enables the coincidence signal output to the decoder 110 when the coincidence signal from the retransmission comparator 130 or the coincidence signal from the backoff comparator 140 is enabled. .

3 is a diagram illustrating the operation controller 150 in detail.

As shown in the figure, the operation controller 150 is composed of a D flip-flop 151, an oragate 153, and a JK flip-flop 152.

The D flip-flop 151 latches and outputs the attempt start signal Cur_Attempt. The JK flip-flop 152 then enables the output according to the signal input from the D flip-flop 151. In the K input terminal of the JK flip-flop 152, the coincidence signal from the retransmission comparator 130 and the coincidence signal from the backoff comparator 140 are logically inputted by the oragate 153. Therefore, the JK flip-flop 152 disables the output Q when the signal at the K input terminal is enabled. The output of the oragate 153 is output as a match signal (Same) of the operation controller 150.

Referring back to FIG. 1, the operator 160 performs the backoff operation through the shifter. That is, when the operation control signal Shift_En from the operation controller 150 is enabled, the operator 160 shifts 1-bit data from the least significant bit to the most significant bit according to the clock Pclk. Therefore, if for example that number of clock K, back-off calculation value (BackOff_Val) outputted from the arithmetic unit 160 are the 2 ^K. The operation of the calculator 160 stops when the operation control signal Shift_En from the operation controller 150 is disabled. In this way, the 10-bit backoff operation value output from the operator 160 is input to the slot comparator 180 as data.

4 is a diagram illustrating the calculator 160 in detail.

As shown in the figure, the J input terminal of the JK flip-flop 161 is input the operation control signal (Shift) from the operation controller 150, the K input terminal is input to the trial start signal (Cur_Attempt). The output Q of the JK flip-flop is applied to the control signal input terminal S of the multiplexer 162.

First, when the retry is initiated and the attempt start signal Cur_Attemp is enabled, the JK flip-flop 161 disables the output Q. Then, the multiplexer 162 outputs the signal of the input terminal D0. Therefore, the high level from the multiplexer 162 is applied to the data input terminal D of the shift register 163. The sp register 163 stores data 1, and the data 1 stored in the shift register 163 is applied to the next shift register 164 and output as an operation value BackOff_Val. That is, the operation value BackOff_Val is 000000001hex.

In the next clock, the shift register 163 outputs a low level, and the shift register 164 outputs a high level. In this manner, each time the clock Pclk is generated, one bit of data is shifted through the shift register of the upper bit. Such a shift operation is performed only while the operation control signal is enabled. Therefore, the operator 160 performs a calculation of 2 ^K corresponding to 000000001hex to 100000000hex each time a clock is generated.

Referring back to FIG. 1, in the drawing, the slot counter 210 counts and outputs a slot clock (Slot_Time) generated every one slot.

Then, the slot comparator 180 outputs a backoff clock (BackOff_Time) to retry frame transmission when the slot count value from the slot counter 210 is equal to the calculation value from the calculator 160.

FIG. 5 is a timing chart illustrating the maximum delay operation of the backoff clock when the retransmission count is 11 times in the Ethernet interface apparatus having the frame transmission control function according to an embodiment of the present invention.

As shown in the figure, the number of retransmission attempts Attempt [3: 0] represents a value of 11 dec. Then, the backoff upper limit value 10dec is applied to the backoff operation so that the backoff operation value BackOff_Val [9: 0] becomes 1024. Therefore, at the leading edge of the clock Pclk after the slot count value Cnt [9: 0] becomes 1024, the backoff clock (BackOff_Time) is output as high as one clock pulse.

6 is a timing chart illustrating the maximum delay operation of the backoff clock when the number of retransmission attempts is three times in the Ethernet interface apparatus having the frame transmission control function according to an embodiment of the present invention.

As shown in the figure, the number of retransmission attempts Attempt [3: 0] represents a value of 3dec. If the attempt start signal Cur_Attempt is input at a high level by one clock pulse at any point in time, the operation control signal Shift_En is at a high level by three clock pulses at the leading edge of the clock after the attempt start signal is terminated. When the operation control signal Shift_En is at the low level, the backoff operation value BackOff_Val [9: 0] outputs 8dec. At this time, the slot count value Cnt outputs 1dec when the third clock of the operation control signal Shift_En is used. In this manner, the backoff clock BackOff_Time is output at a high level by one clock pulse at the leading edge of the clock Pclk after the slot count value is output to eight.

The present invention relates to an Ethernet interface according to the IEEE 802.3 recommendation, calculates a backoff delay time having a maximum delay time according to the number of retransmission attempts, and generates a backoff clock to control retransmission.

Claims (12)

In an Ethernet interface device that controls a backoff clock (BackOff_Time) according to a start signal (Cur_Attempt), a clock (Pclk), a reset (Resetb), a retransmission attempt count (Attempt), and a slot clock (Slot_Time): If the Attempt is greater than 0 and less than 10, the first load signal Load_Attempt is enabled to load the number of attempts. If the Attempt is greater than 10, the upper backoff limit is loaded. Enable the second load signal Load_MaxB, disable the first and second load signals when the retransmission attempt count is equal to 0, and attempt attempt signal when the retransmission attempt count is not zero. A decoder 110 that enables the count control signal Cnt_En when (Cur_Attempt) is enabled, and disables the count control signal Cnt_En when the third coincidence signal Same is enabled; A reference counter 120 for counting and outputting a clock Pclk while the count control signal Cnt_En is enabled; When the first load signal Load_Attempt of the decoder 110 is enabled and the retry transmission count Attempt is equal to the count value Cnt of the reference counter 120, the first coincidence signal Same is sent. A retransmission comparator 130 for enabling; A back off upper limit setting unit 190 for outputting a back off upper limit value MaxBackOff; When the second load signal Load_MaxB of the decoder 110 is enabled and the backoff upper limit MaxBackOff equals the count value Cnt of the reference counter 120, the second coincidence signal Same is connected. A backoff comparator 140 for enabling; If the attempt start signal Cur_Attempt is enabled, the operation control signal Shift_En is enabled, and the first coincidence signal Same of the retransmission comparator 130 or the second coincidence signal Same of the backoff comparator 140 An operation controller 150 for disabling the operation control signal Shift_En and enabling the third coincidence signal Same when the first or second coincidence signal Same is enabled; The operation control signal (Shift_En) is enabled and, the clock 2 ^K value each time it occurs (Pclk) computing unit 160 to output a (BackOff_Val, K is a clock number) and; A slot counter 210 for counting the slot clock Slot_Time and outputting a slot count value Cnt; The slot comparator 180 is enabled according to the slot clock (Slot_Time), and the slot comparator 180 enables the back off clock (BackOff_Time) when the slot count value Cnt is equal to the operation value BackOff_Val of the calculator 160. Ethernet interface device having a frame transmission control, characterized in that configured. The method of claim 1, The retransmission attempt count (Attempt) is an Ethernet interface device having a frame transmission control function, characterized in that consisting of 4-bit data. The method of claim 1, The reference counter 120 is an Ethernet interface device having a frame transmission control function, characterized in that the 4-bit hexadecimal counter. The method of claim 1, The retransmission comparator 130 is an Ethernet interface device having a frame transmission control function, characterized in that the 4-bit comparator. The method of claim 1, The backoff comparator 140 is a four-bit comparator Ethernet interface device having a frame transmission control, characterized in that. The method of claim 1, The upper backoff limit setting unit 190 is an Ethernet interface device having a frame transmission control function, characterized in that set to 1010hex. The method of claim 1, The operator 160 is an Ethernet interface device having a frame transmission control function, characterized in that the 10-bit shifter. The method of claim 1, The slot counter 210 is an Ethernet interface device having a frame transmission control, characterized in that the 1024 binary counter. The method of claim 1, And said slot comparator is a 10-bit comparator. The method of claim 1, The decoder 110 receives the attempt start signal Cur_Attempt to the J input terminal, the clock Pclk to the clock input terminal CK, and the third coincidence signal Same to the K input terminal. 111); An orifice 112 for ORing each bit of the retransmission attempt count Attempt; An AND gate 115 for performing an AND operation on the output of the JK flip-flop 111 and the output of the or gate 112 to output the count control signal Cnt_En; A first NAND gate 113 for performing an AND operation on the inverted second bit of the retransmission attempt number Attempt, the inverted third bit, and the non-inverted most significant bit, and then inverting the result; A second NAND gate 114 which performs an AND operation on the inverted least significant bit of the retransmission attempt number Attempt, the non-inverted second bit, the inverted third bit, and the non-inverted most significant bit, and outputs the result; The output of the second NAND gate 114, the output of the first NAND gate 113, and the non-inverted most significant bit of the retransmission attempt number Attempt are ANDed and inverted to be output as the first load signal Load_Attempt. A third NAND gate 116; And an inverted output of the or gate 112 and a NOR gate 117 for logically inverting and inverting an output of the third NAND gate and outputting the second NAND gate as a second load signal Load_MaxB. Ethernet interface device with functions. The method of claim 1, The operation controller 150 inputs a trial start signal Cur_Attempt to the D input terminal D, a clock Pclk to the clock input terminal CK, and a reset signal Resetb to the reset input terminal RN. A D flip-flop 151; An OR gate 153 for ORing the first match signal from the retransmission comparator 130 and the second match signal from the backoff comparator 140 and outputting a third match signal Same; The J input terminal J receives the output of the D flip-flop 151, the clock input terminal CK receives the clock Pclk, the K input terminal K receives the output of the or gate 153, The reset input terminal (RN) has a JK flip-flop (152) to which a reset signal (Resetb) is input and outputs an operation control signal (Shift_En), Ethernet interface device having a frame transmission control function. The method of claim 1, The calculator 160 inputs an operation control signal Shift_En to the J input terminal J, a clock signal Pclk to the clock input terminal CK, and a trial start signal Cur_Attempt to the K input terminal K. A JK flip-flop 161 to which the reset input terminal RN is input; A multiplexer (162) outputting a high level when the output of the JK flip-flop (161) is disabled, and a low level when the output of the JK flip-flop (161) is disabled; A first shift register (163) enabled by the operation control signal and latching data input from the multiplexer (162); A second shift register 164 enabled by an operation control signal and storing data input from the first shift register 163 and outputting the data at a next clock Pclk; A third shift register 165 enabled by an operation control signal and storing data input from the second shift register 164 and outputting the data at a next clock Pclk; A fourth shift register 166 enabled by an operation control signal and storing data input from the third shift register 165 and outputting the data at a next clock Pclk; A fifth shift register 167 enabled by an operation control signal and configured to store data input from the fourth shift register 166 and then output the data at a next clock Pclk; A sixth shift register 168 enabled by an operation control signal and configured to store data input from the fifth shift register 167 and then output the data at a next clock Pclk; A seventh shift register (169) enabled by an operation control signal and storing data input from the sixth shift register (168) and outputting the data at a next clock (Pclk); An eighth shift register 170 enabled by an operation control signal and configured to store data input from the seventh shift register 169 and then output the data at a next clock Pclk; A ninth shift register (171) which is enabled by an operation control signal and stores data input from the eighth shift register (170) and outputs the data at a next clock (Pclk); The frame is configured to include a tenth shift register 172 which is enabled by an operation control signal and stores data input from the ninth shift register 171 and outputs the data at a next clock Pclk. Ethernet interface device with transmission control.

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