KR100453170B1 - Method And Apparatus Of Driving Radio Frequency Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a high frequency plasma display panel to simplify a driving circuit for driving an address electrode.

The driving method of the high frequency plasma display panel according to the present invention includes an address electrode and a scan electrode formed between a dielectric layer on a lower plate, and a partition wall formed between the lower plate and the upper plate with a discharge space and partitioning a discharge cell. A method of driving a plasma display panel having a high frequency electrode formed therein, a high frequency base electrode formed on the other partition wall facing the one side partition wall with the discharge cell interposed therebetween, and a phosphor formed on the top plate and the partition walls. Initializing the discharge cell by applying a reset signal to an electrode; Applying a scan signal to the scan electrode and applying a data signal to the address electrode to select the discharge cell; Applying a positive trigger pulse and a negative trigger pulse to only the scan electrode, applying a high frequency voltage to the high frequency electrode, and applying a ground voltage of the high frequency voltage to the high frequency base electrode to cause a high frequency sustain discharge in the selected cell; It includes.

Description

Method and apparatus for driving high frequency plasma display panel {Method And Apparatus Of Driving Radio Frequency Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency plasma display panel, and more particularly, to a method and apparatus for driving a high frequency plasma display panel to simplify a driving circuit for driving an address electrode.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device in which ultraviolet light generated by gas discharge excites a phosphor to generate visible light from the phosphor. PDP has advantages such as thin, light, high-definition large screen and wide viewing angle compared to cathode ray tube (CRT), which has been the dominant display device. In recent years, research has been actively conducted on a radio frequency (“RF”) PDP that can significantly improve discharge efficiency and brightness compared to an AC surface discharge PDP developed in the past. In the RF PDP, electrons vibrating in the discharge space of the discharge cell by the high frequency signal continuously ionize the discharge gas, thereby causing continuous discharge for most of the discharge time. In the PDP, the discharge cells forming the pixel unit are arranged in a matrix to form the entire screen.

1 is a longitudinal sectional view of a panel showing a discharge cell structure of a conventionally developed RF PDP.

Referring to FIG. 1, the RF PDP includes an address electrode 16 formed on the lower substrate 14, a first dielectric layer 18 formed on the lower substrate 14 and the address electrode 16, and an address electrode 16. Scan electrode 20 formed on the first dielectric layer 18 so as to be orthogonal to the second dielectric layer, the second dielectric layer 22 formed on the first dielectric layer 18 and the scan electrode 20, and the second dielectric layer 22. A protective film 24 formed on the barrier layer, a partition wall 26 formed vertically on the protective film 24 to distinguish respective discharge cells, a phosphor 28 applied to an inner wall of the partition wall 26, and a partition wall 26. The upper substrate 30 arranged in parallel with the lower substrate 14 with the gap between them, the high frequency electrode 32 formed on the rear surface of the upper substrate 30 in a direction parallel to the scan electrode 20, and the high frequency electrode 32. The upper dielectric layer 34 formed on the upper substrate 30, and the discharge space 36 is formed surrounded by the upper substrate 30, the lower substrate 14 and the partition wall (26). Data pulses and scan pulses are applied to the address electrode 16 and the scan electrode 20 to cause address discharge, respectively. The first dielectric layer 18 insulates the address electrode 16 and the scan electrode 20. In the second dielectric layer 22, wall charges are accumulated during address discharge. The protective film 24 protects the dielectric layer 22 from sputtering during discharge to extend the life of the discharge cell, and also generates secondary electrons during discharge to improve discharge efficiency. The partition wall 26 formed vertically on the lower plate 10 distinguishes each discharge cell and serves to suppress mutual interference between adjacent discharge cells. The high frequency electrode 32 is applied with a high frequency driving voltage for causing high frequency sustain discharge. The phosphor 28 is excited by vacuum ultraviolet rays generated during sustain discharge to generate visible light.

2 is a diagram illustrating a driving waveform applied to each electrode to drive the RF PDP having such a discharge cell structure. A conventional RF PDP discharge process will be described with reference to FIG. 2. First, a high frequency signal is continuously supplied to the high frequency electrode 32. When no charged particles are generated in the discharge space 36 of the discharge cell, even if a high frequency signal is applied to the high frequency electrode 32, no discharge occurs. In the address period in which the data pulse is supplied to the address electrode 16 and the scan pulse is supplied to the scan electrode 20, an address discharge for cell selection occurs between the address electrode 16 and the scan electrode 20. In this process, charged particles such as electrons are generated in the discharge space 36 of the selected discharge cell, and wall charges are accumulated in the second dielectric layer 22. The accumulated wall charges serve to lower the discharge voltage during sustain discharge. In the sustain period, electrons having relatively high mobility among the charged particles generated in the discharge space 36 are discharged during the sustain period. The sustained discharge is continuously generated while vibrating by the high frequency signal supplied to the. The high frequency signal rapidly changes in polarity to generate a high frequency electric field in the discharge space 36. The high frequency electric field causes the electrons in the discharge space 36 to vibrate up and down. In the three-electrode structure shown in FIG. 1, since the scan electrode 20 serves as a ground electrode for the high frequency signal during sustain discharge, electrons in the discharge space 36 are transferred to the high frequency electrode 32 and the lower plate 10 in the upper plate 12. It vibrates up and down between the scan electrodes 20 in FIG. The vibrating electrons excite the discharge gas charged in the discharge space 36 continuously and cause a discharge. Ultraviolet rays generated in the discharge space 36 during discharge excite the phosphor 28 coated on the inner wall of the partition wall 26 to generate visible light, thereby realizing an image of the PDP. An erase pulse (not shown) must be supplied to the electrode 16 or the scan electrode 20. The erasing pulse applies an electric field in the discharge space 36 to attract the electrons in the discharge space 36 toward one electrode so that the electrons in the discharge space 36 no longer vibrate.

However, the problem with the conventional RF PDP having a three-electrode structure is that the driving method is complicated because the scan electrode 20 is commonly used for the address discharge and the high frequency sustain discharge, and electrical interference occurs between the two discharges. to be. In particular, the high frequency signal applied to the discharge cell affects the AC voltage source supplying the scan pulse through the scan electrode 20, so that the address discharge is affected by the high frequency signal. Accordingly, a four-electrode RF PDP has been developed that separates the functions of the scan electrode 20 into a scan electrode and a high frequency ground electrode and inserts a high frequency electrode into the partition wall.

3 is a longitudinal cross-sectional view of a panel showing a discharge cell structure of a four-electrode RF PDP.

Referring to FIG. 3, the discharge cells of the four-electrode RF PDP include a high frequency electrode 56a and a high frequency base electrode 56b formed inside the partition walls 54 facing each other in the longitudinal direction of the discharge cell, and the partition wall 54. Phosphor 58 applied to a predetermined region on side surfaces of the substrate and upper substrate 42, and a scan electrode 50 formed on the lower substrate 44 in the same direction as the address electrode 46 and the high frequency electrode 56a. . The address electrode 46 to which data pulses are applied during address discharge is formed on the lower substrate 44 such that the width increases by a predetermined area for each discharge space. On the lower substrate 44 on which the address electrode 46 is formed, a first dielectric layer 48 is formed on the entire surface to insulate the scan electrode 50 from the address electrode 46, and the scan pulse is applied upon the address discharge thereon. The electrode 50 is formed in the same direction as the high frequency electrode 56a and the high frequency base electrode 56b. On the first dielectric layer 48 having the scan electrode 50 formed thereon, a second dielectric layer 52 for forming wall charges during discharge is formed on the entire surface. A partition wall 54 is formed on the second dielectric layer 52 to distinguish each discharge cell and prevent electrical and optical interference between adjacent discharge cells. The high frequency electrode 56a and the high frequency base electrode 56b are respectively formed in the two partition walls 54 facing in the longitudinal direction of the discharge cell to generate a high frequency sustain discharge. The inner wall of the partition wall 54 in contact with the discharge space is coated with a phosphor 58 which is excited by ultraviolet rays generated during discharge to generate visible light. A protective film (not shown) is formed on the second dielectric layer 52 exposed to the discharge space to protect the dielectric layer 52 from sputtering during discharge. Phosphors 58 are coated on the rear surface of the upper substrate 42 facing the lower substrate 44 with the partition 54 therebetween and the inner surface of the partition 54. Unlike the conventional structure shown in FIG. 1, no electrode is formed on the upper substrate 42.

The height of the partition wall 54 is made relatively low to the extent similar to the width of the discharge cell, is formed about 500㎛, the width of the partition 54 is formed about 80㎛. In addition, the distance between the partition walls 54, that is, the width of the discharge cells is formed to about 1080㎛. The high frequency electrode 56a and the high frequency base electrode 56b are formed at the intermediate height of the partition wall 54. In order to form an electrode in the partition wall 54, first, a height of about the middle of the partition wall to be finally formed by using a conventional partition wall manufacturing method on the lower plate 44 on which the second dielectric layer 52 is formed (about 220 A partition is formed. Then, the high frequency electrode 56a and the high frequency base electrode 56b are formed on the intermediate height partition walls, respectively. At this time, the height of the high frequency electrode 56a and the high frequency base electrode 56b is about 60 μm, and a sputtering method, a screen printing method, or the like may be used as the electrode forming method. The barrier rib 54 is formed on the intermediate height barrier rib on which the high frequency electrode 56a and the high frequency base electrode 56b are formed by screen printing or the like to have a final height.

In addition, the width of the address electrode 46 is about 200 μm, and the width of the scan electrode 50 is about 180 μm. In this case, the scan electrode 50 is formed to be spaced apart from the address electrode 46 in the width direction by about 60 μm when formed on the lower substrate 44.

4 is a diagram illustrating a driving device for driving the RF PDP of FIG. 3.

Referring to FIG. 4, first, an address discharge for selecting a discharge cell is generated by an address pulse and a scan pulse supplied to the address electrode 46 and the scan electrode 50 of the PDP 66, respectively. The address pulse is generated from the address pulse generator 59b and supplied to the address electrode 46, and the scan pulse is generated from the scan pulse generator 59c and supplied to the scan electrode 50, respectively. In addition, the high frequency sustain discharge is generated between the high frequency electrode 56a and the high frequency base electrode 56b. The high frequency signal is generated from the high frequency generator 59a and supplied to the high frequency electrode 56a, and the ground level signal of the high frequency signal applied to the high frequency electrode 56a via the ground plate 68 is supplied to the high frequency base electrode 56b. Continue to apply.

5 is a driving waveform diagram of the discharge cell shown in FIG.

Referring to FIG. 5, first, in the reset period RPD for supplying the reset pulse RP to the scan electrode 50, all the discharge cells are initialized by erasing wall charges in the scan electrode 50.

Thereafter, in the address period APD, which supplies a data pulse to the address electrode 46 and a scan pulse to the scan electrode 50, an address discharge for cell selection occurs between the address electrode 46 and the scan electrode 50. In this process, charged particles such as electrons are generated in the discharge space of the selected discharge cell, and wall charges are accumulated in the second dielectric layer 52. Accumulated wall charges lower the discharge voltage during sustain discharge. After the address discharge is completed, in the sustain discharge period SPD, electrons having relatively high mobility among the charged particles generated in the discharge space are induced by the high frequency signal supplied to the high frequency electrode 56a to continuously generate the sustain discharge. . At this time, triggering signals TPa and TPs for starting high frequency sustain discharge are applied to the address electrode 46 and the scan electrode 50. This is because even when the high frequency signal is applied to the high frequency electrode 56a, the level of the high frequency signal is not large enough to start the discharge in the addressed discharge cell, so that a high frequency discharge cannot be generated by itself. Therefore, the triggering signals TPa and TPs are signals for inducing full high frequency sustain discharge. The high frequency sustain discharge occurs between the high frequency electrode 56a and the high frequency base electrode 56b. The high frequency signal generates an electric field whose direction alternates in the longitudinal direction of the high frequency discharge cell in which the polarity is quickly reversed in the discharge space. Accordingly, the electrons in the discharge space vibrate along the long path between the partition walls 54 by the high frequency electric field. The vibrating electrons excite the discharge gas charged in the discharge space continuously and generate a discharge. Ultraviolet rays generated during high frequency sustain discharge excite the phosphor 58 formed on the partition 54 and the upper substrate 42 to generate visible light, thereby realizing an image of the PDP.

FIG. 6 is a detailed view of the address generator 59b shown in FIG.

Referring to FIG. 6, the address generator 59b includes an address electrode driving integrated circuit (hereinafter referred to as “IC”) 60 connected to the PDP 66 and an input terminal of the address electrode driving IC 60. A photo coupler 64 connected to the photocoupler 64 and an address printed circuit board connected to the output terminals of the address electrode driver IC 60 and the photocoupler 64 (hereinafter referred to as a PCB) 62 It is provided.

The address PCB 62 serves to relay various control signals supplied from a timing controller (not shown) and drive voltage signals from a power supply unit (not shown) to the address driver ICs 60.

The address driving ICs 60 supply the data signal and the triggering signal to the address electrodes 46 in response to the control pulse output from the address PCB 62.

The photo coupler 64 is connected to the input terminal of the address driving ICs 60 to prevent side operation of the address driving ICs 60. When the trigger pulse TPa is made to the address electrodes 46 for the trigger discharge in the sustain period SPD, the address driver ICs 60 generate the trigger voltage (0 to 250V) from the address PCB 62. By the address driving input signals of 0 to 5V are affected, it does not operate. As a result, the input terminals of the address driver ICs 60 are not affected by the trigger voltage of 0 to 250V using the photo coupler 64.

FIG. 7 is a detailed view of the address PCB 62 shown in FIG.

Referring to FIG. 7, the address PCB 62 includes an energy recovery circuit 63, and a data voltage supply unit 64 connected between the energy recovery circuit 63 and the address electrode 46. The energy recovery circuit 63 charges the voltage of the address electrode 46 by using the charging voltage of the external capacitor Cexa and LC resonance, and recovers energy from the address electrode 46 to charge the external capacitor Cexa. . The energy recovery circuit 63 is operated at the time of supplying the trigger voltage Vt and the data voltage Vdata.

5, the operation of the address PCB 62 will be described. In the address period, the predetermined data pulse voltage Vdata is supplied to the address electrode 46 in synchronization with the scan pulse SP of the scan electrode 50. To this end, the twenty-second switch Q22 is turned off at the beginning of the address period, and the twenty-fifth switch Q25 is turned on in response to the control signal dc to thereby turn the data voltage Vdata into the address electrode 46. Is supplied.

The trigger pulse TPa is supplied to the scan electrode 50 so that the trigger discharge occurs after the address discharge. At this time, the trigger pulse TPa is supplied using the energy recovery circuit 63.

The energy recovery circuit 63 supplies the recovered voltage to the address electrode 46 to reduce excessive power consumption during trigger discharge of the sustain period SPD.

Meanwhile, as shown in FIG. 8, the trigger pulse TP may be supplied using only the twenty-first switch Q21.

However, since the number of address electrode lines in the 20-inch PDP has as many as 60 inputs, the number of photo couplers 64 in the address generator 59b of FIGS. 4 and 6 is also required. In addition, as PDPs become larger and larger, more photocouplers are added. As a result, the same number of photocouplers 64 must be used at the address electrode driving IC input terminal in order to trigger the discharge on the address electrode.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a high frequency plasma display panel which can simplify an address driving circuit in a driving apparatus of a high frequency plasma display panel having a four electrode structure.

1 is a longitudinal sectional view of a panel showing a discharge cell structure of a conventionally developed high frequency plasma display panel.

FIG. 2 is a waveform diagram showing a driving waveform applied to each electrode of the discharge cell in order to drive the discharge cell shown in FIG.

3 is a longitudinal cross-sectional view of a panel showing a discharge cell structure of a conventional four-electrode high frequency plasma display panel;

4 is a view showing a driving device of the high frequency plasma display panel shown in FIG.

5 is a driving waveform diagram of the discharge cell shown in FIG.

FIG. 6 shows details of the address generator shown in FIG. 4; FIG.

FIG. 7 is a detailed view of the address printed circuit board shown in FIG. 6; FIG.

8 is a diagram showing another example of the address printed circuit board shown in FIG. 6;

9 is a driving waveform diagram of a high frequency plasma display panel according to an exemplary embodiment of the present invention.

FIG. 10 is a view showing a driving circuit for driving the scan electrode shown in FIG. 9; FIG.

Fig. 11 shows a driving circuit for driving an address electrode.

<Description of Symbols for Main Parts of Drawings>

14,44: lower substrate 16,46: address electrode

18,22,34,48,52: Dielectric layer 20,50: Scanning electrode

24: shield 26,54: bulkhead

28,58: phosphor 30,42: upper substrate

32,56a: high frequency electrode 36,64: discharge space

56b: high frequency base electrode 59a: high frequency generator

59b: address pulse generator 59c: scan pulse generator

60: address driver IC 62: address PCB

64: photocoupler 70: scan drive IC

63, 71: energy recovery circuit 64: data voltage supply unit

72: setup supply 73: set down supply

74: scan reference voltage supply 75: scan voltage supply

In order to achieve the above object, the driving method of the RF PDP according to the present invention is formed between an address electrode and a scan electrode formed between a dielectric layer on a lower plate, and a discharge space between the lower plate and the upper plate to partition discharge cells. In the driving method of the PDP having a partition wall, a high frequency electrode formed on one side partition wall, a high frequency base electrode formed on the other side wall facing the one side partition wall with the discharge cell interposed therebetween, and a phosphor formed on the top plate and the partition walls. The method may include: initializing the discharge cell by applying a reset signal to the scan electrode; Applying a scan signal to the scan electrode and applying a data signal to the address electrode to select the discharge cell; Applying a positive trigger pulse and a negative trigger pulse to only the scan electrode, applying a high frequency voltage to the high frequency electrode, and applying a ground voltage of the high frequency voltage to the high frequency base electrode to cause a high frequency sustain discharge in the selected cell; The voltage of the negative trigger pulse is the same as the voltage of the scan electrode. The driving apparatus of the RF PDP according to the present invention includes an address electrode, a scan electrode, and a discharge space formed on a lower plate with a dielectric layer interposed therebetween. A high frequency base electrode formed between the lower plate and the upper plate to partition a discharge cell, a high frequency electrode formed on one side wall, and a high frequency base electrode formed on the other side wall facing the one side wall with the discharge cell interposed therebetween; A PDP having phosphors formed on the partition walls; A scan driver for applying a reset signal to the scan electrode during a reset period and applying a scan signal to the scan electrode during an address period, and then applying a positive trigger pulse and a negative trigger pulse to the scan electrode during a sustain discharge period; An address driver which applies a data signal to the address electrode during the address period; And a high frequency driving unit configured to apply a high frequency voltage to the high frequency electrode and apply a ground voltage of the high frequency voltage to the high frequency base electrode during the sustain discharge period. The address discharge, the high frequency electrode, and the high frequency base electrode include the sustain discharge. Trigger pulse is not applied during the period.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 9 to 11.

The discharge cell structure of the RF PDP applied to the present invention is substantially the same as the discharge cell shown in FIG. 3, and is driven through a driving circuit similar to the driving device of the RF PDP shown in FIG.

9 is a driving waveform diagram of an RF PDP discharge cell according to an embodiment of the present invention.

3, 4 and 9, the reset pulse RP of the ramp-up waveform is sequentially supplied to the scan electrode 50 of the reset period RPD followed by the reset pulse RP of the ramp-down waveform. do. At this time, the reset pulse (-RP) of the ramp-down waveform drops to the scan reference voltage (-Vm) of negative polarity (-). In this case, all the discharge cells are initialized by erasing wall charges in the scan electrode 50.

In the address period APD, the negative scan pulse SP and the positive data pulse DP are supplied to the scan electrodes 50 and the address electrodes 46 so as to be synchronized with each other. do. The address discharge is generated by the scan pulse SP and the data pulse DP. In this process, charged particles such as electrons are generated in the discharge space of the selected discharge cell, and wall charges are accumulated in the second dielectric layer 52. Accumulated wall charges lower the discharge voltage during sustain discharge.

In the sustain discharge period SPD in which the address discharge is completed, relatively high mobility electrons among the charged particles generated in the discharge space are supplied to the high frequency electrode 56a and a high frequency signal supplied to the high frequency base electrode 56a. The high-frequency sustain discharge is generated between the partition walls 54 while vacuuming by the high-frequency electric field generated between the ground voltages of. The positive and negative triggering signals TP and -TP for starting the high frequency sustain discharge are applied only to the scan electrode 50. This is because even when the high frequency signal is applied to the high frequency electrode 56a, the level of the high frequency signal is not large enough to start the discharge in the addressed discharge cell, so that a high frequency discharge cannot be generated by itself. Therefore, the triggering signals TP and -TP are signals for attracting full-scale high frequency discharges. Here, sustain discharge occurs between the high frequency electrode 56a and the high frequency base electrode 56b which face each other in the longitudinal direction of the discharge cell. The high frequency signal with alternating polarity generates an electric field whose direction alternates in the longitudinal direction of the discharge cell in the discharge space. Accordingly, the electrons in the discharge space vibrate in the longitudinal direction of the discharge cell by the electric field, unlike in the conventional structure. The vibrating electrons excite the discharge gas charged in the discharge space continuously and cause discharge. The ultraviolet light generated in the discharge space during the discharge excites the phosphor 58 formed on the partition 54 and the upper substrate 42 to generate visible light, thereby realizing an image of the PDP.

The triggering signals TP and -TP_ applied only to the scan electrode 50 are alternately applied with a positive (+) and a negative (-) trigger pulse TP in an alternating current form. The voltage of is equal to the voltage of the scan pulse SP.

FIG. 10 is a diagram illustrating a driving circuit for driving the scan electrode illustrated in FIG. 9.

Referring to FIG. 10, the scan electrode driver according to the present invention may include an energy recovery circuit 71, a fourth switch Q4 connected between the energy recovery circuit 71, and a third node n3, and a fourth switch. A scan reference voltage supply 74 and a scan voltage supply 75 for connecting the Q4 and the scan driver IC 70 to generate the scan pulse SP, the fourth switch Q4 and the scan voltage supply And a setup supply 72 and a set down supply 73 for generating setup / down waveforms RP, -RP.

The scan driving IC 70 is connected in a push-pull form, and the tenth and eleventh switches Q10, which receive a voltage signal from the energy recovery circuit 70, the scan reference voltage supply 74, and the scan voltage supply 75, Q11). The output line between the tenth and eleventh switches Q10 and Q11 is connected to one of the scan electrode lines 50.

The energy recovery circuit 71 includes an external capacitor Cex for charging the voltage recovered from the scan electrode line 50, switches Q12 and Q13 connected in parallel to the external capacitor Cex, and a first node ( The inductor L_y connected between n1 and the second node n2, the first switch Q1 connected between the sustain voltage supply Vs and the second node n2, and the second node n2. And a second switch Q2 connected between the ground terminal and the ground terminal GND.

The energy recovery circuit 71 supplies a trigger pulse TP of the scan electrode line 50 to the sustain period SPD. While the voltage of the scan electrode line 50 is charged and discharged by the energy recovery circuit 71, the fourth switch Q4 to form a current path between the energy recovery circuit 51 and the scan driving IC 52. Keeps on.

The scan reference voltage supply 74 is composed of a sixth switch Q6 connected between the third node n3 and the scan voltage source -Vy. The sixth switch Q6 switches in response to the control signal yc supplied in the address period, thereby supplying the scan voltage -Vy to the scan driving IC 70.

The scan voltage supply unit 75 includes eighth and ninth switches Q8 and Q9 connected in series between the scan voltage source Vsc and the fourth node n4. The eighth and ninth switches Q8 and Q9 are switched in response to the control signal SC supplied in the address period to supply the scan voltage Vsc to the scan driving IC 70.

The setup supply 72 is composed of a diode and a third switch Q3 connected between the setup voltage source Vsetup and the third node n3. The diode serves to block a reverse current flowing from the third node n3 toward the setup voltage source Vsetup. The third switch Q3 serves to supply the setup waveform RP. The slope of the setup waveform RP is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the third switch Q3, that is, the gate terminal. Therefore, the slope of the setup waveform RP is adjusted by adjusting the resistance value of the variable resistor R1.

The set-down supply 73 includes a fifth switch Q5 connected between the third node n3 and the scan voltage source -Vy. The fifth switch Q5 serves to supply the setdown waveform (-RP). The slope of the set-down waveform (-RP) is determined by the RC time constant value of the RC time constant circuit connected to the control terminal of the fifth switch Q5, that is, the gate terminal. Therefore, the slope of the set-down waveform (-RP) is adjusted by adjusting the resistance value of the variable resistor (R2).

The scan electrode driver according to the present invention further comprises a seventh switch Q7 connected to the scan reference voltage supply 74 and the scan voltage supply 75 via the third node n3 and the fourth node n4, respectively. Equipped. The seventh switch Q7 switches the scan voltage Vsc supplied to the scan driving IC 70 in response to the control signal Dic_updn.

9 and 10, the operation of the scan driver according to the present invention will be described. In the reset period, the setup waveform RP and the set-down waveform (-RP) are continuously supplied to the scan electrode 50. To this end, the third, fourth and fifth switches Q3, Q4 and Q5 are sequentially turned on in response to the control signals setup and setdn, respectively. Then, the positive setup voltage Vsetup and the negative scan reference voltage (-Vy) are passed through the third, fourth and fifth switches Q3, Q4 and Q5 and the eleventh switch Q11 of the driver IC 70. ) Is sequentially supplied to the scan electrode 50. The setup waveform RP rises to the setup voltage Vsetup and the set down waveform -RP falls to the voltage -Vm by the negative scan reference voltage -Vy.

The setdown waveform (-RP) performs the setdown operation through the fifth switch Q5, the ninth switch Q9, and the internal diodes of the driving IC 70 up to the base voltage source GND. Subsequently, from the base voltage level, the ninth switch Q9 is turned off and the eleventh switch Q11 is turned on to continue the setdown operation.

As described above, driving the divided sections causes the fourth node n4 to be lowered to the ground or less when the setdown operation is continuously performed through the ninth switch Q9. This is because a short circuit with the ground is performed through the internal diodes of the fourth switch Q4 and the second switch Q2.

Since the setup waveform RP rises to the setup voltage Vsetup at a predetermined slope, the setup waveform RP generates wall charges required in the scan without large discharge in the cell. In the falling section of the setup waveform RP, the inclination of the energy recovery circuit 71 is operated to smoothly adjust its slope. Since the falling slope of the setup waveform (RP) is gentle, the cells do not self-erase.

Thereafter, in the address period APD, which supplies a data pulse to the address electrode 46 and a scan pulse to the scan electrode 50, an address discharge for cell selection occurs between the address electrode 46 and the scan electrode 50. In this process, charged particles such as electrons are generated in the discharge space of the selected discharge cell, and wall charges are accumulated in the second dielectric layer 52. Accumulated wall charges lower the discharge voltage during sustain discharge.

In the sustain discharge period after the address discharge is completed, electrons having relatively high mobility among the charged particles generated in the discharge space are induced by the high frequency signal supplied to the high frequency electrode 56a to continuously generate sustain discharge. The triggering signals TP and -TP for starting the high frequency sustain discharge are applied only to the scan electrode 50. This is because even when the high frequency signal is applied to the high frequency electrode 56a, the level of the high frequency signal is not large enough to start the discharge in the addressed discharge cell, so that a high frequency discharge cannot be generated by itself. Therefore, the triggering signal TP is a signal for attracting full-scale high frequency discharge. The high frequency sustain discharge occurs between the high frequency electrode 56a and the high frequency base electrode 56b which face each other in the longitudinal direction of the discharge cell, and the electrons vibrate therebetween. The vibrating electrons excite the discharge gas charged in the discharge space continuously and cause discharge.

In the triggering signal applied only to the scan electrode 50, the positive trigger pulse TP and the negative trigger pulse (-TP) are alternately applied. At this time, the positive trigger pulse TP is applied by the energy recovery circuit 71, and the negative trigger pulse -TP is applied to the scan voltage supply unit 75 which supplies the scan pulse SP in the address period APD. Is applied by.

11 is a view showing a driving circuit for driving an address electrode.

Referring to FIG. 11, the address driving circuit is an address driving IC (not shown) connected to a panel, and is composed of a twenty-first switch Q21 and a diode between the data voltage source Vdata and the panel. The address driving circuit applies the data pulse DP in the address period APD. The data pulse DP is controlled by the control signal DC input to the control terminal of the twenty-first switch Q21.

As described above, the method and apparatus for driving the RF PDP according to the present invention can remove the driving circuit for applying the trigger pulse from the address driving circuit by supplying the trigger pulse in the AC form only to the scan electrode. As a result, the driving circuit for driving the address electrode can be simplified and the manufacturing cost can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

An address electrode and a scan electrode formed on a lower plate with a dielectric layer interposed therebetween, a partition wall formed between the lower plate and the upper plate with a discharge space to partition discharge cells, a high frequency electrode formed on one side wall, and the discharge cell therebetween. In the driving method of the plasma display panel having a high frequency base electrode formed on the other side wall facing the one side partition wall, and the phosphor formed on the upper plate and the partition walls, Initializing the discharge cell by applying a reset signal to the scan electrode; Applying a scan signal to the scan electrode and applying a data signal to the address electrode to select the discharge cell; Applying a positive trigger pulse and a negative trigger pulse to only the scan electrode, applying a high frequency voltage to the high frequency electrode, and applying a ground voltage of the high frequency voltage to the high frequency base electrode to cause a high frequency sustain discharge in the selected cell; Method for driving a high frequency plasma display panel comprising a. delete The method of claim 1, And the voltage of the negative trigger pulse is the same as that of the scan electrode. delete An address electrode and a scan electrode formed on a lower plate with a dielectric layer interposed therebetween, a partition wall formed between the lower plate and the upper plate with a discharge space to partition discharge cells, a high frequency electrode formed on one side wall, and the discharge cell therebetween. A plasma display panel having a high frequency base electrode formed on the other partition wall facing the one partition wall, and a phosphor formed on the upper plate and the partition walls; A scan driver for applying a reset signal to the scan electrode during a reset period and applying a scan signal to the scan electrode during an address period, and then applying a positive trigger pulse and a negative trigger pulse to the scan electrode during a sustain discharge period; An address driver which applies a data signal to the address electrode during the address period; A high frequency driving unit for applying a high frequency voltage to the high frequency electrode and applying a ground voltage of the high frequency voltage to the high frequency base electrode during the sustain discharge period; And a trigger pulse is not applied to the address electrode, the high frequency electrode, and the high frequency base electrode during the sustain discharge period. delete delete