KR100452312B1 - Memory device using GTO and its manufacturing method - Google Patents

Abstract

A memory device using GTO of the present invention includes a substrate of a first conductivity type; A device isolation region for separating the devices; A gate electrode formed on the substrate between the device isolation regions; A gate insulating film surrounding the gate electrode; First impurity regions of a second conductivity type formed on both sides of the substrate with respect to the gate electrode to form a channel when an arbitrary bias voltage is applied to the gate electrode; A second impurity region of a first conductivity type formed in one side of the first impurity region with respect to the gate electrode; A third impurity region of a first conductivity type formed under the isolation region to form a GTO thyristor together with a first conductivity type substrate, the first impurity region and a second impurity region; It is configured to include a metal wiring layer for wiring between the elements, it is possible to reduce the chip area of the memory to 1/2 of the existing DRAM, the manufacturing process is easy and there is an effect that can be driven at a low current.

Description

Memory device using GTO and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device using a GTO (Gate turn off Thyrister) and a manufacturing method thereof.

Since the development of 1K DRAM (DRAM) in the 1970s, the DRAM has led the memory market, and has made rapid progress every year due to various efforts for miniaturization and high integration of the DRAM. Research and development of DRAMs in China is active.

However, for the miniaturization and high integration of these DRAMs, submicron design rules are used, and the development of materials with high dielectric constant to increase capacitance, the complicated structure to increase the storage electrode area, and the highly sophisticated equipment for multilayer wiring. In addition to the burden of process technology development, various problems such as parasitic transistor and junction capacitance due to miniaturization have to be solved.

Accordingly, an object of the present invention is to reduce the chip area to 1/2 of the conventional DRAM by using a GTO thyristor that can be turned off by simply changing the direction of the trigger current, in order to solve the problems of the prior art. It is to provide a memory device using GTO that is easy to process and can be driven with low current.

Another object of the present invention is to provide a manufacturing method for efficiently manufacturing a memory device using the GTO.

A memory device using GTO of the present invention for achieving the above object comprises: a substrate formed by ion implantation with a first conductivity type impurity; A device isolation region formed on the substrate to separate the devices; A gate electrode surrounded by a gate insulating film on the substrate between the device isolation regions; First impurity regions formed on both sides of the substrate between the gate electrode and the device isolation region to have a depth smaller than that of the device isolation region, and ion-implanted with a second conductivity type impurity opposite to the first conductivity type impurity; A second impurity region formed by ion implantation into the first conductivity type impurity from a surface of the substrate to a predetermined depth in a first impurity region around the gate electrode; A third impurity region ion-implanted into the second conductivity type impurity under the device isolation region adjacent to the second impurity region and formed to be spaced apart from the first impurity region; And a metal wiring layer formed independently on both sides of the gate electrode and the gate insulating layer on the first impurity region and the second impurity region to interconnect each element.

According to another aspect of the present invention, there is provided a method of fabricating a memory device using GTO, the method including: forming a gate electrode on a substrate of a first conductivity type; Forming a first impurity region by ion implanting a second conductivity type impurity into the substrate using the gate electrode as a mask; Forming a second impurity region by ion implanting a second conductivity type impurity into one first impurity region by pairing two adjacent first impurity regions; After forming a trench from the surface of the substrate to a predetermined depth in the substrate both in the center of the second impurity region and in the center of the first impurity region in which the second impurity region is not formed, ion implanted impurities are implanted into the lower portion of the trench. To form a third impurity region; Filling the trench with an insulator to form an isolation region; And forming a metal wiring layer to cover between the first impurity regions on both sides of the device isolation region and between the second impurity regions on both sides of the other device isolation region.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

GTO is one of the thyristors of the pnpn junction structure, and the basic thyristors require reverse bias by external circuit to turn off, but they can be turned off only by changing the direction of the trigger current. have.

Accordingly, in the present invention, as shown in FIG. 1, the GIO 1 is connected in a forward direction between the word line W / L and the resistor 2 having one side grounded, and a drain bit is formed in the gate of the Gthio. A source of transistor 3 connected to the line B / L and a gate connected to the word line is connected to control the turn-off of the Gthio.

In the memory device using the GEO of the present invention connected as described above, information is stored in accordance with the voltage level across the resistor (2).

That is, when a high level voltage is applied to the word line, the transistor 3 is turned on, and data of the bit line is applied to the gate of the Gthio. When the data of the bit line is forward, the resistor 2 Since the current flows to the ground, the voltage across the resistor 2 is at a low level, and the voltage is maintained until a reverse current is applied to the gate of the gate. ) Is off, so that the voltage applied to GIO through the word line is applied to the voltage across the resistor 2 as it is, and becomes high level.

FIG. 2 is a cross-sectional view illustrating a memory device using the Gthio of FIG. 1, wherein a first p-type conductive layer 4, a first n-type conductive layer 5 formed on the first conductive layer 4, and the In the gate electrode 6 formed on the first n-type conductive layer 5, the gate insulating film 9 for insulating the gate electrode 6, and the first n-type conductive layer 5 on both sides of the gate electrode. The second p-type conductive layer 7 formed thereon and the second n-type conductive layer 8 formed in the second p-type conductive layer on one side and connected to a grounded resistor on one side thereof.

That is, the gate electrode 6 and the second p-type conductive layer 7 form one transistor, and the first p-type conductive layer 4, the first n-type conductive layer 5, and the second p are The type conductive layer 7 and the second n-type conductive layer 8 form a thion.

3 to 6 illustrate a fabrication procedure of a memory device using GTI capable of minimizing an area based on the structure of FIG. 2. First, in FIG. 3, n-type impurities (eg, first conductivity type impurities) are used. First, a gate oxide film (not shown) is grown on a substrate doped with a silicon oxide, and then, for example, polysilicon is deposited on the gate oxide film as a conductive material to a predetermined thickness, and then a photo-etch mask is formed on the photoresist and applied thereto. The gate electrode 12 is formed by etching the deposited polysilicon.

After removing the photolithography mask, a p-type impurity (eg, a second conductivity type) is ion-implanted into the substrate using the gate electrode 12 as a mask to form a first impurity region 13. An n-type impurity is ion-implanted into the impurity region 13 to form a second impurity region 14, and the second impurity region 14 and the non-existing second impurity region 14 are alternately located in the first impurity region 13.

That is, when the two adjacent first impurity regions 13 are paired, the second impurity regions 14 necessarily exist in the first impurity regions in the same direction.

Subsequently, in FIG. 4, both the center of the second impurity region 14 and the center of the first impurity region 13 in which the second impurity region is not formed are etched from the substrate surface to a predetermined depth in the substrate to form the trench 15. do.

Subsequently, in FIGS. 5 and 6, p-type impurities are implanted into the lower portion of the trench to form the third impurity region 16, and then, for example, silicon nitride or silicon oxide is embedded in the trench to form a device isolation region ( 17), and subsequently, an insulating film is formed on the entire surface of the resultant, and then selectively etched to form a gate insulating film 18 which surrounds and insulates the gate electrode 12, and then on both sides of the device isolation region 17. A metal wiring layer 19 is formed of aluminum or an aluminum alloy so as to cover between the first impurity regions 13 and the second impurity regions 14 on both sides of the other device isolation region.

Here, the gate electrode 12 and the first impurity region 13 on both sides of the gate electrode 12 serve as a source / drain region to form a transistor, wherein the source / drain region is formed on an existing DRAM. Since only half of the area is required, the area of the entire memory device can be reduced by about half, and the metal wiring layer 19 layer is much wider than that formed in the source / drain region of a conventional DRAM. Therefore, pnpn is easy to manufacture and is composed of the p-type third impurity region 16, the n-type substrate 11, the p-type first impurity region 13, and the n-type second impurity region 14. In the case of Gitio, the current flows predominantly in the dotted line ① rather than the solid line ②, so it can operate with less current.

As described above, according to the present invention, the chip area of the memory can be reduced to one half of the existing DRAM by using the thio, and the manufacturing process can be easily performed and the low current can be driven.

1 is an equivalent circuit diagram of a memory device using GTO according to the present invention.

Fig. 2 is a sectional view showing the basic structure of a memory device using GTO according to the present invention. One

3 to 6 are cross-sectional views illustrating a method of manufacturing a memory device using GTO according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate 12 gate electrode

13: first impurity region 14: second impurity region

15 trench 16: third impurity region

17 device isolation region 18 gate insulating film

19 metal wiring layer

Claims (8)

A substrate formed by ion implantation with a first conductivity type impurity; A device isolation region formed on the substrate to separate the devices; A gate electrode surrounded by a gate insulating film on the substrate between the device isolation regions; First impurity regions formed on both sides of the substrate between the gate electrode and the device isolation region to have a depth smaller than that of the device isolation region, and ion-implanted with a second conductivity type impurity opposite to the first conductivity type impurity; A second impurity region formed by ion implantation into the first conductivity type impurity from a surface of the substrate to a predetermined depth in a first impurity region around the gate electrode; A third impurity region ion-implanted into the second conductivity type impurity under the device isolation region adjacent to the second impurity region and formed to be spaced apart from the first impurity region; GTO (GTO), characterized in that it comprises a; metal wiring layer formed independently on both sides of the gate electrode and the gate insulating film on the first impurity region and the second impurity region for wiring between the elements; Memory elements. 2. The memory device of claim 1, wherein the device isolation region comprises silicon nitride buried from a surface of a substrate to a predetermined depth. The memory device of claim 1, wherein the device isolation region comprises silicon oxide embedded from a surface of a substrate to a predetermined depth. 2. The second impurity region of claim 1, wherein the second impurity region is configured to be adjacent to a second impurity region of another element adjacent to one element isolation region among two device isolation regions for separating one element, and the second impurity therein. And a first impurity region having no region formed so as to be adjacent to the first impurity region of another element adjacent to the other element isolation region. The memory device of claim 1, wherein the metallization layer is formed to cover an upper portion of a second impurity region between adjacent elements and a first impurity region between adjacent elements, respectively. The memory device of claim 1, wherein the first conductivity type impurity is an n type impurity and the second conductivity type impurity is a p impurity. The memory device of claim 1, wherein the first conductivity type impurity is an n type impurity and the second conductivity type impurity is a p type impurity. Forming a gate electrode on the substrate of the first conductivity type; Forming a first impurity region by ion implanting a second conductivity type impurity into the substrate using the gate electrode as a mask; Forming a second impurity region by ion implanting a second conductivity type impurity into one first impurity region by pairing two adjacent first impurity regions; After the trench is formed in the center of the second impurity region and in the center of the first impurity region in which the second impurity region is not formed, the trench is formed from the surface of the substrate to a predetermined depth in the substrate, and then ion implanted impurities are formed in the lower portion of the trench. To form a third impurity region; Filling the trench with an insulator to form an isolation region; Forming a metal wiring layer to cover between the first impurity regions on both sides of the device isolation region and between the second impurity regions on both sides of the other device isolation region, respectively. Manufacturing method.

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