KR100450652B1 - Trench type power MOSFET and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A trench-type power FET(field effect transistor) is provided to avoid a leakage current caused by a tunneling phenomenon at the corner of a trench and increase insulating voltage tolerance of a transistor by diffusing high density impurities of different conductivity types to the corner of the trench to form a dual junction. CONSTITUTION: A body(30) of the second conductivity type is formed on a drain of the first conductivity type. A trench(84) penetrates the body to expose the drain. A gate oxide layer is formed on the trench. A high density source(40) of the first conductivity type is formed at the upper corner of the trench. A voltage distribution layer(50) and the high density source forms a junction. The voltage distribution layer is formed in the high density source and floated from an outer power source. The trench is filled with a gate. The gate and the voltage distribution layer are covered with an insulation layer. A source electrode in contact with the source is formed.

Description

Trench type power MOSFET and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power device and a method for manufacturing the same, and more particularly, to a trench type power MOSFET capable of dispersing a voltage applied to a corner of a trench and a method for manufacturing the same.

Power MOS FETs are unipolar devices with MOS structures. Compared to bipolar transistors, it has faster switching speed, higher thermal stability, higher power gain at high input impedance, and ease of use.It is widely used in home appliances such as OA equipment, electronics, and general industrial equipment. It is adopted in the field.

The chip structure of the power MOS FET includes a lateral structure (LMOS) and a trench structure, and the trench structure includes V Grooved MOS (VMOS), UMOS, and double diffused MOS (DMOS).

In the trench structure, the drain is disposed on the lower surface of the semiconductor substrate and the source is disposed on the upper surface, and the gate is disposed on the trench which is dug into the surface of the semiconductor substrate. For this reason, the current flows in the longitudinal direction through the longitudinal channel.

In order to form a power MOSFET having a trench structure, a process of forming a trench and growing an oxide film on the inner wall of the trench is essential. By the way, when the thermal oxidation process is performed after the trench formation, the oxide film tends to grow thinner at the corner portions of the trench than at other portions, and when the voltage (VGS) is applied, the electric field applied to this portion is applied to the other portions. It is higher than the electric field taken. As described above, the trench structure has a lower dielectric breakdown voltage of the oxide film as compared with the lateral structure.

The above-described phenomenon in which the oxide film is thinly formed at the corners of the trench has a close relationship with the reliability of the oxide film, ESD, and the like, which causes a serious defect in the device.

Various methods have been proposed to improve the oxide film thinning at the trench edges as described above, which is a method of growing the oxide film at high temperature, wet etching after trench formation, and chemical dry etching (CDE). The method of rounding the corners and the method of increasing the thickness of the oxide film at the corners by performing a thermal oxidation process after forming a high concentration of impurity layer in the trench corners.

1 is a cross-sectional view illustrating a bus line of a conventional trench type power MOSFET, and a method of increasing an oxide film thickness at a corner by forming a high concentration impurity layer at a corner of a trench and performing thermal oxidation.

This utilizes the phenomenon that the oxide film growth rate in the region where the impurity concentration is high is faster than in other regions. In other words, if the thermal oxidation process is performed after the high concentration of impurity layer 40 is formed in the trench corners, the oxide film growth rate at this portion is faster than that at the other portions, thereby improving the oxide film thinning at the trench edges as described above. can do.

In Fig. 1, reference numeral 10 denotes an N + drain, "20" denotes an N- epi layer, "30" denotes a P-body, "40" denotes an N + high concentration impurity layer, and "60". Is an oxide film, and "70" is a bus line.

At this time, the N + high concentration impurity layer 40 is formed when the source of the power MOSFET is formed, and is in a floating state.

SUMMARY OF THE INVENTION An object of the present invention is to provide a trench type power MOSFET capable of distributing a voltage applied to a corner of a trench.

Another object of the present invention is to provide a trench type power MOSFET manufacturing method capable of dispersing the voltage applied to the trench corners.

1 is a cross-sectional view showing a bus line portion of a conventional trench type power MOSFET.

2 is a cross-sectional view illustrating a bus line part of a trench type power MOSFET according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a bus line of a trench type power MOSFET according to another exemplary embodiment of the present invention.

4 is a cross-sectional view illustrating a trench type power MOSFET according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a trench type power MOSFET according to another embodiment of the present invention.

6A to 6C are cross-sectional views illustrating a bus line forming method of a trench type power MOSFET according to the present invention, in accordance with a process sequence.

7A to 7D are cross-sectional views illustrating a method for forming a trench type power MOSFET according to the present invention in order of process.

The bus line portion of the trench type power MOSFET according to an embodiment of the present invention includes a first conductive type substrate having a trench, an oxide film formed on the trench surface, and a second high concentration of conductive material formed on a substrate at an upper edge of the trench. A type impurity layer, a voltage dispersion layer formed in the second conductivity type impurity layer and bonded to each other, and a bus line formed to fill the trench.

In this case, the voltage dispersion layer has a structure in which a high concentration of the first conductivity type impurity layer and a high concentration of the second conductivity type impurity layer are alternately formed from a junction portion where the substrate and the second conductivity type impurity layer contact each other. It is a high concentration first conductivity type impurity layer bonded to the two conductivity type impurity layer. In addition, the first conductivity type is P type, and the second conductivity type is N type.

The bus line portion of the trench-type power MOSFET according to another embodiment of the present invention includes a body of the second conductivity type formed on the collector of the first conductivity type, a trench formed to expose the collector through the body, A gate oxide film formed on the trench surface, a high concentration first conductivity type source formed at an upper edge of the trench, a voltage dispersion layer formed in and bonded to the high concentration first conductivity type source, and filling the trench And a gate electrode formed on the gate electrode, an insulating layer covering the gate and the voltage dispersion layer, and a source electrode in contact with the source.

In this case, the voltage dispersion layer has a structure in which a high concentration of a second conductivity type impurity layer and a high concentration of a first conductivity type impurity layer are alternately formed from a junction where the body and the source contact each other, or are formed to form a junction with the source. It is a high concentration second conductivity type impurity layer. The first conductivity type is N type, and the second conductivity type is P type.

In the method of manufacturing a trench type power MOSFET according to an embodiment of the present invention, a step of forming a high concentration of a second conductivity type impurity layer by doping a second conductivity type impurity at a high concentration near the surface of the first conductivity type substrate is performed. And forming a voltage dispersion layer in the second conductivity type impurity layer to be bonded to the second conductivity type impurity layer, and penetrating through the voltage dispersion layer and the second conductivity type impurity layer. And forming a trench in which the conductive substrate is partially exposed, forming an oxide film on the trench surface, and forming a bus line in which the trench is buried.

At this time, the step of forming the voltage dispersion layer is a step of doping a high concentration of the first conductivity type impurities in the second conductivity type impurity layer, or a high concentration of the first conductivity type in the second conductivity type impurity layer It is a step of doping alternating impurities and impurities of a high concentration second conductivity type. In addition, the first conductivity type is P type, and the second conductivity type is N type.

According to another embodiment of the present invention, a method of manufacturing a trench type power MOSFET may include: forming a body of a second conductivity type by doping a second conductivity type impurity into a collector of the first conductivity type; Forming a source by doping a high concentration of impurities of a first conductivity type in the vicinity of the surface of the body, and forming a voltage dispersion layer in the source to be in contact with the first conductivity type source; Forming a trench through the dispersion layer, the source and the body to partially expose the collector, forming a gate oxide film on the trench surface, and forming a gate filling the trench And forming an insulating layer covering the gate and the voltage dispersion layer, and forming a source electrode in contact with the source.

In this case, the step of forming the voltage dispersion layer is a step of doping the second conductivity type impurities in the source at a high concentration, or a high concentration of the second conductivity type impurities and a high concentration of the first conductivity type impurities in the source. This is a step of doping alternately. The first conductivity type is N type, and the second conductivity type is P type.

In the present invention, a double junction is formed by double-diffusion of impurities having different conductivity types at high concentrations at the corners of the top of the trench to increase the thickness of the oxide film of the portion, and to take part of the voltage applied between the gate and the source in the double junction. The dielectric breakdown voltage of the transistor is increased by dispersing the voltage to be burdened by the oxide film of this part.

Hereinafter, with reference to the accompanying drawings, it will be described in more detail with respect to the trench-type power MOSFET and a method for manufacturing the same.

2 is a cross-sectional view illustrating a bus line of a trench type power MOSFET according to an exemplary embodiment of the present invention, in which reference numeral “10” denotes an N + drain, “20” denotes an N− epilayer, and “30” denotes a P− A body, "40" represents an N + high concentration impurity layer, "50" represents a P + high concentration impurity layer, "60" represents an oxide film, and "70" represents a bus line.

The bus line portion of the trench-type power MOSFET according to the present invention includes an N + drain (substrate) 10, an N− epi layer 20 formed on the N + drain, and a P formed on the N− epi layer 20. A P + high concentration impurity layer formed in the body 30, an N + high concentration impurity layer 40 formed near the surface of the P- body 30, and formed in a junction with the N + high concentration impurity layer 40; (50), a trench 84 for partially exposing the N- epi layer 20 through the P + high concentration impurity layer 50, the N + high concentration impurity layer 40, and the P- body 30; It is formed of an oxide film 60 formed on the inner wall of the trench 84 and a bus line 70 formed in a shape of filling the trench 84,

In this case, the N + high concentration impurity layer 40 is formed when the source of the power MOSFET is formed and is floating. The P + high concentration impurity layer 50 is a voltage dispersion layer and is bonded to the N + high concentration impurity layer 40.

When the P + high concentration impurity layer 50 is not formed (conventionally), the voltage applied between the bus line 70 and the N + high concentration impurity layer 40 is concentrated in the oxide film at the corner portion of the trench, whereby As a result of the insulation breakdown, as a result, the breakdown voltage of the transistor is reduced or a tunneling phenomenon occurs at this portion, thereby increasing the leakage current.

However, when the P + high concentration impurity layer 50 is formed in the N + high concentration impurity layer 40, the voltage between the bus line 70 and the N + high concentration impurity layer 40 may cause not only the oxide film at the corner portion of the trench but also the P + high concentration impurity layer. Since it is also applied to the junction between the 50 and the N + high concentration impurity layer 40, the magnitude of the voltage applied to the oxide film at the corner portion of the trench becomes small. That is, there is a voltage dispersion effect. Therefore, the field concentration in the oxide film at the trench edge portion can be weakened, so that not only the insulation breakdown voltage of the transistor can be increased but also the leakage current characteristics can be improved.

3 is a cross-sectional view illustrating a bus line of a trench type power MOSFET according to another embodiment of the present invention. In FIG. 2, the voltage dispersion layer is formed of a single P + high concentration impurity layer (50 in FIG. 2). In the N + high concentration impurity layer 40, P + high concentration impurity layer 52 and N + high concentration impurity layer 54 are alternately formed and used as the voltage dispersion layer.

In the embodiment of the present invention described above, only one junction is formed in the N + high concentration impurity layer 40 to distribute the voltage. However, in the present embodiment, two junctions (N + high concentration impurity layer 40 and P + high concentration impurity layer ( 52) and a junction between the P + highly doped impurity layer 52 and the N + heavily doped impurity layer 54) to apply a voltage that is concentrated only on the oxide film at the corner of the trench, not only to the oxide but also to the two junctions mentioned above. By doing so, it is possible to further weaken the field concentration in the oxide film at the trench edge.

In this embodiment, only two junctions are exemplified, but three, four, or more junctions may be used to further disperse the voltage applied at the trench edges.

4 is a cross-sectional view illustrating a trench type power MOSFET according to an embodiment of the present invention, in which reference numeral “10” denotes an N + drain, “20” denotes an N− epilayer, and “30” denotes a P-body (body) ), 42 is N + source, 56 is P + high impurity layer, 62 is gate oxide, 72 is gate, 80 is insulating layer, and 90 is source. Represent the electrode.

The trench-type power MOSFET according to the present invention includes an N + drain (substrate) 10, an N- epi layer 20 formed on the N + drain, and a P- body formed on the N- epi layer 20 ( 30), an N + source 42 formed near the surface of the P- body 30, a P + high concentration impurity layer 56 formed in and forming a junction with the N + source 42, and the P +. A trench 86 penetrating the high concentration impurity layer 56, the N + source 42 and the P-body 30 to partially expose the N- epi layer 20, and a gate formed in the inner wall of the trench 86 A gate 72 formed to fill the oxide film 62, the trench 84, an insulating layer 80 covering the gate 72 and the P + high concentration impurity layer 56, and the source A source electrode 90 in contact with 42 is formed.

In FIG. 2 and FIG. 3, the N + high concentration impurity layer 40 is floating. However, in the present embodiment, the N + source 42 is connected to the source electrode 90 to apply an electric voltage. At this time, the insulating layer 80 is formed on the P + high concentration impurity layer 56 used as the voltage dispersion layer to prevent the connection with the source electrode 90.

The voltage dispersion effect of the P + high concentration impurity layer 56 is as described with reference to FIG. 2.

FIG. 5 is a cross-sectional view illustrating a trench type power MOSFET according to another embodiment of the present invention. In this embodiment, the P + high concentration impurity layer 58 and the N + high concentration impurity layer 59 are alternated in the N + source 42. It is formed to use as a voltage dispersion layer.

Distributing the voltage by forming two junctions is as mentioned in FIG. 3.

6A to 6C are cross-sectional views illustrating a bus line forming method of a trench type power MOSFET according to the present invention, in accordance with a process sequence.

After the N- epitaxial layer (epitaxial layer) 20 is formed on the N + drain (substrate) 10, the P-type impurities are doped at low concentration to form the P-body 30. Thereafter, N-type impurities are doped at high concentration to selectively form N + high concentration impurity layer 40 in the vicinity of the surface of the P-body 30, and then P-type impurities are doped at high concentration to thereby form the N + high concentration impurity. P + high concentration impurity layer 50 (voltage dispersion layer) is formed in layer 40. At this time, the N + high concentration impurity layer 40 and the P + high concentration impurity layer 50 is formed to a size larger than the trench to be formed later (Fig. 6a).

After the insulating film 82 is formed on the entire surface of the resultant P + high concentration impurity layer 50, a photolithography process is performed to expose the P + high concentration impurity layer 50 in the region where the trench is to be formed. Pattern). Subsequently, the exposed substrate is etched using the insulating layer 82 as an etch mask to penetrate the P + high concentration impurity layer 50, the N + high concentration impurity layer 40, and the P-body 30 to form the N− epilayer ( A trench 84 is formed which partially exposes 20) (FIG. 6B).

Thereafter, a thermal oxidation process is performed to form an oxide film 60 on the surface of the trench 84. At this time, since the oxide film has a property of growing faster in a high impurity concentration, the growth rate on the surface of the N + high concentration impurity layer 40 and the P + high concentration impurity layer 50 is faster than that of other parts. Therefore, even if the corner portions of the trench are sharply formed, a thicker oxide film can be obtained than when the high concentration impurity layer is not formed.

Subsequently, by depositing a conductive material such as polysilicon doped with impurities, for example, a photolithography process is performed to form a bus line 70 in which the trench is buried (FIG. 6C).

According to the present invention, by forming a high concentration impurity layer (that is, an N + high concentration impurity layer 40 and a P + high concentration impurity layer 50) in the trench corner portion, the oxide film growth rate in this portion is increased to increase its thickness. . In addition, the P + high concentration impurity layer 50 is formed in the N + high concentration impurity layer 40 to concentrate the electric field concentrated in the oxide film at the corner of the trench at the junction between the N + high concentration impurity layer 40 and the P + high concentration impurity layer 50. Can be dispersed. Therefore, it is possible to prevent a problem of increasing leakage current and a decrease in dielectric breakdown voltage due to the tunneling effect.

7A to 7D are cross-sectional views illustrating a method for forming a trench type power MOSFET according to the present invention in order of process.

After the N- epitaxial layer (epitaxial layer) 20 is formed on the N + drain (substrate) 10, the P-type impurities are doped at low concentration to form the P-body 30. Thereafter, N-type impurities are doped at a high concentration to selectively form an N + source 42 in the vicinity of the surface of the P-body 30, and then P-type impurities are doped at a high concentration to thereby form the N + source 42. A P + high concentration impurity layer 56 (voltage dispersion layer) is formed within. At this time, the N + source 42 and the P + high concentration impurity layer 56 is formed to a size larger than the trench to be formed later (Fig. 7a).

After the insulating film 82 is formed on the entire surface of the resultant P + high concentration impurity layer 56, a photolithography process is performed to expose the P + high concentration impurity layer 56 in the region where the trench is to be formed. Pattern). Subsequently, the exposed substrate is etched using the insulating layer 82 as an etch mask to penetrate the P + high concentration impurity layer 56, the N + source 42, and the P-body 30 to form the N− epitaxial layer 20. A trench 86 is formed that partially exposes (FIG. 7B).

Thereafter, a thermal oxidation process is performed to form a gate oxide film 62 on the surface of the trench 86. In this case, the gate oxide film 62 may have a thicker oxide film than the case where the high concentration impurity layer is not formed for the reason described in FIG. 6C. Subsequently, for example, a gate 72 having a shape of filling the trench is formed by depositing a conductive material such as polycrystalline silicon doped with impurities and then etching it back.

Subsequently, an oxide film obtained by thinly oxidizing the polysilicon silicon, a low temperature oxide film, and films 80 such as boron-phosphorus-doped silicon are sequentially formed (FIG. 7C), followed by a photolithography process to perform the N + source 42. ), After forming a contact window 92 partially exposing the contact window 92, a metallization process is performed to form a source electrode 90 for connecting with the N + source 42 (FIG. 7D).

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by one of ordinary skill in the art within the technical idea of the present invention.

According to the trench type power MOSFET according to the present invention and a method of manufacturing the same, a double junction is formed by double-diffusion of impurities having different conductivity types at high concentrations at the corners of the trench, firstly, to increase the thickness of the oxide film of the second portion, and A portion of the voltage applied between the gate and the source is charged at the double junction to disperse the voltage to be burdened by the oxide film of this portion. Therefore, not only the leakage current generated by the tunneling phenomenon at the trench edges can be prevented, but also the dielectric breakdown voltage of the transistor can be increased.

Claims (8)

A body of the second conductivity type formed on the drain of the first conductivity type; A trench formed through the body to expose the drain; A gate oxide film formed on the trench surface; A high concentration first conductivity type source formed at an upper edge of the trench; A voltage dispersing layer formed in the first conductive source of high concentration and junctioned thereto, and floating from an external power source; A gate formed to fill the trench; An insulating layer covering the gate and the voltage dispersion layer; And A trench type power MOSFET comprising a source electrode in contact with the source. The method of claim 1, wherein the voltage dispersion layer, A trench type power MOSFET, characterized in that a high concentration of the second conductivity type impurity layer and at least one structure in which the first conductivity type impurity layer is formed inside the second conductivity type impurity layer. The method of claim 1, wherein the voltage dispersion layer, A trench type power MOSFET, characterized by a high concentration of a second conductivity type impurity layer. The method of claim 1, The first conductive type is N type, the second conductive type is a trench type power MOSFET, characterized in that the P type. Forming a body of the second conductivity type by doping the second conductivity type impurities into the drain of the first conductivity type; Forming a source by doping the impurities of the first conductivity type at a high concentration near the surface of the body of the second conductivity type; Forming a voltage dispersion layer in the source, the voltage dispersion layer being in contact with the first conductivity type source; Forming a trench through the voltage spreading layer, the source and the body to partially expose the drain; Forming a gate oxide film on the trench surface; Forming a gate shaped to fill the trench; Forming an insulating layer covering the gate and the voltage dispersion layer; And Forming a source electrode in contact with the source; and forming a trench type power MOSFET. The method of claim 5, wherein the step of forming a voltage dispersion layer, A method of manufacturing a trench type power MOSFET, characterized in that the step of doping a high concentration of impurities of the second conductivity type in the source. The method of claim 5, wherein the step of forming a voltage dispersion layer, And a step of doping alternating impurities of a high concentration of a second conductivity type and impurities of a high concentration of a first conductivity type in said source. The method of claim 5, The first conductive type is N type, the second conductive type is a trench type power MOSFET manufacturing method, characterized in that the P type.

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