KR100447175B1 - turbo decoding method and Apparatus for the same - Google Patents

Abstract

The present invention relates to a mobile communication system, and more particularly, to an efficient turbo decoding method and apparatus therefor. The turbo decoding apparatus according to the present invention includes a deinterleaver for receiving and deinterleaving a punctured bit stream, a buffer for restoring the bit stream output from the deinterleaver into a depunctured codeword and storing the decoded codeword for each address; It is configured to include a turbo decoder for performing decoding by reading the stored value of the buffer as a bit stream in the codeword unit.

Description

Turbo decoding method and apparatus for same {turbo decoding method and Apparatus for the same}

The present invention relates to a mobile communication system, and more particularly, to an efficient turbo decoding method and apparatus therefor.

In general, next generation mobile communication systems must be able to support high-speed data transmission of up to several Mpbs. Unlike voice communication, data communication requires a very low packet error probability of about 10 ^-5 to 10 ^-6 . Therefore, in high-speed data communication, the conventional convolutional coding method may encounter limitations. There is no choice but to.

However, the recent turbo widely known turbo coding method can maintain a very low packet error probability as required above even in a poor mobile communication environment. It is widely adopted as a standard.

According to the structure of the turbo decoder, the configuration of the turbo decoder is considerably simplified compared to decoding in units of codewords at one time in terms of complexity since the input codewords alternately pass through two convolutional decoders.

However, as described above, in order for the input codewords to pass through the two convolutional decoders repeatedly, the outputs of the two convolutional decoders are hard, such as "0" or "1". It must be a soft decision value corresponding to the ratio of probability "0" or "1", not decision values.

In order to obtain the soft decision value, a maximum posteriorri (MAP) decoding technique has been proposed that calculates a posteriori probability value of an information bit and decodes the information bit such that the posterior probability value is maximized. .

1 is a view showing the structure of a turbo decoder according to the prior art.

Referring to FIG. 1, two component MAP decoders 101 and 102, a turbo interleaver 103, a turbo deinterleaver 104, and a determiner 105 are used.

The configuration MAP decoder 101 primarily decodes the systematic bits, the first parity bits, and the external information bits. The external information bits are output bits of the second component MAP decoder 102.

The primary decoding bits (which become external information bits in terms of the second component MAP decoder) are interleaved by the turbo interleaver 103 and input to the second component MAP decoder 102.

The second configuration MAP decoder 102 decodes second using the first decoding bits, the second parity bits, and the tail bits.

Here, the systematic bits are information bits, and the first and second parity bits are redundancy bits respectively added by two component MAP encoders for error correction during encoding at a transmitter. In addition, the tail bits are bits that are additionally added for Trellis Termination.

In the Nth repeated decoding, the determiner 107 hardly determines the output signal of the turbo interleaver 103 and the output signal of the turbo deinterleaver 104 to extract decoding bits. .

2 is a diagram illustrating a detailed configuration for a block deinterleaving and turbo decoding process according to the prior art.

Referring to FIG. 2, a deinterleaver 201, a symbol generation block 202, a turbo decoder 203, and a controller 204 are configured.

FIG. 3 is a diagram illustrating a memory format of the deinterleaver shown in FIG. 2.

First, the received signal is deinterleaved by the deinterleaver 201 and stored in the deinterleaver memory. As shown in FIG. 3, in the above-described deinterleaver memory capable of storing five symbols at one address with one symbol of five bits, one codeword punctured may be, for example, x5 to x8 (x7 is a puncture). Processing bits) can be read across two clocks.

That is, the symbol generation block 202 generates an input symbol of the turbo decoder 203 by inputting an output symbol of the deinterleaver 201. The symbol generation block (202) is generated due to the data format of the deinterleaver memory. 202 cannot read one codeword unit from the deinterleaver memory in one clock. For reference, x is a systematic bit, y0, y1 are first and second parity bits, and xx represents a second systematic bit when the tail bit is a tail bit.

Accordingly, the turbo decoder 203 may use the systematic bits from the symbol generation block 202, the first and second parity bits, and the 0 (bits punctured at the transmitting end) for one or more clocks to perform decoding. ) Or read symbols in a codeword unit including the first and second systematic bits and the first and second parity bits (if tail bits).

One punctured codeword (x5, x6, x8) is stored in another memory address so that it cannot be read in one clock, resulting in a long decoding time.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and is to provide a turbo decoding method and apparatus for reducing the decoding time.

According to an aspect of the present invention for achieving the above object, a deinterleaver for receiving and deinterleaving a punctured bit stream, and restores the bit stream output from the deinterleaver to a depunctured codeword for each address And a turbo decoder configured to read the stored value of the buffer into a bit stream in units of codewords and perform decoding.

Preferably, when the sliding window depth which is a processing time unit of the turbo decoder is L, the buffer has a storage depth of 4 × L.

Preferably, the apparatus further includes control means for controlling the deinterleaver and the buffer such that the stored value of the buffer is provided to the turbo decoder in units of one codeword per reference clock.

According to another aspect of the present invention for achieving the above object, receiving and deinterleaving a punctured bit stream, restoring the deinterleaved output bit stream to a depunctured codeword, turbo If the sliding window depth, which is a processing time unit of decoding, is L, storing the reconstructed codeword for each address in a buffer having a storage unit of (4 × L), and the buffer; And performing the turbo decoding by reading the stored value of the codeword unit.

The method may further include outputting the stored value of the buffer in one codeword unit per reference clock.

1 is a view showing the structure of a turbo decoder according to the prior art.

2 is a diagram illustrating a detailed configuration for a block deinterleaving and turbo decoding process according to the prior art.

3 is a diagram illustrating a memory format of the deinterleaver shown in FIG. 2;

4 is a diagram showing a detailed configuration of a MAP decoder used in the present invention.

FIG. 5 is a timing diagram illustrating a sliding window technique according to a detailed configuration of the MAP decoder illustrated in FIG. 4.

6 illustrates a detailed configuration for a block deinterleaving and turbo decoding process according to the present invention.

FIG. 7 shows the data format of the turbo input buffer shown in FIG. 6; FIG.

* Description of the symbols for the main parts of the drawings *

301: Deinterleaver

302: turbo input buffer

303: symbol generation block

304: Turbo Decoder

305 controller

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a diagram illustrating a detailed configuration of a MAP decoder used in the present invention.

FIG. 5 is a timing diagram illustrating a sliding window technique according to a detailed configuration of the MAP decoder illustrated in FIG. 4.

The MAP decoder is comprised of a forward processor 106, a first reverse processor 107, a second reverse processor 108, and a dual maxima processor 109 that performs dual maxima using these 106, 107, and 108 outputs. . Operation of each processor according to the above configuration will be described in more detail below with reference to a timing diagram in FIG. 5.

In FIG. 5, the x-axis represents the passage of time, and shows which symbols the processors 106, 107, and 108 process as the passage of time. The number of symbols in forward processor 106 increases and the number of symbols in reverse processor 107, 108 decreases. In addition, the reverse processors 107 and 108 indicate that they are 'learning' in the dashed period. The arrow of the curve shows the correlation between the forward recursion value and the reverse recursion value required for bit determination of the MAP decoder.

That is, the processing time of the forward processor 106 is a time for calculating a forward recursive state metric, and the processing times of the first and second reverse processors 107 and 108 are respectively a first reverse recursive state metric and a second reverse recursion. Time to calculate the status metric. The first and second reverse recursion values are calculated by 2L, and only the last L portion is alternately input to the dual Maxima processor 109.

While one reverse processor 107 is "learning" using two reverse processors, the other reverse processor 108 calculates backward recursion values necessary for bit determination of the MAP decoder.

That is, when one MAP decoding is started, the first reverse processor 107 performs a "learning" process from 2L to (1L + 1). The second reverse processor 108 is stationary during this learning process. Where L represents the sliding window length, that is, the processing unit time of each processor included in the turbo decoder.

Thereafter, the first reverse processor 107 calculates backward recursion values of 1L to 1, and the dual maxima processor 109 uses 1L to 1 by using forward recursion values of 1 to 1L that are already calculated and stored. The dual maxima is executed to generate and output external information, which is a soft decision value. During the external information bit determination time, the second reverse processor 108 performs " learning " using symbols from 3L to (2L + 1).

In the next section, the second reverse processor 108 calculates backward recursion values from 2L to 1L, and the dual maxima processor 109 executes dual maxima from 2L to (1L + 1) to obtain external information that is a soft decision value. Create and print During the generation time of this external information bit, the first reverse processor performs " learning " using symbols from 4L to 3L.

The external information output, which is the output of the dual maxima processor 108, has the same index as the first and second reverse recursion values, is generated in L units, and is generated in the reverse order of the information bits in each L unit.

In addition, the three forward and backward recursion values receive symbols required for the recursion value from the block interleaver, and in order to calculate one step (3L length) of the recursion value, all symbols forming the codeword of the corresponding decoder are required. .

For example, if the code rate is 1/4 at the transmitter, three symbols are punctured and concatenated from the first encoder and the second encoder to generate four codewords, and the tail bits. In the case of, four symbols are alternately output from the first encoder and the second encoder to generate a new codeword. Therefore, at the receiving end, the recursive value of each of the forward processor 106 and the first and second reverse processors 107 and 108 can perform one step (3L length) calculation by inputting a codeword composed of up to four symbols. .

6 is a diagram illustrating a detailed configuration for a block deinterleaving and turbo decoding process according to the present invention.

FIG. 7 is a diagram illustrating a data format of a turbo input buffer shown in FIG. 6.

Referring to FIG. 6, a deinterleaver 301, a turbo input buffer 302, a symbol generation block 303, a turbo decoder 304, and a controller 305 are configured.

First, the received signal is deinterleaved by the deinterleaver 301 and stored in a deinterleaver memory (not shown). As shown in FIG. 3, the deinterleaver memory has a data format capable of storing four symbols at one address.

To shorten the decoding time of turbo decoding, the turbo input buffer 302 reads punctured symbols from the deinterleaver memory from one codeword at the transmitting end, and punctures the puncturing bits with zero, Store the codeword in memory at one address. The turbo input buffer 302 has a maximum code rate of 1/4 in the case of the CDMA 2000 system, and thus stores four symbols at one address, and the storage unit has 4L, which is four times the sliding window size L.

The controller 305 controls the deinterleaver 301 and the turbo input buffer 302 to output one codeword per one reference clock for codewords stored at one address.

As shown in FIG. 5, the MAP decoder needs 3L turbo codewords consecutively during the processing unit time L period of each processor. Therefore, the turbo input buffer 302 must store L turbo codewords from the deinterleaver memory in advance for calculation of the next L section with a storage unit of 3L. That is, the turbo input buffer 302 must have a storage depth of (3L + L).

For example, in FIG. 5, a forward recursion value is obtained for a period between (L + 1) and 2L between processing times (L + 1) to 2L, and the first reverse recursion value is L to 1 and the second reverse recursion value is obtained. Since is obtained in the section of 3L-(2L + 1), the turbo codeword of this section is required. A total of 1 to 3 L of consecutive 3L turbo codewords are required. The turbo codewords of (3L + 1) to 4L must be read in advance from the deinterleaver memory and stored for the next section of operation. In the next (2L + 1) to 3L interval, the forward recursion value is obtained, and the second reverse recursion value is respectively (2L + 1) to L, 4L to (3L + 1), and 2L to (L + 1). Turbo codeword of is required. Since turbo codewords of 1 to L are not required in this section, the turbo codewords required for the next section (4L + 1 to 5L) in this area of the turbo input buffer are read in advance from the memory and stored.

As such, with every L interval execution, the turbo input buffer must have a storage depth of 4L to store a total of 4L turbo codewords.

FIG. 7 illustrates a symbol format stored in a turbo input buffer when the code rate is 1/4 and the symbol puncturing pattern is '1101-1101-1010'.

Three (8 symbols) data are sequentially read from the deinterleaver memory having the data format as shown in FIG. 3, and the third write operation is performed in the format as shown in FIG. In this way, the MAP decoder can read and decode the turbo codewords required for each recursion at every clock, and perform a soft decision by performing dual maxima at every three clocks (the time when the turbo codewords are read in total of three recursions). You can create an external output that is a value. That is, the processing time 1 of FIG. 3 may consist of three clocks.

At the first decoding time, 2L turbo codewords are stored in the turbo input buffer from the deinterleaver, and decoding is then performed.

As described above, the present invention generates a turbo codeword, which is the input signal of the MAP decoder, every clock using a turbo input buffer having four times the storage unit (4L) of the learning period in the turbo decoder. The required turbo codeword can be generated for three clocks to generate external output information per three clocks to shorten the turbo decoding time.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

Claims (5)

A deinterleaver for receiving and deinterleaving a punctured bit stream; A buffer for restoring the bit stream output from the deinterleaver into a depunctured codeword and storing the bit stream for each address; And a turbo decoder configured to read the stored value of the buffer into a bit stream in codeword units and perform decoding. The turbo decoding of claim 1, wherein the buffer has a storage depth of (4 × L) when a sliding window depth, which is a processing time unit of the turbo decoder, is L. 4. Device. 2. The turbo according to claim 1, further comprising control means for controlling the deinterleaver and the buffer such that the stored value of the buffer is provided to the turbo decoder in units of one codeword per reference clock. Decoding device. Receiving and deinterleaving a punctured bit stream; Restoring the deinterleaved output bit stream to a depunctured codeword; If the sliding window depth, which is a processing time unit of turbo decoding, is L, storing the reconstructed codeword by address in a buffer having a storage unit of (4 × L); And performing the turbo decoding by reading the stored value of the buffer in codeword units. The turbo decoding method of claim 4, further comprising outputting the stored value of the buffer in one codeword unit per reference clock.