KR100317377B1 - Encoding and decoding apparatus for modulation and demodulation system - Google Patents

Abstract

The present invention relates to a technique for matching the difference in the number of tail bits by using extra reserved bits in a wired / wireless communication system using two or more different convolutional codes at the same time and at the same time improving coding performance.

The object of the present invention includes a tail bit inserting unit 12 for inserting (K-1) tail bits into a data block when one data block composed of L bits is inputted; An encoder (13) comprising one convolutional encoder or a parallel or serial convolutional convolutional encoder for performing convolutional coding on the output signal of the tail bit inserter (12); A hold bit inserter (14) for inserting (K1-K2) reserved bits into the data block when the data block is input; A tail bit inserting unit (15) for inserting (K2-1) tail bits to the output signal of the hold bit inserting unit (14); One of using (K1-K2) reserved bits to match the number of output bits when the relation of tail bits is K1> K2 in performing convolutional coding on the output signal of the tail bit inserter 15 Is achieved by an encoder 16 consisting of a convolutional encoder or a parallel or serial convolutional encoder.

Description

ENCODED AND DECODING APPARATUS FOR MODULATION AND DEMODULATION SYSTEM}

The present invention relates to a technique for matching tail bits in a wired or wireless communication system using two or more different types of convolutional codes at the same time. Particularly, the number of tail bits is used by using an extra reserved bit. The present invention relates to an encoding and decoding apparatus of a modulation / demodulation system, which is adapted to match and at the same time improve coding performance.

In the next generation mobile communication systems, one or more error correction codes are used to satisfy various transmission speeds and quality of service. In particular, next-generation mobile communication systems (eg, IMT-2000) have two convolutional codes, namely, conventional convolutional code, parallel concatenated convolutional code (aka Turbo code) or serial concatenation ( Serially concatenated convolution codes are used.

In this case, in order to end the trellis of the used convolutional code in a contracted state in one data block, it is common to use tail bits at an end portion of one data block. 1) tail bits are required. However, considering the performance and complexity of the system, the number of tail bits needed to terminate the trellis of the other convolutional codes selected is generally different.

However, in the conventional coding technique, random data is used for the extra reserved bits in order to match the number of tail bits which are different from each other, so an efficient use of the extra reserved bits cannot be expected. There is a defect that does not contribute to the improvement of the encoding.

Accordingly, an object of the present invention is to encode a modulation and demodulation system that efficiently processes extra reserved bits without additional hardware in a wired or wireless communication system using two or more different convolutional codes at the same time, thereby improving the code / decoding performance. And a decoding apparatus.

1 is a block diagram of an embodiment of an encoding apparatus of a modulation and demodulation system according to the present invention;

2 (a)-(d) are data format diagrams showing an example of inserting a retention bit between a data block and tail bits when K1> K2.

3 (a)-(d) are data format diagrams illustrating an example in which a reserved bit is inserted at an optimized position between data blocks when K1> K2.

4 is a block diagram of a parallel concatenated encoder with N systematic convolutional coding functions.

5 is a block diagram of a serial concatenation encoder with two convolutional encoders.

6 is a block diagram of a parallel convolutional convolutional encoder requiring six tail bits.

7 is a block diagram of a parallel concatenated encoder with two convolutional coding functions.

8 is an exemplary block diagram of an apparatus for decoding a demodulation system according to the present invention.

9 is a signal flowchart of a decoding process of FIG. 8;

10A-10F are tables showing simulation results by inserting reserved bits between data blocks and tail bits.

11A-11F are tables showing simulation results by inserting a reserved bit at an intermediate position of a data block.

12 is a block diagram of an encoder with constraint 4 used for the simulations of FIGS. 10 and 11.

*** Description of the symbols for the main parts of the drawings ***

11: Data block output section 12,15: Tail bit insertion section

13,16: encoder 14: hold bit insertion unit

81: deinterleaver 82,84: interleaver

83,85 Decoder 86,88 RAM

87,89: Rom

According to a first aspect of the present invention, as a scheme for utilizing extra reserved bits, an encoder uses reserved bits rather than random data for extra reserved bits.

According to a second aspect of the present invention, the use position of extra reserved bits in the encoder as a method of utilizing the reserved bits according to the first characteristic is between the data block and the tail bits.

According to a third aspect of the present invention, as a method of utilizing reserved bits according to the first aspect, a position where an extra reserved bits are used in an encoder is a bit error rate (BER) or a frame error rate (FER). : It is between arbitrary data blocks that optimize performance in terms of Frame Error Rate.

According to a fourth aspect of the present invention, there is provided a method of utilizing reserved bits according to the first aspect, wherein information that the decoder knows in advance about extra reserved bits by using a previously known bit (committed bit) in the encoder. Is used in the decoding process.

According to a fifth aspect of the present invention, when applied to a system in which a parallel or serial convolutional coder using an interleaver is used as a method of utilizing reserved bits according to the features 1-4, the decoder is previously decoded. The learned information is used more efficiently through an iterative decoding process.

According to a sixth aspect of the present invention, when applied to a system in which a parallel or serial convolutional convolutional coder using an interleaver is used as a method of utilizing reserved bits according to the fifth aspect, the decoder performs iterative decoding. ) Is to reflect the information on the reserved bits reserved in advance based on the probability of occurrence of the reserved bits.

EMBODIMENT OF THE INVENTION Hereinafter, the structure and operation | movement of the code | symbol and decoding apparatus by this invention are demonstrated with reference to attached drawing.

1 is an exemplary block diagram of an encoding apparatus of a modulation / demodulation system for achieving an object of the present invention. As shown therein, a data block output unit 11 continuously outputs one data block composed of L bits; A switch SW1 for switching an output path of a data block output from the data block output unit 11; A tail bit inserting unit (12) for inserting (K-1) tail bits into the data block when the data block is input through the switch (SW1); An encoder (13) formed of one convolutional encoder or a parallel or serial convolutional convolutional encoder for performing convolutional coding on the output signal of the tail bit inserter (12); A hold bit inserter (14) for inserting (K1-K2) reserved bits into the data block when the data block is input through the switch (SW1); A tail bit inserting unit (15) for inserting (K2-1) tail bits to the output signal of the hold bit inserting unit (14); One of using (K1-K2) reserved bits to match the number of output bits when the relation of tail bits is K1> K2 in performing convolutional coding on the output signal of the tail bit inserter 15 It is composed of an encoder 16 consisting of a convolutional encoder or a parallel or serial convolutional coder, which will be described in detail with reference to FIGS. 2 to 12 attached to the operation of the present invention.

For example, if the encoder 13 needs (K1-1) tail bits and the encoder 16 needs (K2-1) tail bits and the relationship of the tail bits is K1> K2, the two encoders In order to match the number of output bits of (13) and (16), (K1-K2) reserved bits are used in the encoder 16.

The encoder 13 may be implemented by one convolutional encoder, or may be implemented by a parallel or serial convolutional convolutional encoder. Similarly, another encoder 16 may be implemented with one convolutional encoder, or may be implemented with a parallel or serial convolutional convolutional encoder.

When the parallel convolutional coder is used in the modulation / demodulation system as described above, at least two systemic coders 42A to 42N are provided as shown in FIG. 4. In addition, when the serial convolutional encoder is used in the modulation and demodulation system, two convolutional encoders 51 and 54 are provided as shown in FIG. 5.

The data block output unit 11 outputs a data block in units of L bits, in which L = 376, the encoder 13 is a convolutional encoder requiring 8 tail bits, and the encoder 16 has 6 tail bits. Assume that we have a parallel convolutional convolutional encoder that requires. 6 is a block diagram illustrating an embodiment of a convolutional convolutional encoder requiring six tail bits. In this case, the encoder 16 needs two reserved bits.

The position at which the reserved bits are inserted will be described with reference to FIG. 2 as shown in FIG. 2A and FIG. 2A output from the data block output unit 11 when the switch SW1 is shorted to the fixed terminal a. The same L bits of data are supplied to the tail bit inserting unit 12 through the switch SW1, and (K-1) tail bits are added to the encoder 13 as shown in FIG. And encoding processing.

In addition, when the switch SW1 is short-circuited to the fixed terminal b, L-bit data such as (a) of FIG. 2 output from the data block output unit 11 is tail bit through the switch SW1. (K1-K2) reserved bits are added to the insertion section 14, as shown in (c) of FIG. 2, and then the tail bit insertion section 15 of the next stage is supplied to (d) of FIG. Similarly, (K2-1) tail bits are added and then supplied to the encoder 16 for encoding.

7 illustrates a process of inserting reserved bits in relation to the encoder 16. That is, in FIG. 1, when the switch SW1 is shorted to the fixed terminal b, the data block sequentially output from the data block output unit 11 is added through the fixed terminal b of the switch SW1. After the two bits supplied and withheld to 71 are added, on the one hand, it is supplied to the adder 72, three tail bits are added, and then encoded through the system encoder 73, and on the other hand, the interleaver ( 74 is supplied to the adder 75, and three tail bits are added, and then encoded by the system encoder 76. Each of the encoded data is punctured through two levels of puncturing patterns 77 and 78. The first puncturing pattern 77 does not include tail bits, and the second puncturing pattern ( 78) is a puncturing pattern for tail bits.

3 illustrates another embodiment of the present invention, which inserts reserved bits into an optimized position between data in a data block unlike FIG. Here, the 'optimized position' refers to a position in which bit errors or frame errors are reduced on average, and these positions are based on simulation results.

Codes generated through the above process are modulated and then transmitted to a receiver through a predetermined communication channel and decoded by a decoder.

In the decoding process, the maximum probability decoding algorithm of the 'Viterbi algorithm' type is used, and when the iterative decoding algorithm using the soft decision output value is used, the efficiency can be further improved.

Examples of iterative decoding algorithms that use soft decision outputs in the form of a 'Viterbi algorithm' can be used: Maximum a Posteriori (MAP) algorithm, Soft-Output Viterbialgorithm (SOVA), Max-Log-MAP algorithm.

The iterative decoding algorithm using the soft decision output value of the Viterbi algorithm type is a signal before the data block is encoded in the decoding process. The probability of occurrence of is used. For example, the signal of the data block P1 output from the data block output unit 11 of FIG. 1. If is a binary signal of '1' or '-1', the logarithm of the probability ratio of Equation 1 or Equation 2 is used in the iterative decoding algorithm.

--------------- (Equation 1)

--------------_-- (Equation 2)

When an iterative decoding algorithm using the soft decision output value is used, an iterative decoding process is performed by reflecting a known fact about reserved bits to a value defined by Equation (1) or (2). .

That is, the values of the expressions (1) and (2) are determined as shown in the following expressions (3) and (4) to reflect the facts previously known to the decoder for the reserved bits.

------------ (Equation 3)

------------ (Equation 4)

In formula (3), (formula 4) Is two reserved bits for encoder 16. Further, in the formulas (3) and (4),? It is a positive value set to a value large enough so that an error does not occur due to the influence of other data when decoding the corresponding transmission data. For reference, the demodulation system shows the most ideal performance when using the maximum positive value allowed to perform the decoding algorithm.

FIG. 8 illustrates an embodiment of a decoder using an iterative decoding algorithm utilizing information known to the reserved bits by Equation (3) or (4). Here, the two decoders 83 and 85 repeatedly perform the decoding algorithm for a predetermined number of times and are updated each time. Wow (or and ) Using RAMs 86 and 88 that store values.

At this time, (or ) Values are updated with values calculated by the decoding algorithm performed repeatedly. and (or and ) Are repeatedly recorded at predetermined positions on the RAMs 86 and 88 with the values defined by Equation 3 or 4 above.

From above and (or and Repeated recording of the values) will be described with reference to FIG.

For example, when the encoder 16 of FIG. 1 is implemented with a parallel convolutional convolutional encoder requiring six tail bits as shown in FIG. 6, a vector encoded from the encoder 16 through a predetermined transport channel signal In this case, all values of the RAM 86 are initialized to σ, and the value selected in the ROM 87 is written to the corresponding address of the reserved bit among the addresses of the RAM 86. (S1-S3)

In this case, the decoder 83 uses the value written to the RAM 86 to input the input vector signal. Decode and output the signal from Is written to another RAM 88 after being interleaved by the interleaver 84, and at this time, the value selected in the ROM 89 is written to the corresponding address of the reserved bits in the address of the RAM 88. (S4 -S7)

The decoder 85 decodes an input signal using the value written to the RAM 88. The input signal is the vector signal. Is interleaved by the interleaver 82, the output signal of the interleaver 84, and the vector signal. (S8)

The decoding process is repeatedly performed a predetermined number of times. If the predetermined number of times has not yet been reached, the output signal of the decoder 85 is deinterleaved through the deinterleaver 81 and then the RAM 86 is executed. The process returns to the third step S3 and repeats the above process (S9-S11).

However, when the above decoding process is repeatedly performed a predetermined number of times (the number of decryptions performed = K), a decision variable value is calculated, and a variable value (for example, based on the calculated result) is calculated. +1 or -1) (S12, S13).

Meanwhile, FIGS. 10A to 10F illustrate simulation results by inserting a reserved bit through the above process between the data block and the tail bit as shown in FIG. 2. When it is set to '00', '01', '10', and '11', it can be seen that the number of frame errors and the number of bit errors is smaller than that of using random bits.

11A and 11F illustrate simulation results by inserting a reserved bit in an intermediate position of the data block as shown in FIG. 3. At this time, the insertion position of the reserved bits is selected as an optimized place to properly improve the BER and FER based on the simulation results.

FIG. 12 illustrates an encoder having a constraint field 4 used for the simulation of FIGS. 10 and 11.

The same applies to the use of a serial concatenation encoder instead of the parallel convolutional encoder of the encoder 16 used in the first embodiment.

Instead of the iterative decoding algorithm used in the first and second embodiments, a Viterbi algorithm having a hard decision output value may be used. In such a case and (or and Recording of the values is performed only once before starting decoding.

As described in detail above, the present invention relates to a data block and tail bits when inserting reserved bits to match the number of tail bits that are different in wired and wireless communication systems using two or more different convolutional codes simultaneously. By inserting in the interpolation, or between data blocks that optimize performance in terms of bit error rate or frame error rate, encoding performance can be improved together. In addition, in the decoding process, the decoding efficiency may be improved by utilizing the reserved bits. In addition, when applied to a system using a parallel or serial convolutional encoder using the interleaver, the decoding performance is further improved by using information previously known in decoding in an iterative decoding process.

Claims (5)

An encoding apparatus in which different types of convolutional encoders are used simultaneously, wherein a convolutional encoding is performed on a first tail bit inserter for inserting tail bits into a data block of a predetermined bit and an output signal of the first tail bit inserter. First encoding means comprising a first encoder; A retention bit inserter for inserting a reserved bit previously reserved for matching the number of output bits with said first encoding means with respect to the data block of the predetermined bit, and a tail bit for the output signal of the reserved bit inserter; And a second encoding means including a second tail bit inserting unit and a second encoder for performing convolutional encoding on the output signal of the second tail bit inserting unit. The apparatus of claim 1, wherein the reserved bit inserter inserts the reserved bit between the data in the data block and inserts the reserved bit at an optimized position that reduces bit error or frame error on average. . The apparatus of claim 2, wherein the optimized position is determined by simulation. 2. The apparatus of claim 1, wherein the second encoding means comprises: an adder (71) for inserting a predetermined number of bits reserved for sequentially input data blocks; An adder 72 for inserting a predetermined number of tail bits to the output signal of the adder 71; A system encoder (73) for encoding the output signal of the adder (72); An interleaver (74) for interleaving the sequentially input data blocks; An adder (75) for inserting a predetermined number of tail bits to the output signal of the interleaver (74); A system encoder (76) for encoding the output signal of the adder (75); And a series of parallel convolutional convolutional encoders consisting of two levels of puncturing patterns (77) and (78) puncturing the output signals of the two systemic encoders (73) and (75). In implementing a decoder corresponding to a parallel convolutional convolutional encoder requiring a predetermined number of tail bits, a vector signal encoded from the encoder through a transmission channel RAM 86 initializes all stored values when is inputted and writes the selected value in the ROM 87 to the corresponding address of the reserved bit; The input vector signal by using the value written to the RAM 86 A decoder (83) for decoding the; An interleaver (84) for interleaving an output signal of the decoder (83); A RAM 88 in which the value selected in the ROM 89 is written to the corresponding address of the reserved bit after the interleaved signal is written; The interleaved vector signal using the value written to the RAM 88 And an output signal and a vector signal of the interleaver 84 A decoder 85 for encoding the data; Decoding the demodulation system by deinterleaving the output signal of the decoder 85 and then performing the encoding process a predetermined number of times through the deinterleaver 81 which writes to the RAM 86 and then calculates the decision variable value. Device.