KR19990013245A - Adaptive channel coding method and apparatus - Google Patents

Abstract

A coding apparatus of a communication system using a channel encoder in which convolutional codes are connected in a parallel or serial structure, the encoding apparatus comprising: a first encoder for encoding input information bits and an input information bit according to a set rule to change the order of the information bits; An interleaver composed of a memory and an index generator, a second encoder for encoding the output of the interleaver, a first terminator and a second terminator for terminating frames of input and output information bits of the first encoder and the second encoder; And a tail bit storage device for storing and outputting tail bits used at the end of the frame, and a controller and a switch for controlling this process.

Description

Adaptive channel coding method and apparatus

The present invention relates to a channel encoding method and apparatus for a communication system, and more particularly, to an adaptive channel encoding method and apparatus for voice and data transmission.

A turbo encoder is a system that creates a parity symbol using two simple constituent encoders, which is composed of a frame of N information bits, and can be configured in parallel and serial structures. have. The constituent code of the turbo encoder uses a recursive systematic convolutional code.

1 is a diagram showing a configuration of a turbo encoder having a conventional parallel structure, which is disclosed in US Pat. No. 5,446,747, which was invented by Berrou. The turbo encoder having the configuration as shown in FIG. 1 is connected to the interleaver 12 between the first component encoder 11 and the second component encoder 13. The interleaver 12 has the same size as the frame length N of the input information bits and reduces the correlation between the information bits by changing the order of the information bits input to the second component encoder 13. 2 is a diagram illustrating a structure of a turbo encoder in a conventional serial structure, in which an interleaver 12 is connected between a first component encoder 11 and a second component encoder 13.

The turbo coder having the above structure is used for the turbo code that has been used in space-space communication, and the constituent encoders 11 and 13 have a smaller length than the conventional convolutional code having a K length of K = 9. For example, the memory used for interleaver 12 is very large. Therefore, the time delay during decoding is also very large.

A turbo decoder which decodes an output to a turbo encoder having a parallel structure as shown in FIG. 1 has the configuration as shown in FIG. 3 and is disclosed in US Pat. No. 5,446,747 invented by Berrou. The turbo decoder which decodes the output of the turbo encoder of the serial structure as shown in FIG. 2 has the configuration as shown in FIG. 4 and is published in a paper published by Benedetto. (IEEE Electronics Letters, June 1996, Vol. 13)

Referring to the operation of the turbo decoder of the parallel structure of FIG. 3, as shown in FIG. 3, by repeating the decoding using the iterative decoding algorithm on a frame-by-frame basis, an error rate is increased according to an increase in the number of repeated decoding. Rate (BER) performance has the advantage of gradually improving. The interleaver 323 distributes an uncorrected error pattern that is not corrected in the first decoder 319 and then corrects the error in the second decoder 327 to improve the error correction capability.

The iterative decoding is decoding again by using the decoded symbols. When the iterative decoding is performed by using the decoded symbols and additional information derived with a specific rule, excellent performance can be obtained. Algorithms for iterative decoding include SOVA (Soft-Output Viterbi Algorithm) and MAP (Maximum A Posteriori Probability) algorithms, in which the decoded value has a soft-determined value. (SOVA: Proceedings of IEEE Vehnicular Technology Conference, pp 941-944. May 1993, MAP: IEEE Transactions on Information Theory, pp 429-445, Vol. 42 No. 2 March 1996) The SOVA algorithm is a Viterbi algorithm. Modified to output soft decision value in, it can minimize error of codeword. On the other hand, the MAP algorithm is an algorithm capable of minimizing symbol error, thereby obtaining a lower symbol error probability than the SOVA algorithm.

In FIG. 3, when the received parity symbol y _k is a value encoded by the first component encoder 11 of the parallel turbo encoder of FIG. 1, y _1k = y _k , y _2k = 0, and y _k is FIG. 1. When the value is encoded by the second constituent encoder 13 of the parallel structure turbo encoder, y _1k = 0, y _2k = y _k . Z _{k + 1} is a soft decision value using an iterative decoding algorithm and is used as an input for the next iterative decoding. In the final decoding step, the hard decision value of z _{k + 1} becomes the final desired d ^ _k . The performance of the turbo code is determined according to the size of the interleaver, the structure of the interleaver and the number of iterative decoding.

As shown in FIG. 1, an interleaver 12 is provided inside the turbo encoder. The interleaver 12 performs encoding and decoding on a frame-by-frame basis when encoding and decoding a turbo code. Therefore, as shown in FIG. 3, the frame size of the memory required for the first iteration decoder 319 and the second iterative decoder 327 is proportional to the product of the number of states of the component codes 11 and 13. Since the turbo code generally uses a very large frame, it is very difficult to apply to the transmission of voice and data. Increasing the number of states of the constituent codes of the turbo encoder to reduce the size of the interleaver reduces the memory size required for the interleaver, but increases the complexity of the first and second decoders of FIG. 3.

When a concatenation error occurs in the decoder having the structure as shown in FIG. 3, the output of the first iteration decoder 319 has a correlation, and in the decoding process of the next step, the second iterative decoder 327 which is the second decoder is Correlated inputs prevent correct decoding. Therefore, there is an error in the entire block, which cannot be corrected in the next iterative decoding process. Therefore, in the code for performing the iterative decoding, the interleaver and the deinterleaver (12 in FIG. 1, 12 in FIG. 2, 323 in FIG. 3, 331 in FIG. 3, and 3 in FIG. 335, 12 of FIG. 4, and 13 of FIG. 4 are essential.

Therefore, the turbo code shows very good performance by using a random interleaver that makes the correlation very small. However, if the size of the frame is not large, even if the random interleaver is used, it is difficult to separate the error so that the collection error is irrelevant, and the lookup table necessary for the random interleaver is needed. Therefore, in the case of voice transmission or data transmission with low transmission rate, a frame size and a structured interleaver that can minimize time delay while having a small number of configuration codes should be used. Therefore, the above-mentioned voice and data transmission is very difficult with the constrained length and interleaver of the component code used in the conventional turbo code. However, efforts to implement an encoder and a decoder of a communication system have been increasing by using the advantages of the turbo code.

In order to implement a turbo encoder that has similar or superior performance to that of the convolutional code used in the conventional communication system and has no high complexity, an interleaver having a high performance while minimizing time delay and having a small number of configuration codes should be used. do. In general, the larger the size of the interleaver 12 of FIG. 1 or 12 of FIG. 2, the better the performance. However, there is a limit in increasing the frame size in the turbo code. In such a case, it is advantageous to use an interleaver that makes the turbo code the minimum Hamming distance of the turbo code in terms of block code. In the case of small frames, this problem can be solved by using a structural interleaver.

Accordingly, an object of the present invention is to provide a turbo encoding method and apparatus capable of encoding voice and low data rate in a communication system.

Another object of the present invention is to provide a parallel or serial turbo encoding method and apparatus using a diagonal interleaver capable of interleaving regardless of the size of a data frame input in a communication system.

Another object of the present invention is to provide a parallel encoding method or an apparatus for turbo encoding using a cyclic interleaver capable of interleaving regardless of the size of an input data frame.

It is still another object of the present invention to provide a method and apparatus for transmitting a parity bit generated by tail bits and tail bits to a channel in an apparatus for encoding a voice and data signal using a turbo code.

It is still another object of the present invention to provide a method and apparatus for adjusting a data rate by puncturing data and parity information in an apparatus for encoding a voice and a data signal with a turbo code.

In order to achieve the above object, an encoding apparatus of a communication system according to an embodiment of the present invention includes at least two component encoders for encoding input bits and matrix information corresponding to a frame size of the input information. And diagonally interleaving the input information according to the matrix information of the frame and connecting the input information to at least one input terminal of the encoder.

In addition, the encoder of the communication system according to an embodiment of the present invention for achieving the above object comprises at least two encoders for encoding the information bits input, hop variable information corresponding to the size of the input data and the hop And a cyclic interleaver which cyclically interleaves the input information according to a variable and then connects to the input terminal of at least one constituent encoder of the encoders.

In addition, at least two component encoders for encoding the information bits inputted by the encoding apparatus of the communication system according to an embodiment of the present invention for achieving the above object, and after interleaving the input information of at least one of the encoders An interleaver connected to an output terminal, and tail bit generators connected to the input / output terminals of the component encoders and switched at the end of frame data to generate tail bits for terminating the component encoders and input the tail bits generators to the corresponding component encoders, respectively. do.

In addition, according to an embodiment of the present invention for achieving the above object, an encoding apparatus of a communication system having a decoder using an iterative decoding algorithm interleaves input information and at least two component encoders for encoding input information bits. And an interleaver connected to an output terminal of at least one of the encoders, and a puncturer for puncturing the input information to adjust transmission rates of the input information and the parity symbol.

In addition, a turbo encoding apparatus according to an embodiment of the present invention for achieving the above object; A first constituent encoder for encoding input information bits; An interleaver for interleaving the information bits according to a set rule to change the order of the information bits; A perforator capable of varying the transmission rate of the turbo encoder output; A second constituent encoder for encoding an output of the interleaver, a first switch, a second switch, and a tail bit generator connected to input terminals of the first constituent encoder and the second constituent encoder; A tail bit storage device and a third switch for transmitting tail bits of the tail bit generator to a transmission channel; A first tail bit generator for generating a tail bit for terminating the first component encoder and inputting the tail bit to the first component encoder; A second tail bit generator for generating a tail bit for terminating the first component encoder and inputting the tail bit to the second component encoder; A memory device for storing data input to the interleaver and deinterleaver, a memory device for storing interleaved and deinterleaved data, and a controller for controlling the process. Characterized in that consisting of.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the configuration of a conventional parallel chain circular structural encoder

Fig. 2 is a diagram showing the configuration of a conventional serial chain cyclic structural coder.

3 is a diagram showing the configuration of a conventional parallel chain cyclic structural decoder.

4 is a diagram showing the configuration of a conventional serial chain cyclic structural decoder.

5 is a diagram showing a chain circular structural encoder according to the first embodiment of the present invention.

6 is a diagram showing a chain circular structural encoder according to a second embodiment of the present invention.

7 illustrates the structure of a diagonal interleaver in a turbo encoder according to a first embodiment of the present invention.

8 is a flowchart illustrating a first diagonal interleaving operation process according to an embodiment of the present invention in the structure of a diagonal interleaver having the configuration as shown in FIG.

7 illustrates the structure of a cyclic interleaver in a turbo encoder according to a second embodiment of the present invention.

10 is a flowchart illustrating a first cyclic interleaving operation procedure according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG.

11 is a flowchart illustrating a second cyclic interleaving operation process according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG.

12 is a diagram showing characteristics of a turbo encoder using a random interleaving method and a block interleaving method and a turbo encoder using a cyclic interleaving method according to a second embodiment of the present invention.

13 is a diagram illustrating a configuration for explaining tail bit generation and puncturing operations in a turbo encoder according to an embodiment of the present invention.

In the embodiment of the present invention, a configuration of a turbo encoder having a parallel chain circulation structure will be described as an example for convenience of description. 5 and 6 are diagrams illustrating a configuration of a turbo encoder according to an embodiment of the present invention. It is assumed that the first encoders 412 and 414 use a component encoder, and the encoders 412 and 414 are shown in FIGS. Parity symbol Y _k is generated by encoding the received information bit d _k as in the configuration coder of 2. In addition, the diagonal interleaver 432 and the circular shifting interleaver 434 are interleavers according to the first and second embodiments of the present invention. It will be called.

5 and 6, the information bit d _k is input to the first component encoder 410 and simultaneously to the interleaver 430 so that the order of the information bits is changed and input to the second component encoder 420. When the interleaver 430 performs optimal interleaving, the interleaver 430 uses an interleaver whose maximum Hamming distance of the sequence X _k and Y _k is output after the input information bit d _k is encoded. In addition, the frame size of data input to the channel encoder is not constant due to the addition of CRC bits and other control bits as well as pure data. If forcibly fixing the size of the input data frame, dummy bits should be added as much as the interleaver size. Since the dummy bits have nothing to do with improving the performance of the system, fewer are better. Therefore, the interleaver 430 should have good performance and operate well regardless of the parameter change related to the input data frame size.

FIG. 7 shows the configuration of the diagonal interleaver 432 and the cyclic interleaver 434 shown in FIGS. 5 and 6. The diagonal interleaver 432 and the cyclic interleaver 434 analyze the corresponding frame size when an information bit having a variable sized frame is input and perform an interleaver operation by receiving interleaver-related parameters from the system controller according to the frame size analysis result. Done. In the embodiment of the present invention, the diagonal interleaver 432 and the cyclic interleaver 434 will be described as an example of implementing one interleaver. However, when the interleaving method is selected from the diagonal interleaving or the cyclic interleaving method in the turbo encoder, it may be configured as one. Here, the diagonal interleaver 432 and the cyclic interleaver 434 will be referred to as interleaver 430.

Referring to FIG. 7, the register 511 receives and stores a frame size signal and an interleaver type signal output from a system controller (not shown). The diagonal interleaving table 513 is a table for storing values M and N of rows and columns which may have optimal diagonal interleaving characteristics according to the frame size of the information bit when performing the diagonal interleaving function. That is, when diagonally interleaving information bits received with a variable frame size, M and N having an optimal diagonal interleaving effect are experimentally measured and stored in the diagonal interleaving table 513. The diagonal interleaving table 513 outputs M and N values corresponding to the frame size signal output from the register 511. The diagonal interleaving controller 517 inputs M and N values output from the diagonal interleaving table 513 and then generates a read address for interleaving and outputting information bits in a set diagonal interleaving scheme. The cyclic interleaving table 515 is a table for storing hop variable and step variable values p and STEPs which may have optimal cyclic interleaving characteristics according to the frame size of information bits when performing the cyclic interleaving function. That is, when cyclic interleaving information bits received with a variable frame size, p and STEP variables having an optimal cyclic interleaving effect are experimentally measured and stored in the cyclic interleaving table 515. The cyclic interleaving table 513 outputs p and STEP values corresponding to the frame size signal output from the register 511. The cyclic interleaving controller 519 inputs p and STEP values output from the cyclic interleaving table 515 and then generates a read address for interleaving and outputting information bits in a cyclic interleaving scheme. The multiplexer 521 inputs a read address output from the diagonal interleaving controller 517 and the cyclic interleaving controller 519, and selects an address of an interleaving scheme corresponding to the interleaver type signal output from the register 511 and outputs the read address to the read address. The memory 523 sequentially inputs the information bits, and interleaves the information bits stored by the read address output from the multiplexer 521. The memory 523 is set to a size capable of storing information bits having a maximum frame size from information bits that are variably input.

In the configuration of FIG. 7, the diagonal interleaver 432 may be implemented alone, and may include a register 511, a diagonal interleaving table 513, a diagonal interleaving controller 517, and a memory 523. In this case, the multiplexer and the interleaver type signal are not used. In addition, when the cyclic interleaver 434 is implemented solely in the configuration of FIG. 7, the cyclic interleaver 434 may be configured as a register 511, a cyclic interleaving table 515, a cyclic interleaving controller 519, and a memory 523. The multiplexer and the interleaver type signal are not used here. Do not.

In the configuration of FIG. 7, the diagonal interleaving table 513 and the cyclic interleaving table 515 may be implemented using a ROM and a RAM, or may be implemented by combining logic elements. In addition, the diagonal interleaving controller 517 and the cyclic interleaving controller 519 may be implemented by combining logic elements, and may be implemented using a digital signal processing function.

8 and 9, which will be described below, illustrate an implementation of the diagonal interleaving scheme, and FIGS. 10 and 11 illustrate an implementation of the cyclic interleaving scheme. In addition, the interleaver described below is described with an example having an input buffer.

A first diagonal interleaving to a third diagonal interleaving operation will be described with reference to the configuration of the interleaver 430 as shown in FIG. 7.

First, FIG. 8 is a flowchart illustrating an operation of first diagonal interleaving. Referring to FIG. 8, the first diagonal interleaving is a method of reading and writing data by viewing a sequence of input bits as an M * N matrix. Referring to the first diagonal interleaving, when the information bit d _k is first input, the information is stored in the address old_addr [k] for sequentially storing the information bits input in step 611 in the memory 523, and the size k of the frame data is changed. Set it. Where k is a variable representing the size of input frame data. Thereafter, in step 613, the row and column variables (M * N) of the data frame for diagonal interleaving are determined. That is, in order to perform diagonal interleaving, the M and N values are set in the diagonal interleaving table with reference to the input frame data size variable k. The M and N values may be stored in the lookup table, and may be determined according to the size K of the input frame, and the optimal M and N may be calculated according to the size K of the input frame. In operation 615, the maximum common divisor of the M and N values is 1 [gcd (M, N) = 1)]. In this case, when the greatest common divisor of M and N is 1, the address of the first diagonal interleaving is calculated in the same manner as in Equation 1 in operation 617.

[Equation 1]

for (k = 0; kM * N-1; k ++)

new addr [k] = (M-1- (kmodN) * N + (kmod N)

As shown in Equation 1, the address of the output buffer is specified to interleave the input information bits stored in the input buffer and stored in the output buffer.

However, if the greatest common divisor of M and N is not 1 (gcd (M, N) ≠ 1) in step 615, the operation of the first diagonal interleaving is stopped and terminated in step 619.

An example of the first diagonal interleaving will be described. First, for example, when M = 6 and N = 5 stored in old_addr [k] of the input buffer, old_addr [k] = {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29}, the sequence stored in the output buffer new_addr [k] after the first diagonal interleaving is new_addr [k] = {25 21 17 13 9 0 26 22 18 14 5 1 27 23 19 10 6 2 28 24 15 11 7 3 29 20 16 12 8 4}.

When the above stored values are expressed in an M * N matrix, the data output after the first diagonal interleaving with the input data are shown in Table 1.

TABLE 1

However, the above first diagonal interleaving can be made only if the greatest common factor (M, N) = 1. However, assuming the case of M = 6 and N = 6 where the greatest common divisor (M, N) ≠ 1, there is a disadvantage in that interleaving is not performed at all and data is overwritten at the same address as shown in Table 2 below.

TABLE 2

The second diagonal interleaving method and the third diagonal interleaving method view a sequence of input information bits as an M * N matrix, and read and write data, but not only when the greatest common factor (M, N) = 1, but also the maximum common factor (M, Even if N) ≠ 1, interleaving is possible.

9 is a flowchart illustrating the operation of the second diagonal interleaving. Referring to FIG. 9, the second diagonal interleaving is a method of viewing an input bit sequence as an M * N matrix and reading and writing data, which can be applied to a case where the maximum common divisor of M and N is 1 and not 1. Diagonal interleaving. Referring to the second diagonal interleaving, when the information bit _dk is input, in step 631, the information is stored in the address old_addr [k] of the input buffer and the size k of the frame data is set. Where k is a variable representing the size of input frame data. Thereafter, in step 633, the row and column variables (M * N) of the data frame for diagonal interleaving are determined. After setting M and N, in step 635, an address of the second diagonal interleaving is calculated in the same manner as in Equation 2 below. In Equation 2, M and N are variable information of columns and rows, j is a variable increasing from 1 to M, and i is a variable increasing from 1 to N.

[Equation 2]

for (j = 0; jM; j ++)

for (i = 0; iN; i ++)

new addr [i + j + N] = i + (M-1- (i + j) mod M)) * N

As shown in Equation 2, the address of the output buffer is designated to interleave the input information bits stored in the input buffer and stored in the output buffer.

Using the second diagonal interleaving method, M = 6 and N = 5 having the greatest common divisor (M, N) = 1 are shown in Table 3 below.

TABLE 3

In addition, it can be seen that interleaving with Table 4 below is performed even when M = 6 and N = 6 where the greatest common divisor (M, N) ≠ 1.

TABLE 4

Third, in the case of the third diagonal interleaving scheme, the diagonal interleaving controller 517 may be implemented as Equation 3 below.

[Equation 3]

for (j = 0; jM; j ++)

for (i = 0; iN; i ++)

new addr [i + j + N] = i + ((i + j) mod M) * N

Using the diagonal interleaver 432, the input sequence is stored in a mapped memory address, and then data is read sequentially in rows or columns, or the input sequence is sequentially stored in memory in rows or columns, and then stored in the diagonal interleaving generator. Interleaving can be done by reading data one by one from an address.

Deinterleaving may be performed in the reverse order of the method used by the interleaver.

FIG. 10 is a flowchart illustrating an operation of first cyclic interleaving of input information bits using the cyclic interleaver 434 as shown in FIG. 7. In the first cyclic interleaving method according to an embodiment of the present invention, the input sequence is viewed as a single circle, and data can be read and written at regular intervals, thereby interleaving an input sequence having an arbitrary length.

Referring to the first cyclic interleaving operation with reference to FIG. 10, first, when the information bit d _k is input, the information is stored in the address old_addr [k] of the input buffer in step 711 and the size (SIZE) of the frame data is set. In step 713, the P and STEP variables are set. Herein, the P variable is a hop interval variable and determines the performance of the cyclic interleaver. Therefore, the P variable is experimentally determined to have an optimal effect. In addition, the STEP variable is a variable that shifts to the left or right at the position hopping by the P variable. Here, the STEP variable is an integer. After the p variable and the STEP variable are obtained as described above, in step 715, the maximum common factor of the hop variable P and the STEP variable is 1 [gcd (P, SIZE = 1)]. In this case, when the greatest common factor of the P and SIZE variables is 1, the first cyclic interleaving address is calculated with Equation 4 below.

[Equation 4]

for (i = 0; iSIZE; i ++)

new addr [i] = (p * i + STEP) mod SIZE

In Equation 4, the i variable is a variable representing the number of input frame data sizes, and is a variable that varies from 0 to SIZE (address number). The SIZE is the size of the interleaver, p is any natural number satisfying the greatest common divisor (SIZE, p) = 1, and STEP is an integer.

Here, for example, a sequence having SIZE = 30 stored in the first input buffer old_addr [k] old_addr [k] = {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29}, after first circular interleaving with p = 11 and STEP = 0, the sequence stored in buffer new_addr [k] is equal to new_addr [k] = {0 11 22 3 14 25 6 17 28 9 20 1 12 23 4 15 26 7 18 29 10 21 2 13 24 5 16 27 8 19}. When the stored values are expressed as M * N matrices, they are shown in Table 5.

TABLE 5

However, when using p = 6 having a maximum common divisor (SIZE, p) ≠ 1, if the first cyclic interleaving as shown in FIG. 10 is not interleaved, an error of overwriting data at the same address occurs.

Herein, assuming that a sequence of SIZE = 30 stored in the sequential address old_addr [k] of the first memory is input, and p = 11 and STEP = 0, the first cyclic interleaving scheme as shown in FIG. Interleaving result of the input sequence is expressed as M * N matrix as shown in Table 6 below.

TABLE 6

In order to compensate for the disadvantages of the first cyclic interleaving scheme as described above, a second cyclic interleaving scheme capable of interleaving even when the greatest common factor (SIZE, p) ≠ 1 is illustrated in FIG. 11. The second cyclic interleaving scheme illustrated in FIG. 11 represents an input sequence. In the matrix, the first cyclic interleaving method is used as a column, and the block interleaving method is used as a row.

Second, FIG. 11 is a flowchart illustrating the operation of the second cyclic interleaving, and is a cyclic interleaving scheme applicable to both the case where the maximum common factor of the P and STEP variables is 1 and not 1. Referring to the second cyclic interleaving operation, when the information bit _dk is input, in step 721, the information is stored in the sequential address old_addr [k] of the memory and the size SIZE of the frame data is set. Here, the SIZE is a variable representing the size of input frame data. In step 723, hop variables P and STEP variables for cyclic interleaving are determined. After setting the P and STEP variables, in step 725, the address of the second cyclic interleaving is calculated in the same manner as in Equation 5 below. In Equation 5 below, the i and k variables represent variables ranging from 0 to SIZE. j is an address variable and j is a number from 0 to d. P represents a hop variable for performing cyclic interleaving. STEP is a variable for determining a start time by shifting left or right by the STEP variable at the position determined by the hop variable P.

[Equation 5]

d = gcd (P, SIZE);

for (k-j = 0; jd; j ++)

for (i = 0; iSIZE / d; i ++, k ++)

new addr [k] = ((P * i + STEP) + j) mod SIZE

In Equation 5, (P * i + STEP) represents a cyclic interleaving operation, and j represents a block interleaving operation. Where SIZE is the size of the input data frame, p is any natural number, and STEP is an integer.

Here, the second cyclic interleaving result of SIZE = 30 and p = 11 is represented by the M * N matrix, as shown in Table 7 below.

TABLE 7

The result of Table 7 is the same as the result of the first cyclic interleaving. However, the case of p = 15 with the greatest common divisor (SIZE, p) ≠ is as follows.

TABLE 8

Using the above cyclic interleaving generator, store the input sequence in the mapped memory address, and then read the data sequentially in rows or columns, or sequentially store the input sequence in memory in rows or columns, and then address the cyclic interleaving generator. Interleaving can be done by reading data one by one.

Deinterleaving may be performed in the reverse order of the method used by the interleaver.

Fig. 12 is a diagram showing the performance of the cyclic interleaver used in the embodiment of the present invention with respect to the parallel chain structure, with the constraint length K = 3 of the configuration code, the input frame size is 104 bits, the number of repetitive decoding times, and the BPSK. It shows the BER (Bit Error Rate) characteristics of the simulation results in the modulation method, AWGN (Additive White Gaussian Noise) environment. Compared with the simulation results of generally used block interleaver and random interleaver. As shown in FIG. 12, the Eb / No of the cyclic interleaver is about 3 dB at 10 ⁻⁵ BER, and the block interleaver is 3.4 dB. Therefore, the cyclic interleaver is about 0.4 than the block interleaver at 10 ⁻⁵ BER. It can be seen that the performance is improved by dB.

13 shows the configuration of a specific embodiment of a turbo encoder according to an embodiment of the present invention.

Referring to FIG. 13, the first constituent encoder 410 encodes and outputs an input information bit, and exemplifies a case where the constraint length is K = 3. The interleaver 430 interleaves the information bits according to a set rule to change the order of the information bits. 7 may be configured as shown in FIG. 7, and in this case, the first to third diagonal interleaving or the first to second cyclic interleaving may be implemented. The second constituent encoder 420 encodes and outputs the output of the interleaver 430, and illustrates a case where the constraint length is K = 3.

The first tail bit generator 450 may include: a first switch 455 connected to an input terminal of the first constituent encoder 410; an exclusive ocate 451 for exclusively ORing the outputs of the memory elements 412 and 413 of the first constituent encoder 410; The bit generator 453 initializes the memory of the first component encoder 410 and generates a frame termination signal according to the output of the exclusive oragate 451 and applies it to the first switch 455. When the frame ends, the first tail bit generator 450 generates a frame termination signal while initializing the memory elements of the first component encoder 410 by connecting the first switch 455 to the first component encoder 410. The second tail bit generator 460 includes: a second switch 465 connected to an input terminal of the first constituent encoder 420; an exclusive oragate 461 for exclusively ORing the outputs of the memory elements 422 and 423 of the first constituent encoder 420; The bit generator 463 initializes the memory of the first component encoder 420 and generates a frame termination signal to be applied to the second switch 465 according to the output of the exclusive oragate 461. When the frame ends, the first tail bit generator 460 is connected to the second component encoder 420 to initialize the memory elements of the second component encoder 420 and generates a frame termination signal.

The first puncturer 470 punctures the information bits. The second puncturer 480 inputs the outputs of the first constituent encoder 410 and the second constituent encoder 420 and punctures the encoded data. The first puncturer 470 and the second puncturer 480 perform a function for adjusting the data rate. The multiplexer 491 inputs the outputs of the bit generators 453 and 463 and multiplexes both outputs. The third switch 493 switches the tail bits multiplexed and output from the multiplexer 491 to the transmission channel at the end of the frame.

Accordingly, the first tail bit generator 450 generates tail bits for terminating the first component encoder 410, and the second tail bit generator 460 generates tail bits for terminating the second component encoder 420. In addition, the first puncturer 470 and the second puncturer 480 perform a function for adjusting and outputting the transmission rate in a standardized state.

Referring to FIG. 13, which is assumed to be a configuration of a parallel turbo encoder, the turbo code uses tail bits to terminate component encoders 410 and 420. At this time, since the constituent code of the turbo code is an organization code, the continuous input of 0 like the unstructured convolutional code does not initialize the memories 412-413 and 422-423 of the constituent encoders 410 and 420. However, the constituent encoders 410 and 420 keep the memory closest to the input to 0 by inputting a value equal to the sum of the feedback values to the input using the tail bit generator. Therefore, the turbo encoder requires as many tail bits as the number of memories of each component code. In FIG. 13, the switch 455 connected to the input terminal of the first component encoder 410 and the switch 465 connected to the input terminal of the second component encoder 420 are switched at the time of generating the tail bit. Thereafter, the parity bits of the tail bits output to the first component encoder 410 and the second component encoder 420 are output to the second puncturer 480, and the tail bits generated by the tail bit generator are switched by the third switch 493. Outputted with information bit Xk.

In order to reduce the complexity of the hardware production, it is good to make the transmission rate of two. However, in the case of a data rate such as 384 kbps, using a turbo code with a code rate of 1/2 cannot make the data rate an exponential power of two. Therefore, in such a case, it is possible to use a turbo code having a code rate of 3/8, which is formed by punching a turbo code having a code rate of 1/2. Especially for the 144kbps data rate, the turbo code with 1/2 code rate is punctured to make the code rate 9/16. Tables 9 and 10 below show examples of 9/16 perforation matrices.

TABLE 9

TABLE 10

In Tables 9 and 10, the information bits correspond to the input information bits _dk and are applied to the first puncturer 470, and RSC1 is applied to the second puncturer 480 as parity bits output from the first configuration encoder 410. In this case, Table 9 shows an example of puncturing the parity bits output from the constituent encoders 410 and 420. In this case, there are several places where zeros are continuously displayed in the portion corresponding to the parity bits. That is, when the parity bit is punctured to match the transmission rate, there is a place where zero appears continuously in the part corresponding to the parity bit as shown in the underlined part of Table 9. However, in the embodiment of the present invention, since the configuration encoders 410 and 420 have only two memories, a fatal error may occur if two or more parity bits are not transmitted consecutively. Therefore, in the embodiment of the present invention, the information bits are punctured as shown in Table 10 above. Table 10 is the same 9/16 puncturing matrix as Table 9, but does not transmit two or more parity bits in succession. However, since the information bits are punctured, the performance is not good when the number of iteration decoding is small. However, if the number of iterative decoding is large, the information bits can be predicted almost accurately using additional information.

As described above, by reducing the size of the interleaver existing in the turbo encoder according to the embodiment of the present invention and presenting an interleaver having excellent performance in the turbo code, it is not applicable to voice and data transmission of a communication system due to the limitation of time delay. Turbo codes can be used for voice and data transmission. In addition, by using an interleaver with excellent performance, the complexity of the decoder can be reduced by reducing the number of states of the constituent encoder of the turbo encoder.

Claims (16)

A method of diagonally interleaving input information bits having a table for storing row and column information of interleaving respectively corresponding to a variable frame size, the method comprising: Inputting a frame size signal corresponding to the input of the information bit; determining row and column information corresponding to an input frame size in the table; Diagonally interleaving and outputting information bits of a corresponding frame according to the row and column information. The diagonal interleaving method of claim 1, wherein the diagonal interleaving is performed by Equation 1 below. [Equation 1] for (k = 0; kM * N-1; k ++) new addr [k] = (M-1- (kmodN) * N + (kmod N) In Equation 1, M and N are row and column information of a frame, and k (= M * N) is a frame size. The method of claim 1, wherein the diagonal interleaving is performed by Equation 2. [Equation 2] for (j = 0; jM; j ++) for (i = 0; iN; i ++) new addr [i + j + N] = i + (M-1- (i + j) mod M)) * N In Equation 2, M and N are row and column information of a frame, and M * N is a frame size. The method of claim 1, wherein the diagonal interleaving is performed by Equation 3 below. [Equation 3] for (j = 0; jM; j ++) for (i = 0; iN; i ++) new addr [i + j + N] = i + ((i + j) mod M) * N In Equation 3, M and N are row and column information of a frame, and M * N is a frame size. A method of circularly interleaving an input information bit having a table storing hop variable and step variable information of interleaving corresponding to a variable frame size, respectively, Inputting a frame size signal corresponding to the information bit input; Determining hop and step values corresponding to the frame size in the table; The cyclic interleaving method according to the determined hop and step value to hop and shift the input frame information bits to output the cyclic interleaving. 6. The cyclic interleaving method according to claim 5, wherein the cyclic interleaving process is performed by Equation 4. [Equation 4] for (i = 0; iSIZE; i ++) new addr [i] = (p * i + STEP) mod SIZE In Equation 4, SIZE is a frame size, p is a hop variable for cyclic interleaving, and STEP is an integer as a step variable for shifting at a hopped position. 6. The cyclic interleaving method according to claim 5, wherein the cyclic interleaving process is performed by Equation 5. [Equation 5] d = gcd (P, SIZE); for (k-j = 0; jd; j ++) for (i = 0; iSIZE / d; i ++, k ++) new addr [k] = ((P * i + STEP) + j) mod SIZE In Equation 5, SIZE is a frame size, p is a hop variable for cyclic interleaving, and STEP is an integer as a step variable for shifting at a hopped position. In the turbo encoding device, At least two components, comprising constituent encoders encoding input information bits, a table for storing row and column information corresponding to variable frame sizes, and setting row and column information corresponding to a transmitted frame size. And a diagonal interleaver configured to diagonally interleave information bits of a corresponding frame according to the row and column information, and connect the information bits to an input terminal of the at least one component encoder. The method of claim 8, wherein the diagonal interleaver, A diagonal interleaving table for storing row and column information for diagonal interleaving corresponding to the frame size of the input information bits; A diagonal interleaving controller for generating a read address for diagonally interleaving information bits of a corresponding frame according to the row and column information according to Equation 6 below; And a memory configured to sequentially store the input information bits and to diagonally interleave the stored information bits by the read address. [Equation 6] for (k = 0; kM * N-1; k ++) new addr [i] = (M-1- (kmodN) * N + (kmod N) In Equation 6, M and N are row and column information of a frame, and k (= M * N) is a frame size. The method of claim 8, wherein the diagonal interleaver, A diagonal interleaving table for storing row and column information for diagonal interleaving corresponding to the frame size of the input information bits; A diagonal interleaving controller for generating a read address for diagonally interleaving information bits of a corresponding frame according to the row and column information according to Equation 7 below; And a memory configured to sequentially store the input information bits and to diagonally interleave the stored information bits by the read address. [Equation 7] for (j = 0; jM; j ++) for (i = 0; iN; i ++) new addr [i + j + N] = i + (M-1- (i + j) mod M)) * N In Equation 7, M and N are row and column information of a frame, and k (= M * N) is a frame size. The method of claim 8, wherein the diagonal interleaver, A diagonal interleaving table for storing row and column information for diagonal interleaving corresponding to the frame size of the input information bits; A diagonal interleaving controller for generating a read address for diagonally interleaving the information bits of a corresponding frame according to the row and column information; And a memory configured to sequentially store the input information bits and to diagonally interleave the stored information bits by the read address. [Equation 8] for (j = 0; jM; j ++) for (i = 0; iN; i ++) new addr [i + j + N] = i + ((i + j) mod M) * N In Equation 8, M and N are row and column information of a frame, and k (= M * N) is a frame size. In the turbo encoding device, At least two component encoders for encoding input information bits; And a table for storing hop and step information corresponding to the variable frame size, and setting hop and step information corresponding to the transmitted frame size, and then circularly interleaving information bits of corresponding framing according to the hop and step information. And a cyclic interleaver connected to an input of the at least one constituent encoder. The method of claim 12, wherein the cyclic interleaver, A cyclic interleaving table for storing hop and step information for cyclic interleaving corresponding to the frame size of the input information bits; A cyclic interleaving controller for generating a read address for cyclic interleaving of information bits of a corresponding frame according to the hop and step information according to Equation (9); And a memory configured to sequentially store the input information bits and to cyclically interleave the stored information bits by the read address. [Equation 9] for (i = 0; iSIZE; i ++) new addr [k] = (p * i + STEP) mod SIZE In Equation 9, SIZE is a frame size, p is a hop variable for cyclic interleaving, and STEP is an integer as a step variable for shifting at a hopping position. The method of claim 12, wherein the cyclic interleaver, A cyclic interleaving table for storing hop and step information for cyclic interleaving corresponding to the frame size of the input information bits; A cyclic interleaving controller for generating a read address for cyclic interleaving of information bits of a corresponding frame according to the hop and step information according to Equation 10 below; And a memory configured to sequentially store the input information bits and to cyclically interleave the stored information bits by the read address. [Equation 10] d = gcd (P, SIZE); for (k-j = 0; jd; j ++) for (i = 0; iSIZE / d; i ++, k ++) new addr [k] = ((P * i + STEP) + j) mod SIZE In Equation 10, SIZE is a frame size, p is a hop variable for cyclic interleaving, and STEP is an integer as a step variable for shifting at a hopped position. In the turbo encoding device, At least two component encoders for encoding input information bits; An interleaver for interleaving information bits of a frame corresponding to the transmitted frame size and connecting the input bits to the input terminal of the at least one component encoder; A tail bit generator provided with a number corresponding to the constituent encoders and generating tail bits for terminating the frame of the input frame data by cutting off the input of the constituent encoders at the end of the frame and analyzing a memory element value of the constituent encoders; Turbo coding device, characterized in that consisting of. In the turbo encoding device, At least two component encoders for encoding input information bits; An interleaver for interleaving information bits of a frame corresponding to the transmitted frame size and connecting the input bits to the input terminal of the at least one component encoder; A number corresponding to the constituent encoders, and after the input of the constituent encoders is interrupted at the end of the frame, the memory elements of the constituent encoders are initialized based on the analysis of the memory element values, and at the same time the terminal of the input frame data is terminated. Tailbit generators generating tailbits, A first puncturer for puncturing the input information bits at a set ratio, and inserting and outputting tail bits output from the tail bit generators as a frame termination signal at the end of the frame; And a second puncturer configured to adjust the transmission rate of the encoded data by puncturing at a predetermined rate after inputting the outputs of the constituent encoders.