KR100447094B1 - Method for forming a silicide layer of a semiconductor device - Google Patents
Method for forming a silicide layer of a semiconductor device Download PDFInfo
- Publication number
- KR100447094B1 KR100447094B1 KR10-2002-0035690A KR20020035690A KR100447094B1 KR 100447094 B1 KR100447094 B1 KR 100447094B1 KR 20020035690 A KR20020035690 A KR 20020035690A KR 100447094 B1 KR100447094 B1 KR 100447094B1
- Authority
- KR
- South Korea
- Prior art keywords
- ions
- semiconductor substrate
- present
- silicide layer
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims abstract description 39
- 150000001793 charged compounds Chemical class 0.000 claims abstract description 15
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000006698 induction Effects 0.000 abstract description 9
- 238000005280 amorphization Methods 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- -1 P 2 + Chemical class 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 실리사이드 레이어 형성방법에 관한 것으로, 본 발명에서는 일련의 PAI 공정(Pre-Amorphization Implantation process)에 이용되는 반도체 기판의 비정질화 유도매체를 종래의 원자이온(Atomic ion)에서, 분자이온(Particle ion)으로 변경한다.The present invention relates to a method for forming a silicide layer of a semiconductor device. In the present invention, an amorphous induction medium of a semiconductor substrate used in a series of pre-amorphization implantation processes (PAI) is used in a conventional atomic ion. Change to particle ions.
이러한 분자이온은 원자이온에 비해, 그 중량, 사이즈 등이 매우 크기 때문에, 본 발명의 체제 하에서, 반도체 기판의 표면은 소량의 이온이 주입된 상황 하에서도 그 격자손상이 광범위하게 이루어져, 만족할 만한 수준의 비정질화를 이룰 수 있게 되며, 결국, 일련의 PAI 공정이 완료된 후에도, "게이트 전극, 소오스/드레인 전극" 등으로 이루어진 액티브 디바이스는 그 고유특성이 크게 변하지 않게 된다.Since the molecular ions are much larger in weight and size than the atomic ions, under the framework of the present invention, the surface of the semiconductor substrate has a wide range of lattice damage even in a situation where a small amount of ions have been implanted, which is a satisfactory level. After the series of PAI processes are completed, an active device made of a "gate electrode, a source / drain electrode," or the like does not change its inherent characteristics significantly.
이러한 본 발명의 실시에 의해, 분자이온의 불필요한 영향력이 최소화되어, 액티브 디바이스의 고유특성이 크게 변하지 않게 되는 경우, 최종 완성되는 반도체 소자는 그 품질이 대폭 향상될 수 있게 된다.By the implementation of the present invention, when the unnecessary influence of the molecular ions is minimized, and the intrinsic characteristics of the active device are not significantly changed, the quality of the finally completed semiconductor device can be greatly improved.
Description
본 발명은 반도체 소자의 실리사이드 레이어 형성방법에 관한 것으로, 좀더 상세하게는 일련의 선 비정질화 이온주입 공정(PAI process:Pre-Amorphization Implantation process; 이하, "PAI 공정"이라 칭함)에 이용되는 반도체 기판의 비정질화 유도매체를 종래의 원자이온(Atomic ion)에서, 중량, 사이즈 등이 상대적으로 큰 분자이온(Particle ion)으로 변경하고, 이를 통해, 반도체 기판이 적은 량의 분자이온 만으로도 적절히 비정질화 될 수 있도록 유도함으로써, 이온의 과량 주입으로 인한 액티브 디바이스의 불필요한 특성변화를 미리 차단시킬 수 있도록 하는 반도체 소자의 실리사이드 레이어 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicide layer of a semiconductor device, and more particularly, to a semiconductor substrate used in a series of pre-amorphization implantation processes (hereinafter referred to as "PAI processes"). Amorphous induction medium of the Atomic ion, from the conventional ion (Atomic ion), the weight, size, etc. relatively large molecular ions (Particle ions), through which the semiconductor substrate can be properly amorphous by only a small amount of molecular ions The present invention relates to a method of forming a silicide layer of a semiconductor device, which can prevent an unnecessary characteristic change of an active device due to an excessive injection of ions in advance.
근래에, 반도체 소자의 콘택 저항문제가 반도체 소자의 전체적인 기능을 결정짓는 주요 팩터들 중의 하나로 대두되면서, 이 콘택 저항을 줄일 수 있는 다양한기술방안이 모색되고 있다.In recent years, as the problem of contact resistance of semiconductor devices has emerged as one of the major factors that determine the overall function of semiconductor devices, various technical solutions to reduce the contact resistance have been sought.
이러한 기술방안중의 하나로써, 반도체 소자의 게이트 전극 및 소오스/드레인 전극 상에 예컨대, 티타늄, 코발트 등의 금속을 포함하는 실리사이드 레이어를 형성하고, 이 실리사이드 레이어를 통해 반도체 소자의 콘택 저항 저감을 유도하는 이른바, "셀리사이드(SALICIDE:Self-Aligned Silicide)" 기술이 개발되어 폭 넓게 보급되고 있다.As one of the technical solutions, a silicide layer including a metal such as titanium or cobalt is formed on the gate electrode and the source / drain electrode of the semiconductor device, and the silicide layer reduces the contact resistance of the semiconductor device. So-called "SALICIDE: Self-Aligned Silicide" technology has been developed and widely used.
최근 들어, 반도체 소자의 선폭이 초미세화 되면서, 게이트 전극의 길이 또한 점차 줄어들고 있는 바, 이 상황에서는 각 전극의 전기저항, 표면저항 등이 매우 높아질 수밖에 없기 때문에, 별도의 조치가 취해지지 않는 한, 게이트 전극 상에 실리사이드 레이어를 형성하기가 매우 힘들어질 수밖에 없다.In recent years, as the line width of the semiconductor device becomes very fine, the length of the gate electrode is gradually decreasing. In this situation, since the electric resistance and the surface resistance of each electrode have to be very high, unless special measures are taken, It is very difficult to form a silicide layer on the gate electrode.
종래의 경우에는 이러한 어려움을 해결하기 위하여, 본격적인 실리사이드 레이어 형성공정 이전에 반도체 기판의 전면에 일련의 원자이온을 주입하는 이른바, "PAI 공정"을 시행하고 있다.In the related art, in order to solve this difficulty, a so-called "PAI process" is performed in which a series of atomic ions are injected into the entire surface of the semiconductor substrate before the full silicide layer forming process.
이러한 PAI 공정이 시행되면, 반도체 기판의 표면은 주입되는 원자이온과의 충돌에 의해 비정질화 되어, 그 그레인 사이즈가 크게 줄어들게 됨으로써, 전기저항, 표면저항 등이 대폭 낮아지게 되며, 결국, 게이트 전극의 길이가 초미세화된 상황 하에서도, 실리사이드 레이어가 형성될 수 있는 안정적인 기반환경을 제공할 수 있게 된다.When the PAI process is performed, the surface of the semiconductor substrate is amorphized by the collision with the implanted atomic ions, and the grain size is greatly reduced, so that the electrical resistance, the surface resistance, and the like are greatly reduced. Even under extremely fine lengths, it is possible to provide a stable foundation in which silicide layers can be formed.
그런데, 이러한 종래의 PAI 공정 체제 하에서, 반도체 기판의 표면은 주입된 원자이온의 양에 비례하여, 비정질화 정도가 결정되기 때문에, 반도체 기판의 표면을 만족할 만한 수준으로 비정질화 시키기 위해서는 다량의 원자이온이 주입될 수밖에 없다.However, under such a conventional PAI process, since the surface of the semiconductor substrate is determined in proportion to the amount of atomic ions implanted therein, a large amount of atomic ions is required to make the surface of the semiconductor substrate amorphous to a satisfactory level. This can only be injected.
그러나, 이처럼, 다량의 원자이온이 주입되는 경우, 기판 표면의 비정질화는 어느 정도 달성할 수 있지만, 이 경우, 주입된 원자이온의 영향으로 인해, "게이트 전극, 소오스/드레인 전극" 등으로 이루어진 액티브 디바이스는 그 특성이 원하지 않은 방향으로 크게 변할 수밖에 없으며, 결국, 최종 완성되는 반도체 소자는 그 품질이 대폭 낮아질 수밖에 없다.However, in the case where a large amount of atomic ions are implanted as described above, amorphousness of the surface of the substrate can be achieved to some extent, but in this case, due to the influence of the implanted atomic ions, it is composed of a "gate electrode, a source / drain electrode" and the like. The active device is forced to change its characteristics in an undesired direction, and finally, the final finished semiconductor device is inevitably degraded in quality.
물론, 주입되는 원자이온의 양을 줄이면, 액티브 디바이스의 특성변화를 어느 정도 차단시킬 수 있겠지만, 이 경우, 반도체 기판 표면의 비정질화가 정상적으로 이루어질 수 없는 또 다른 문제점이 야기될 수밖에 없으며, 결국, 종래 에서는 상술한 액티브 디바이스 특성변화의 문제점을 깊이 인식하면서도, 이에 대한 구체적인 대응방안을 마련하지 못하고 있는 실정이다.Of course, reducing the amount of implanted atomic ions may block the change of the characteristics of the active device to some extent, but in this case, there is no doubt that there is another problem that the amorphous state of the surface of the semiconductor substrate cannot be normally performed. While deeply aware of the above-described problems of the characteristic change of the active device, there is no specific countermeasure.
따라서, 본 발명의 목적은 PAI 공정에 이용되는 반도체 기판의 비정질화 유도매체를 종래의 원자이온에서, 중량, 사이즈 등이 상대적으로 큰 분자이온으로 변경하고, 이를 통해, 반도체 기판이 적은 량의 분자이온 만으로도 적절히 비정질화 될 수 있도록 유도함으로써, 이온의 과량 주입으로 인한 액티브 디바이스의 불필요한 특성변화를 미리 차단시키는데 있다.Accordingly, an object of the present invention is to change the amorphous induction medium of the semiconductor substrate used in the PAI process from a conventional atomic ion to a molecular ion having a relatively large weight, size, and the like, whereby the semiconductor substrate has a small amount of molecules. By inducing ions to be properly amorphous by only ions, it is possible to prevent unnecessary changes in characteristics of the active device due to excessive injection of ions.
본 발명의 또 다른 목적들은 다음의 상세한 설명과 첨부된 도면으로부터 보다 명확해질 것이다.Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.
도 1 내지 도 3은 본 발명에 따른 반도체 소자의 실리사이드 레이어 형성방법은 순차적으로 도시한 공정순서도.1 to 3 is a flowchart illustrating a method of forming a silicide layer of a semiconductor device according to the present invention sequentially.
상기와 같은 목적을 달성하기 위하여 본 발명에서는 반도체 기판의 소자영역에 소오스/드레인 전극 및 측벽 스페이서를 갖는 게이트 전극을 형성하는 단계와, 소오스/드레인 전극 및 게이트 전극을 포괄하는 반도체 기판의 전면에 분자이온을 주입하는 단계와, 분자이온이 주입된 반도체 기판의 전면에 실리사이드 레이어를 형성하는 단계의 조합으로 이루어지는 반도체 소자의 실리사이드 레이어 형성방법을 개시한다.In order to achieve the above object, the present invention provides a method of forming a gate electrode having a source / drain electrode and a sidewall spacer in an element region of a semiconductor substrate, and a molecule on the front surface of the semiconductor substrate including the source / drain electrode and the gate electrode. Disclosed is a method of forming a silicide layer of a semiconductor device comprising a combination of implanting ions and forming silicide layers on the entire surface of a semiconductor substrate implanted with molecular ions.
이하, 첨부된 도면을 참조하여, 본 발명에 따른 반도체 소자의 실리사이드 레이어 형성방법을 좀더 상세히 설명하면 다음과 같다.Hereinafter, a silicide layer forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1에 도시된 바와 같이, 먼저, 본 발명에서는 반도체 기판(1)의 소자영역에 게이트 산화막(4) 및 측벽 스페이서(5)를 구비하고 있으면서, 예컨대, 폴리 실리콘 재질을 갖는 게이트 전극(3)을 형성하고, 이 게이트 전극(3)의 양측에 소오스/드레인 전극(2)을 형성함으로써, 반도체 기판(1)의 소자 분리막(6) 사이에 완성된 구조의 액티브 디바이스를 위치시킨다.As shown in FIG. 1, first, in the present invention, the gate electrode 3 having the gate oxide film 4 and the sidewall spacers 5 in the element region of the semiconductor substrate 1 is made of, for example, a polysilicon material. And the source / drain electrodes 2 are formed on both sides of the gate electrode 3 to position the active device of the completed structure between the device isolation films 6 of the semiconductor substrate 1.
이어서, 본 발명에서는 게이트 전극(3) 및 소오스/드레인 전극(2)이 형성된 반도체 기판(1)을 이온 주입 장치(도시안됨)에 탑재시킨 후, 도 2에 도시된 바와 같이, 게이트 전극(3) 및 소오스/드레인 전극(2)을 포함하는 반도체 기판(1)의 전면에 비정질화 유도이온(10)을 주입한다. 이 경우, 반도체 기판(1)의 표면은 주입되는 비정질화 유도이온(10)과의 충돌에 의해 격자구조가 손상되어, 신속히 비정질화 되고, 그 결과, 그레인 사이즈가 크게 줄어들게 됨으로써, 전기저항, 표면저항등이 대폭 낮아지게 되며, 결국, 게이트 전극(3)의 길이가 초미세화된 상황 하에서도, 실리사이드 레이어가 추후 형성될 수 있는 안정적인 기반환경을 제공할 수 있게 된다.Subsequently, in the present invention, the semiconductor substrate 1 on which the gate electrode 3 and the source / drain electrode 2 are formed is mounted in an ion implantation apparatus (not shown), and as shown in FIG. 2, the gate electrode 3 ) And the amorphous induction ion 10 is implanted into the entire surface of the semiconductor substrate 1 including the source and drain electrodes 2. In this case, the surface of the semiconductor substrate 1 is damaged by the collision with the implanted amorphous induction ions 10, and quickly becomes amorphous, and as a result, the grain size is greatly reduced, so that the electrical resistance, the surface The resistance and the like are greatly lowered, and thus, even in a situation where the length of the gate electrode 3 is extremely fine, it is possible to provide a stable base environment in which the silicide layer can be formed later.
이때, 본 발명에서는 앞의 비정질화 유도이온(10)으로, 예컨대, P2+, As2+, Mo2+ 등과 같은 분자이온을 사용한다. 이러한 분자이온은 P+, As+, Mo+ 등과 같은 원자이온에 비해, 그 중량, 부피(사이즈) 등이 매우 크기 때문에, 원자이온보다 적은 량이 주입되면서도, 반도체 기판(1)의 격자구조를 같은 량의 원자이온에 비해 좀더 손쉽게 손상시킬 수 있게 되며, 결국, 반도체 기판(1)의 비정질화를 원자이온에 비해 좀더 효과적으로 달성시킬 수 있게 된다.At this time, in the present invention, as the amorphous induction ion 10, for example, molecular ions such as P 2 +, As 2 +, Mo 2 +, and the like are used. Since the molecular ions are very large in weight, volume (size), etc., compared to atomic ions such as P +, As +, Mo +, and the like, the amount of atoms in the lattice structure of the semiconductor substrate 1 is reduced even though the amount is less than that It can be more easily damaged than ions, and eventually, the amorphous state of the semiconductor substrate 1 can be more effectively achieved than the atomic ions.
종래의 경우, 비정질화 유도이온으로 중량이 비교적 가벼운 원자이온을 사용하였기 때문에, 종래의 체제 하에서, 반도체 기판의 표면을 만족할 만한 수준으로 비정질화 시키기 위해서는 주입되는 원자이온의 양을 과도하게 늘릴 수밖에 없었으며, 결국, 주입된 과량의 원자이온으로 인해 액티브 디바이스의 고유특성은 크게 변할 수밖에 없었다.In the conventional case, since a relatively light weight of ion ions was used as amorphous induction ions, in order to amorphousize the surface of the semiconductor substrate to a satisfactory level under the conventional regime, the amount of atomic ions to be implanted was excessively increased. As a result, the inherent characteristics of the active device were greatly changed due to the excessive atomic ions.
그러나, 본 발명의 경우, 비정질화 유도이온으로 기존의 원자이온에 비해 그 사이즈, 중량 등이 크고 무거운 분자이온을 사용하기 때문에, 본 발명의 체제 하에서, 반도체 기판(1)의 표면은 소량의 이온이 주입된 상황 하에서도 그 격자손상이 광범위하게 이루어져, 만족할 만한 수준의 비정질화를 이룰 수 있게 되며, 결국, 일련의 PAI 공정이 완료된 후에도, "게이트 전극(3), 소오스/드레인 전극(2)" 등으로 이루어진 액티브 디바이스는 그 고유특성이 크게 변하지 않게 된다.However, in the case of the present invention, since the size, weight, etc. of molecular ions are larger and heavier than conventional atomic ions as amorphous induction ions, the surface of the semiconductor substrate 1 has a small amount of ions under the framework of the present invention. Even in this implanted situation, the lattice damage is extensive, resulting in a satisfactory level of amorphousness. Consequently, even after a series of PAI processes are completed, the "gate electrode 3, the source / drain electrode 2, ", Etc., the active device does not change its inherent characteristics significantly.
물론, 이러한 본 발명의 실시에 의해, 분자이온의 불필요한 영향력이 최소화되어, 액티브 디바이스의 고유특성이 크게 변하지 않게 되는 경우, 최종 완성되는 반도체 소자는 그 품질이 대폭 향상될 수 있게 된다.Of course, by the practice of the present invention, when the unnecessary influence of molecular ions is minimized, and the inherent characteristics of the active device do not change significantly, the quality of the finally completed semiconductor device can be significantly improved.
한편, 상술한 과정을 통해, 반도체 디바이스의 비정질화가 완료되면, 본 발명에서는 "게이트 전극(3), 소오스/드레인 전극(2)" 등으로 이루어진 액티브 디바이스를 포함하는 반도체 기판(1)을 세정베스(Cleaning-bath:도시안됨)에 탑재시킨 후, 세정액, 예컨대, 불산(HF)으로 기판(1)을 습식세정(Wet cleaning)하여, 기판 (1) 표면에 잔류하는 자연 산화막을 제거한다.On the other hand, when the amorphous state of the semiconductor device is completed through the above-described process, according to the present invention, the semiconductor substrate 1 including the active device made of the "gate electrode 3, the source / drain electrode 2", etc. is cleaned. After mounting in a cleaning-bath (not shown), the substrate 1 is wet cleaned with a cleaning liquid such as hydrofluoric acid (HF) to remove the natural oxide film remaining on the surface of the substrate 1.
이어서, 본 발명에서는 액티브 디바이스를 포함하는 반도체 기판(1)을 디개스 챔버(Degas chamber:도시안됨)에 탑재시킨 후, 일련의 디개스 프로세스를 진행하여, 기판(1) 표면에 잔류하는 수분, 불순물 등을 제거한다.Subsequently, in the present invention, the semiconductor substrate 1 including the active device is mounted in a degas chamber (not shown), and then a series of degas processes are performed, whereby water remaining on the surface of the substrate 1, Remove impurities.
앞의 과정을 통해, 일련의 기판(1) 표면 클리닝 과정이 완료되면, 본 발명에서는 액티브 디바이스를 포함하는 반도체 기판(1)을 예컨대, 스퍼터링 챔버(도시안됨)에 탑재시킨 후, 해당 반도체 기판(1)의 전면으로 예컨대, 티타늄, 코발트 등의 금속을 스퍼터링 시킴으로써, 도 3에 도시된 바와 같이, 반도체 기판(1)의 전면에 일련의 실리사이드 레이어(7)를 형성시킨다.Through the foregoing process, when a series of surface cleaning processes of the substrate 1 are completed, in the present invention, the semiconductor substrate 1 including the active device is mounted in, for example, a sputtering chamber (not shown), and then the semiconductor substrate ( By sputtering a metal such as titanium or cobalt on the front surface of 1), a series of silicide layers 7 are formed on the front surface of the semiconductor substrate 1 as shown in FIG.
이후, 본 발명에서는 실리사이드 레이어(7)가 형성된 반도체 기판(1)을 예컨대, 속성 열처리 챔버(Rapid thermal process chamber:도시안됨)에 탑재시킨 후, 일련의 빠른 열처리 공정을 진행시켜, 반도체 기판(1)상에 형성된 실리사이드 레이어(7)를 안정화시킴으로써, 일련의 실리사이드 레이어 형성공정을 안정적으로 마무리한다.Subsequently, in the present invention, the semiconductor substrate 1 having the silicide layer 7 formed thereon is mounted in, for example, a rapid thermal process chamber (not shown), and then a series of rapid heat treatment processes are performed to thereby provide a semiconductor substrate 1. By stabilizing the silicide layer 7 formed on the step S, the series of silicide layer forming steps is stably finished.
이상에서 상세히 설명한 바와 같이, 본 발명에서는 일련의 PAI 공정에 이용되는 반도체 기판의 비정질화 유도매체를 종래의 원자이온에서, 분자이온으로 변경한다.As described in detail above, in the present invention, the amorphous induction medium of the semiconductor substrate used in the series of PAI processes is changed from conventional atomic ions to molecular ions.
이러한 분자이온은 원자이온에 비해, 중량, 사이즈 등이 매우 크기 때문에, 본 발명의 체제 하에서, 반도체 기판의 표면은 소량의 이온이 주입된 상황 하에서도 그 격자손상이 광범위하게 이루어져, 만족할 만한 수준의 비정질화를 이룰 수 있게 되며, 결국, 일련의 PAI 공정이 완료된 후에도, "게이트 전극, 소오스/드레인 전극" 등으로 이루어진 액티브 디바이스는 그 고유특성이 크게 변하지 않게 된다.Since the molecular ions are much larger in weight, size, etc. than the atomic ions, under the regime of the present invention, the surface of the semiconductor substrate has a wide range of lattice damage even in a situation where a small amount of ions are implanted, thereby achieving a satisfactory level. Amorphization can be achieved, and eventually, even after a series of PAI processes are completed, an active device made of a "gate electrode, a source / drain electrode," or the like does not significantly change its inherent characteristics.
이러한 본 발명의 실시에 의해, 분자이온의 불필요한 영향력이 최소화되어, 액티브 디바이스의 고유특성이 크게 변하지 않게 되는 경우, 최종 완성되는 반도체 소자는 그 품질이 대폭 향상될 수 있게 된다.By the implementation of the present invention, when the unnecessary influence of the molecular ions is minimized, and the intrinsic characteristics of the active device are not significantly changed, the quality of the finally completed semiconductor device can be greatly improved.
앞에서, 본 발명의 특정한 실시예가 설명되고 도시되었지만 본 발명이 당업자에 의해 다양하게 변형되어 실시될 가능성이 있는 것은 자명한 일이다. 이와 같은 변형된 실시예들은 본 발명의 기술적사상이나 관점으로부터 개별적으로 이해되어서는 안되며 이와 같은 변형된 실시예들은 본 발명의 첨부된 특허청구의 범위안에 속한다 해야 할 것이다.While specific embodiments of the invention have been described and illustrated above, it will be apparent that the invention may be embodied in various modifications by those skilled in the art. Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0035690A KR100447094B1 (en) | 2002-06-25 | 2002-06-25 | Method for forming a silicide layer of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0035690A KR100447094B1 (en) | 2002-06-25 | 2002-06-25 | Method for forming a silicide layer of a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040000755A KR20040000755A (en) | 2004-01-07 |
| KR100447094B1 true KR100447094B1 (en) | 2004-09-04 |
Family
ID=37312571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0035690A KR100447094B1 (en) | 2002-06-25 | 2002-06-25 | Method for forming a silicide layer of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100447094B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208437A (en) * | 1999-01-08 | 2000-07-28 | United Microelectronics Corp | Method for forming silicide layer |
| JP2000299463A (en) * | 1999-04-16 | 2000-10-24 | Ricoh Co Ltd | Manufacture of semiconductor device |
| JP2001044404A (en) * | 1999-07-28 | 2001-02-16 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2001144287A (en) * | 1999-11-15 | 2001-05-25 | Ricoh Co Ltd | Method of manufacturing semiconductor device |
-
2002
- 2002-06-25 KR KR10-2002-0035690A patent/KR100447094B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208437A (en) * | 1999-01-08 | 2000-07-28 | United Microelectronics Corp | Method for forming silicide layer |
| JP2000299463A (en) * | 1999-04-16 | 2000-10-24 | Ricoh Co Ltd | Manufacture of semiconductor device |
| JP2001044404A (en) * | 1999-07-28 | 2001-02-16 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2001144287A (en) * | 1999-11-15 | 2001-05-25 | Ricoh Co Ltd | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040000755A (en) | 2004-01-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6777275B1 (en) | Single anneal for dopant activation and silicide formation | |
| US6797602B1 (en) | Method of manufacturing a semiconductor device with supersaturated source/drain extensions and metal silicide contacts | |
| US5879975A (en) | Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile | |
| US20100330782A1 (en) | Semiconductor device and method for producing the same | |
| US7105412B1 (en) | Silicide process utilizing pre-amorphization implant and second spacer | |
| US20110309457A1 (en) | Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained | |
| JP2006024946A (en) | Manufacturing method of polycrystalline silicon and manufacturing method of semiconductor element utilizing the same | |
| KR100396692B1 (en) | Method for Manufacturing of Semiconductor device | |
| US6010952A (en) | Process for forming metal silicide contacts using amorphization of exposed silicon while minimizing device degradation | |
| US7157342B1 (en) | Thyristor-based semiconductor memory device and its method of manufacture | |
| KR100447094B1 (en) | Method for forming a silicide layer of a semiconductor device | |
| JP2764395B2 (en) | Method for manufacturing thin film transistor | |
| US6048784A (en) | Transistor having an improved salicided gate and method of construction | |
| US20050090067A1 (en) | Silicide formation for a semiconductor device | |
| US20060073656A1 (en) | Method and system for improved nickel silicide | |
| JP2000286397A (en) | Manufacture of semiconductor device | |
| US7947559B2 (en) | Method of fabricating semiconductor device | |
| US5998294A (en) | Method for forming improved electrical contacts on non-planar structures | |
| KR100291276B1 (en) | Silicide forming method of semiconductor devices | |
| US7329910B2 (en) | Semiconductor substrates and field effect transistor constructions | |
| KR100617068B1 (en) | Method for manufacturing of semiconductor device | |
| KR100289779B1 (en) | Silicide forming method of semiconductor devices | |
| US7067410B2 (en) | Method of forming a metal silicide | |
| KR100573271B1 (en) | Method for forming silicide in semiconductor device | |
| KR100587609B1 (en) | Method for manufacturing transistor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110719 Year of fee payment: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20120726 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |