JP2001144287A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a short circuit caused by a high-melting metal silicide layer in a manufacturing method of a semiconductor device, where the method includes a salicide process. SOLUTION: A silicon oxide film 21 is formed over the entire surface of a semiconductor substrate 1, then resist patterns 23a and 23b are formed (A), the silicon oxide film 21 is removed by etching, using the resist patterns 23a and 23b as a mask for the formation of a salicide block layer 21a, the surface of a diffusion region 5 is partially exposed, furthermore ions are implanted using the resist patterns 23a and 23b as a mask to form an amorphous silicon layer 5a on the part of the diffusion region 5, and a region 3a where the structure of an oxide film is in disorder is formed in a region of the field oxide film 3 (B). A titanium film 7 is formed (C), a titanium silicide layer 9a is formed in the diffusion region 5 through a thermal treatment, and a titanium silicide layer 9b is formed in the region 3a. Thereafter, the unreacted part of the titanium film 7 is selectively removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOSFET (Me
tal-Oxide-Semiconductor Field Effect Transistor)
More particularly, the present invention relates to a method for manufacturing a semiconductor device including a step called a salicide (self-aligned-silicide) process in which at least a source region and a drain region are silicided.

[0002]

2. Description of the Related Art In a conventional salicide process, first,
A silicon oxide film as a sidewall film is formed in a self-aligned manner on a sidewall portion of a gate electrode made of polysilicon,
Impurities are implanted into a region where a diffusion region is to be formed by ion implantation using the field oxide film, the gate electrode, and the sidewall film as a mask, and then heat treatment is performed to form a source region and a drain region.

Next, a refractory metal film such as a titanium film is formed on the entire surface of the semiconductor substrate, and a first heat treatment for forming a refractory metal silicide layer is performed to form a source region, a drain region and a gate electrode surface. A titanium silicide film is formed only in a self-aligned manner. Next, the unreacted titanium film on the field oxide film and the sidewall film is selectively removed by etching with a mixed solution of ammonia and hydrogen peroxide, and a second heat treatment for forming a refractory metal silicide layer is performed. Then, the resistance of the titanium silicide film on the source region, the drain region and the gate electrode is reduced to complete the salicide process.

In a semiconductor device that has undergone such a salicide process, a so-called fine wire effect occurs in which a sheet resistance value increases in a silicide film formation region having a small line width.
As one of methods for suppressing the thin line effect, a method has been proposed in which the surfaces of the gate electrode, the source region, and the drain region are made amorphous immediately before forming the refractory metal film. Usually, an ion implantation method is used for the amorphization, and silicon ions or arsenic ions are used as ion species. Before the titanium film is formed in the above-mentioned salicide process, the surfaces of the gate electrode, the source region, and the drain region can be made amorphous by implanting, for example, arsenic ions into the surfaces of the gate electrode, the source region, and the drain region. .

FIG. 1 is a process sectional view showing a conventional salicide process including an amorphization process. After a field oxide film 3 is formed on a silicon substrate 1 and a diffusion region 5 serving as a source region or a drain region is formed in an element formation region (A), ion implantation for amorphization is performed on the entire surface of the silicon substrate 1. (B). As a result, an amorphous silicon layer 5a is formed on the surface of the diffusion region 5, and a region 3a having a disordered oxide film structure due to the influence of ion implantation is formed on the surface of the field oxide film 3. Thereafter, after a titanium film 7 is formed and a normal salicide process is performed, a titanium silicide layer 9 is formed on the diffusion region 5.
a, and a titanium silicide layer 9b is similarly formed thinly on the surface of the field oxide film 3 (C).

Normally, a titanium film does not react with a silicon oxide film or a silicon nitride film. However, it is known that when a high-temperature heat treatment is applied, silicon and titanium in the silicon oxide film react with titanium to form titanium silicide, though slightly. (For example, Journal of Applied Physics, 1988 p.344-353
reference). In particular, if the surface of the field oxide film 3 is in a region 3a where the oxide film structure is disturbed by ion implantation as in the example of FIG. 1, the reaction between silicon and titanium in the field oxide film 3 becomes more active. And the titanium silicide film 9 is easily formed. As a result, a titanium silicide layer 9b is also formed on the surface of the field oxide film 3 as shown in FIG. 2C, and the titanium silicide layers 9a formed on the adjacent diffusion regions 5
A short circuit occurs via the upper titanium silicide layer 9b.

FIG. 1 shows a short circuit between diffusion regions due to a refractory metal silicide layer formed on a field oxide film, but the surface of a sidewall film formed adjacent to a sidewall of a gate electrode is also short-circuited. In some cases, a high-melting-point metal silicide layer is formed in the same manner as described above, and a short circuit may occur between the gate electrode and the diffusion region.

Further, as a method for preventing the refractory metal silicide layer from crawling on the field oxide film and the sidewall film, the following solutions have been proposed. (1) In the first method, after forming a field oxide film and a diffusion layer on a semiconductor substrate, an insulating film is formed on the entire surface of the semiconductor substrate, and as shown in FIG. 2, field oxidation is performed by photolithography and etching. The insulating protrusions 11 are left on the film 3. This insulating protrusion 11
Has a protruding shape, thereby preventing the titanium silicide layer 9b from rising from the diffusion region 5 and preventing a short circuit between the diffusion regions 5 (JP-A-7-263).
No. 536).

(2) In the second method, the titanium silicide is formed on the field oxide film while fluorine (F) in BF ₂ used for implanting the P-type impurity remains on the surface of the field oxide film. Is considered to be the cause of the formation of a titanium silicide layer, and the fluorine is removed by annealing at a low temperature of 300 to 750 ° C. before the heat treatment for activating the P-type impurities. Crawling of titanium silicide on the oxide film is avoided (see JP-A-10-340866).

[0010]

However, according to the solutions of the conventional methods 1 and 2, if ion implantation for amorphization is performed to suppress the thin line effect, the same as in the prior art shown in FIG. There is a concern that a short circuit may occur between adjacent diffusion regions.

Accordingly, an object of the present invention is to prevent a short circuit due to a high melting point metal silicide layer in a method of manufacturing a semiconductor device including a salicide process for performing amorphization.

[0012]

The present invention is a method of manufacturing a semiconductor device including a salicide process, and includes the following steps (A) to (F). (A) a step of forming an element formation region and an element isolation region in a semiconductor substrate; and (B) an impurity is ion-implanted into a region where a diffusion region is to be formed in the element formation region, and heat treatment is performed.
Forming a diffusion region to be a source region or a drain region of T; (C) having an opening on at least a part of the diffusion region and separating adjacent diffusion regions on the element isolation region; Forming a resist pattern covering at least a part of the element isolation region, performing ion implantation using the resist pattern as a mask to amorphize at least a part of the surface of the diffusion region, and (D) removing the resist pattern (E) a step of forming a high melting point metal film over the entire surface of the semiconductor substrate, (E) a step of performing a first heat treatment for forming a high melting point metal silicide layer, and then removing an unreacted high melting point metal; A) a step of performing a second heat treatment for forming the refractory metal silicide layer to lower the resistance of the refractory metal silicide layer;

When the ion implantation for amorphizing the surface of the diffusion region is performed, the field oxide film is covered with a resist pattern, thereby preventing the field oxide film from forming a region having a disordered oxide film structure. . As a result, even if ion implantation for amorphization is performed,
The formation of the refractory metal silicide layer on the field oxide film is suppressed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS ESD (Electro-Static Dischar
ge) As a countermeasure, a salicide block layer made of an insulating film may be formed on the gate electrode and the sidewall film so that the refractory metal silicide layer is not formed around the gate electrode. In this case, after forming an insulating film on the entire surface of the semiconductor substrate, a resist pattern covering the region on the gate electrode and the side wall film is formed on the insulating film, and the insulating film is removed by etching using the resist pattern as a mask. Then, a salicide block layer is formed on the gate electrode and the sidewall film.

In the case of forming a salicide block layer, the step (B) includes a step of forming a gate electrode and a sidewall film in an element forming region before forming a diffusion region.
Further including a step of forming an insulating film serving as a salicide block layer over the entire surface of the semiconductor substrate after forming the diffusion region,
The step (C) is a step in which the resist pattern also covers the gate electrode region and the side wall film region, and includes a step of forming the resist pattern on the insulating film and then removing the insulating film by etching using the resist pattern as a mask;
Further, it is preferable that the ion implantation for the amorphization is performed using the resist pattern and the insulating film as a mask.

After forming an insulating film to be a salicide block layer in the step (B), a resist pattern covering the gate electrode, the sidewall film and the field oxide film is formed in the step (C). The salicide block layer is formed by etching and removing the insulating film using the resist pattern as a mask,
Since a resist pattern and an insulating film can be present on the field oxide film, the implantation of impurities into the field oxide film during ion implantation for amorphization can be suppressed without increasing the number of steps.

Preferably, the insulating film for the salicide block layer is a silicon oxide film. As a result, the refractory metal film comes into contact with the silicon oxide film for the salicide block layer in which the impurity is not implanted in the region on the field oxide film, so that the refractory silicide layer in the region on the field oxide film is formed. Formation can be suppressed.

The insulating film for the salicide block layer is preferably a silicon nitride film. As a result, when the insulating film for the salicide block layer is removed by etching, the field oxide film existing under the insulating film can be selectively removed by etching, so that the field oxide film can be prevented from being reduced in thickness. Further, since the refractory metal film comes into contact with the silicon nitride film for the salicide block layer in which impurities are not implanted in the region on the field oxide film, the refractory silicide layer is formed in the region on the field oxide film. Can be suppressed.

[0019]

FIG. 3 is a process sectional view showing one embodiment. However, the embodiments described below do not limit the present invention, and various modifications can be made within the scope of the present invention described in the claims.

(A) A field oxide film 3 having a thickness of, for example, 4000.degree. After a process of forming a gate electrode and a sidewall film of a MOSFET (not shown), a MOSF
To form the source and drain regions of the ET,
For example, using arsenic, 50 keV, 3 × 10 ¹⁵ atoms
Ions are implanted under the condition of / cm ² . 85 in the diffusion furnace
The impurity is activated by performing a heat treatment in a nitrogen atmosphere at 0 ° C. for about 30 minutes to form the diffusion region 5 in the element formation region.

(B) A resist pattern 13 is formed on the field oxide film 3 by a photolithography process using a mask having a pattern which has an opening in the diffusion region 5 and covers a region separating the adjacent diffusion regions 5 and 5. Form. Using the resist pattern 13 as a mask, ion implantation for amorphization is performed using, for example, arsenic (As) at 40 K.
eV is performed under the conditions of 3 × 10 ¹⁴ atoms / cm ² . Thereby, the amorphous silicon layer 5 is formed on the surface of the diffusion region 5.
In addition to forming a, a region 3a in which the oxide film structure is disordered is formed in a portion of the field oxide film 3 which is not covered with the resist pattern 13.

(C) After the resist pattern 13 is removed by ashing, a titanium film 7, for example, having a thickness of 200 to 600 ° is formed as a high melting point metal film on the entire surface of the silicon substrate 1. Here, it was formed with a thickness of 400 °. (D) 600 minutes in an inert gas atmosphere by lamp annealing
A first heat treatment for forming a refractory metal silicide layer is performed at a temperature of about 800 ° C. to cause a reaction between titanium in the titanium film 7 and silicon in the amorphous silicon layer 5 a to form a titanium silicide layer 9 a on the diffusion region 5. Form. At this time, the region 3a of the field oxide film 3 is in a state where the oxide film structure is disordered by ion implantation, and silicon in the oxide film easily reacts with titanium, so that the titanium silicide layer 9b is formed although it is thin. Is done.

Thereafter, the unreacted titanium film 7 on the field oxide film 3 is selectively removed with a mixed solution of ammonia and hydrogen peroxide solution. 700-850 ° C. higher than that of the first heat treatment in an inert gas atmosphere by lamp annealing
The second heat treatment for forming the refractory metal silicide layer is performed under the above temperature conditions to lower the resistance of the titanium silicide layers 9a and 9b.

In this embodiment, the field oxide film 3 is covered with a resist pattern 13 at the time of ion implantation for amorphization, thereby forming a region of the field oxide film 3 into which impurities are not implanted. The formation of a titanium silicide layer at
A short circuit between the adjacent diffusion regions 5 and 5 can be prevented.

FIG. 4 is a process sectional view showing another embodiment. This embodiment shows an example in which the present invention is applied to a method of manufacturing a semiconductor device in which a salicide block layer is formed so that a refractory metal silicide layer is not formed around a gate electrode as a measure against ESD. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

(A) After the field oxide film 3 is formed on the surface of the silicon substrate 1, the gate oxide film 15 is formed in the element formation region.
A gate electrode 17 is formed through the gate electrode 17, and a sidewall film 1 made of, for example, a silicon oxide film is
9 is formed. Gate electrode 17 and sidewall film 1
By using the mask 9 as a mask, ion implantation is performed in the element formation region to form a diffusion region 5 serving as a source region or a drain region in a self-aligned manner.

For example, a silicon oxide film 21 as an insulating film for a salicide block
It is formed with a thickness of 00 °. A resist pattern 23a is formed on the salicide block layer formation region by a photolithography process using a mask having an opening in the salicide block layer formation region including the gate electrode 17 and the sidewall film 19 and the field oxide film 3 region. A resist pattern 23b is formed on oxide film 3.

(B) The silicon oxide film 21 is removed by, for example, anisotropic etching using the resist patterns 23a and 23b as a mask, an opening is formed in the silicon oxide film 21, and a diffusion region separated from the sidewall film 19 is formed. 5 and a salicide block layer 21a made of a silicon oxide film 21 is formed on the gate electrode 17, on the sidewall film 19, and on a region of the diffusion region 5 adjacent to the sidewall film 19. .
At this time, the silicon oxide film remaining on the field oxide film 3 is defined as 21b.

Using the resist patterns 23a and 23b, the salicide block layer 21a and the silicon oxide film 21b as a mask, ion implantation for amorphization is performed.
For example, using arsenic, 40 keV, 3 × 10 ¹⁴ atoms
/ Cm ² . As a result, an amorphous silicon layer 5a is formed on a part of the surface of the diffusion region 5, and a region 3a having a disordered oxide film structure is implanted into the region of the field oxide film 3 not covered with the silicon oxide film 21b by ion implantation. Form.

(C) After the resist patterns 23a and 23b are removed by ashing, a titanium film 7, for example, having a thickness of 400 ° is formed as a high melting point metal film on the entire surface of the silicon substrate 1. (D) 600 minutes in an inert gas atmosphere by lamp annealing
A first heat treatment for forming a refractory metal silicide layer is performed under a temperature condition of ~ 800 ° C., and a titanium silicide layer 9a is formed in the diffusion region 5 where the amorphous silicon 5a is formed.
Is formed, and a titanium silicide layer 9b is formed in the region 3a of the field oxide film 3. Thereafter, the salicide block layer 21a is mixed with a mixed solution of ammonia and hydrogen peroxide solution.
The unreacted titanium film 7 on the silicon oxide film 21b is selectively removed. A second heat treatment for forming a refractory metal silicide layer is performed by lamp annealing in an inert gas atmosphere at a temperature of 700 to 850 ° C. higher than that of the first heat treatment to reduce the resistance of the titanium silicide layers 9a and 9b. Do.

In this embodiment, the resist pattern 2 is formed on the gate electrode 17, the side wall film 19 and the field oxide film 3 at the time of ion implantation for amorphization.
3a and 23b and the silicon oxide films 21a and 21b to prevent impurities for amorphization from being implanted into a part of the gate electrode 17, the sidewall film 19 and the field oxide film 3. Since the formation of the titanium silicide layer in the region is prevented,
A short circuit between the diffusion region 5 and the gate electrode 17 and a short circuit between the adjacent diffusion regions 5 and 5 can be prevented. Further, since the silicon oxide film 21b and the resist pattern 23b are formed on the field oxide film 3 by the steps required for forming the salicide block film 21a, the silicon oxide film 21b can be formed without increasing the number of steps.
b and the resist pattern 23b can be formed.

In the embodiment shown in FIG. 4, the silicon oxide film 21 is used as the insulating film for the salicide block layer, but the present invention is not limited to this.
A silicon nitride film of about Å may be used. In this case, when an opening is formed by anisotropically etching the silicon nitride film in the step (B), a selectivity can be obtained with respect to a lower field oxide film, so that a decrease in the field oxide film can be suppressed. As an ion species used for ion implantation for amorphization, an ion having a relatively large atomic radius, such as silicon, may be used in addition to arsenic. In the step (B) of FIG. 4, anisotropic etching is used when the silicon oxide film 21 is removed by etching, but isotropic etching may be used.

[0033]

In the method of manufacturing a semiconductor device according to the first aspect, a resist pattern having an opening on at least a part of the diffusion region and covering at least a part of the element isolation region is formed. Since the surface of the diffusion region is made amorphous by performing ion implantation using the resist pattern as a mask, even if the ion implantation for amorphization is performed, the region of the field oxide film in which the oxide film structure is in a disordered state may be formed. Not being formed, the formation of the refractory metal silicide layer on the field oxide film can be suppressed. This can prevent short-circuiting between adjacent diffusion regions by the refractory metal silicide layer.

According to a second aspect of the present invention, an insulating film serving as a salicide block layer is formed on the entire surface of the semiconductor substrate, and the gate electrode, the sidewall film, and the field oxide film are covered on the insulating film. After forming the resist pattern, the insulating film is etched away using the resist pattern as a mask, and ion implantation for amorphization is performed using the resist pattern and the insulating film as a mask, so that the salicide block layer is formed. In addition, a resist pattern and an insulating film can be present on the field oxide film, and when the salicide block layer is formed, the salicide block layer is oxidized to the field oxide film at the time of ion implantation for amorphization without increasing the number of steps. It is possible to suppress the formation of a region with a disordered film structure. Kill.

According to a third aspect of the present invention, a silicon oxide film is used as an insulating film for the salicide block layer, and the refractory metal film is a region on the field oxide film in which impurities are not implanted. Since it is in contact with the silicon oxide film for use, the formation of the high melting point silicide layer in the region on the field oxide film can be suppressed.

In the method of manufacturing a semiconductor device according to the fourth aspect, a silicon nitride film is used as an insulating film for the salicide block layer, and the silicon nitride film is present below the insulating film when the insulating film for the salicide block layer is removed by etching. Since the film is selectively etched away from the field oxide film, it is possible to suppress a decrease in the film thickness of the field oxide film. Further, since the refractory metal film is brought into contact with the silicon nitride film for the salicide block layer in which impurities are not implanted in the region on the field oxide film, the refractory silicide layer in the region on the field oxide film is formed. Formation can be suppressed.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a conventional salicide process including an amorphization process.

FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device in which a short circuit between diffusion regions due to a refractory metal silicide layer is prevented.

FIG. 3 is a process sectional view showing one embodiment.

FIG. 4 is a process sectional view showing another embodiment.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 3 field oxide film 3a region in which oxide film structure is disturbed 5 diffusion region 5a amorphous silicon layer 7 titanium film 9 titanium silicide film 11 insulating protrusions 13, 23a, 23b resist pattern 15 gate oxide film 17 gate electrode 19 Sidewall film 21, 21b Silicon oxide film 21a Salicide block layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kaichi Ueno 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (72) Inventor Taro Usami 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. (Reference) 4M104 AA01 BB25 CC01 DD04 DD64 DD79 DD80 DD84 DD88 DD91 DD99 GG09 GG14 HH16 HH20 5F040 DA10 DA14 DC01 EH02 EH08 EK01 FA03 FA05 FC00 FC19 5F048 BA01 BF06 BF16 BG12 DA23 DA25

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor device including a salicide process, comprising the following steps (A) to (F). (A) a step of forming an element formation region and an element isolation region in a semiconductor substrate;
Forming a diffusion region to be a source region or a drain region of the FET; (C) having an opening on at least a part of the diffusion region, and forming a gap between the adjacent diffusion regions on the element isolation region. Forming a resist pattern covering at least a part of the element isolation region so as to divide the element, and performing ion implantation using the resist pattern as a mask to amorphize at least a part of the surface of the diffusion region; A) forming a refractory metal film over the entire surface of the semiconductor substrate after removing the resist pattern; and (E) performing a first heat treatment for forming a refractory metal silicide layer, and then unreacting the refractory metal film. (F) a step of performing a second heat treatment for forming a refractory metal silicide layer to lower the resistance of the refractory metal silicide layer; 2. The method according to claim 1, wherein the step (B) includes a step of forming a gate electrode and a sidewall film in the element formation region before the formation of the diffusion region, and the step of forming a gate electrode and a sidewall film on the semiconductor substrate after the formation of the diffusion region. A step of forming an insulating film to be a salicide block layer on the entire surface; the step (C) is such that the resist pattern covers the gate electrode region and the sidewall film region; 2. The semiconductor according to claim 1, further comprising a step of etching and removing said insulating film using said resist pattern as a mask after forming a resist pattern, and further performing ion implantation for amorphization using said resist pattern and said insulating film as a mask. Device manufacturing method. 3. The method according to claim 2, wherein the insulating film is a silicon oxide film. 4. The method according to claim 2, wherein the insulating film is a silicon nitride film.