KR100441464B1 - Method for generating an interface between IP modules - Google Patents

Abstract

The present invention relates to a method for automatically generating a synchronous interface between hardware IP (Intellectual Property) modules implemented in different communication protocols. The present invention extends a signal transition graph used in asynchronous interface technology and provides various transactions. By merging them, one finite state is generated and the finite state of the interface module can be automatically extracted by enabling the representation of the data path. In addition, the number of states is minimized by merging unnecessary states in the process of converting from a signal transition graph (STG) capable of describing parallelism to a finite state indicating sequential performance.

Description

Method for generating an interface between IP modules}

The present invention relates to a method for generating an interface between IP modules, and more particularly, to a method for generating a synchronous interface between hardware IP (IP) modules implemented with different communication protocols.

When designing a system-on-chip (SOC) system using IP (Intellectual Property) modules implemented with different communication protocols, creating an interface for communication of data and control signals between different system blocks takes a lot of time. As a process, a lot of errors are generated in this process. Interface design is an important step because it not only has a big impact on the performance of the system but also has a great influence on the success of the final design result. Without automatic synthesis of these interfaces, it is almost impossible to design a system using IP.

Recently, as interest in SOC design using IP has increased, research on interface synthesis has been actively conducted. Most research is focused on automatically synthesizing interfaces between hardware implemented by heterogeneous communication protocols. Initially, research began on the method of automatically synthesizing the interface converter between the custom chip and the system bus. An event graph was generated from timing diagrams describing the different communication protocols. After merging the event graphs into one, a study on the methodology of designing interface modules from them has been published.

The following is a protocol converter. A protocol converter is a module that associates control signals with each other so that data can be transmitted between different protocols. Converts each of the two protocols described in the Verilog language into a finite state, and automatically synthesizes the finite state group of the protocol converter from the product machine of the two finite state machines, in which case the state of the generated finite state machine The number is very large.

As a result of the research, a method of synthesizing the interface using dual operation of two modules described in a high level hardware language was presented. For the synthesis of asynchronous interface circuits, input interface specifications in the form of waveforms are converted into graphs in the form of Petri Nets, and the finite state groups of the interface modules are synthesized therefrom. However, these findings are not practical because only one communication transaction can be synthesized.

Recently, research has been published on synthesizing interface modules from the behavior of protocol converters described in the form of regular expressions. However, these studies on interface synthesis provide only a solution to a limited problem, making it difficult to apply to interface synthesis between real IP modules, and it is difficult to apply because it synthesizes very poor results compared to a manually designed circuit.

Accordingly, an object of the present invention is to provide a method for generating an interface that can solve the above problems by developing a method for automatically generating a synchronous interface between IP modules to implement an interface synthesizer applicable to an actual design. have.

The present invention for achieving the above object is the step of inputting the operation of the interface module using the timing diagram editor, reading the timing diagram information to generate a signal transition graph, and generating a finite state machine from the signal transition graph And minimizing the number of states by merging the mergeable states from the finite state machine, outputting the generated finite state machine in the form of a state transition table or a VHDL program, and using a state synthesizer and a VHDL program. It characterized in that it comprises a step of synthesizing.

The signal transition graph is composed of an event node indicating a signal change and a seat node where a token can be located, and is branched from one seat node to a plurality of event nodes.

The finite state machine searches a graph from a start node on a signal transition graph to obtain a set of possible paths, calculates a path product between the position nodes constituting each path in the path set, and obtains a path product set. Obtaining the required path product from the product set, and converting the required path product to each state on the finite state machine, and obtaining a transition between the states to convert to the finite state state.

The required path product is obtained by obtaining a dependency set for each position node, checking whether the position nodes constituting each path product are dependent on each other, and removing the path product if there is a dependency relationship. It is characterized by.

1 is a flow chart illustrating a method for creating an interface between IP modules in accordance with the present invention.

FIG. 2A is a timing diagram illustrating a signal transition graph (STG) generation process of FIG. 1. FIG.

FIG. 2B is a signal transition graph (STG) for explaining FIG. 1. FIG.

3A and 3B are signal transition graphs (STGs) for explaining a token transfer process in a seat node.

4 is a signal transition graph (STG) showing the branching of the seat node.

5A and 5B are signal transition graphs (STGs) representing transactions of read and write using branches of a seat node.

5C is a signal transition graph (STG) incorporating the signal transition graph (STG) of FIGS. 5A and 5B.

6A is a signal transition graph (STG) showing a data path.

FIG. 6B is a state diagram illustrating the data path synthesis result of FIG. 6A. FIG.

7 is a signal transition graph (STG) showing a process of calculating a set of paths.

8A is a signal transition graph (STG) showing a set of path products.

8B is a state diagram for explaining the elimination of unnecessary path products.

9A and 9B are signal transition graphs (STGs) for explaining a process of generating a finite state machine (FSM) from a set of required path products.

10A to 10C are signal transition graphs (STGs) for explaining an embodiment of state minimization.

11A is a timing diagram for explaining another embodiment of state minimization.

11B to 11D are signal transition graphs (STGs) for explaining FIG. 11A.

The present invention provides a method for generating a synchronous interface between hardware IP modules implemented with different communication protocols.

Conventional asynchronous interface synthesis method can express only control signals without considering only one continuous transaction, but the present invention merges several transactions to create a single finite state, and can represent the data path. From this, the finite state machine of the interface module is automatically extracted. In addition, the number of states is minimized by merging unnecessary states in the process of converting from a signal transition graph (STG) capable of describing parallelism to a finite state indicating sequential performance.

Next, the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a method of generating an interface between IP modules according to the present invention.

Input the operation of the interface module using the timing diagram editor and the editor saves it as a file (step 1). With this file as input, the interface synthesizer constructs a signal transition graph (STG) in the form of a Petri net (step 2) and converts it back into a finite state machine (step 3). When converting from a signal transition graph (STG) that can describe parallelism to a finite state representing sequential performance, the number of states increases exponentially. At this time, the state minimization process of merging unnecessary states is reduced. Perform (step 4). The generated finite state machine is output in the form of a state transition table or VHDL (VHSIC Hardware Description Language) (step 5). The process of each step will be described in more detail as follows.

Step 2: Create a Signal Transition Graph (STG)

The interface synthesizer reads the timing diagram information input by the designer and internally creates a signal transition graph (STG) as shown in FIG. 2. The signal transition graph (STG) is a graph representing a change of events between signal lines in parallel based on a petri net. As shown in FIG. 2B, a rectangular event node and a token ( It consists of a circle place node where a token can be placed. Between these nodes, the direction of the event is represented as a directional edge. As shown in the timing diagram of FIG. 2A, the signal transition graph STG makes a point where an event of each signal occurs and inserts a seat node before each event node. According to the dependency between signal events represented by arrows in FIG. 2A, edges are connected between corresponding nodes as shown in FIG. 2B.

In the present invention, in order to represent multiple transactions in one signal transition graph (STG), it has been extended to branch to multiple event nodes in place of the signal transition graph (STG). That is, in the original signal transition graph STG as shown in FIG. 3A, when the token p0 reaches the seat nodes p1 and p2 immediately above the event node, when the event occurs in the corresponding event node, the token as shown in FIG. 3B. Although (p1 and p2) are separated in both directions and performed in parallel along each path, when branching from a seat node to several event nodes as shown in FIG. 3A, the token is passed only to the event node in which the event occurred among the event nodes. Only along that path.

When the signal transition graphs STG representing the transactions of the read and write operations are merged as shown in FIGS. 5A and 5B using the branch of the seat node, one signal transition graph STG as shown in FIG. 5C is merged. It can be expressed as. Therefore, if one finite state group is made in this way, the size of the circuit can be reduced since the overlapped portions can be reduced rather than generating each finite state group separately.

In the conventional method, a data path circuit for storing or transferring data is set aside so that an interface synthesizer can synthesize only a control signal for controlling the data path module. This is very cumbersome for the designer. Therefore, in the present invention, the expression related to the data path can also be described in the event node as shown in FIG. 6A so that the generated VHDL code is synthesized as shown in FIG. 6B.

Step 3: Generate Finite State Machine (FSM) from Signal Transition Graph (STG)

It is more convenient to implement a signal transition graph (STG) described asynchronously and in parallel as a synchronous circuit than an asynchronous circuit. Therefore, the signal transition graph (STG) is inevitably changed into a finite state, which is a sequential expression, and synthesized into a synchronous circuit. To do this, it is assumed that the positions of the tokens of each digit node on the signal transition graph (STG) are in the overall state, and a finite state machine is created based on the overall state. However, this task is very difficult depending on the complexity of the signal transition graph (STG), and also has a disadvantage in that the number of states of the finite state group becomes very large.

In order to overcome this disadvantage, the present invention implements an algorithm for automatically generating a finite state group from the signal transition graph (STG), and also reduces the number of states of the generated finite state group.

The process of generating a finite state machine from the signal transition graph (STG) involves first finding all possible paths on the signal transition graph (STG) from the start node and creating a path set from them. Calculate the path product between the place nodes that make up the path. By removing the unnecessary path products from the calculated path products, the necessary path products that can form the state on the actual signal transition graph (STG) are obtained, and each is defined as the state of the finite state machine. In addition, the transition between each state on the finite state machine is obtained from the state change according to external events between necessary path products. Each step will be described in more detail as follows.

[1] path set calculation

One path on the signal transition graph (STG) is a set of seat nodes on a single path that return from the starting position node to each starting node on the signal transition graph (STG) and back to the starting position node. On the signal transition graph STG of FIG. 7, four paths P1, P2, P3, and P4 exist from the start node P1. Here, the path P1 = {p1, p2, p4, p6, p7, p9, p11} and the path P2 = {p1, p2, p4, p6, p8, p10}. Path Set = { P1, P2, P3, P4 }, which is a set between these paths.

[2] calculating the set of path products

The set of path products is a set whose elements are the products of the paths constituting these sets of paths. That is, the path product set = P1 x P2 x P3 x P4. That is, when the paths of the signal transition graph (STG) of FIG. 7 are obtained,

P1 = {p1, p2, p4, p6, p7, p9, p11},

P2 = {p1, p2, p4, p6, p8, p10, p11},

P3 = {p1, p3, p5, p6, p8, p10, p11}

P4 = {p1, p3, p5, p6, p7, p9, p11}.

If we get a set of path products from these sets of paths,

Path product set = {{p1}, {p1, p3}, .... {p2, p3}, {p2, p3, p5}, .... {p2, p6, p5, p7},

.... {p6}, .... {p11}}.

[3] eliminating unnecessary path products

To obtain the desired state of the signal transition graph (STG) from the path product set obtained in the step [2], the unnecessary path products that are not feasible on the signal transition graph (STG) of FIG. Remove it to get the path products you need.

The method to remove unnecessary path products from the path product set is to obtain a dependency set for each position node, and check whether the position nodes constituting each path product depend on each other. Remove the path product because it is not necessary. Here, the dependency set of each seat node is a set of all visitable seat nodes starting from the corresponding seat node on the signal transition graph (STG) until reaching the starting seat node. For example, the dependency set Dp2 of the seat node p6 = {p2, p4, p6, p7, p8, p9, p11}, and the dependency set Dp5 of the seat node p5 = {p6, p7, p8, p9, p11}. Therefore, in the case of the path product {p2, p6, p5, p7}, there is a dependency relationship p2-> p6, p5-> p7 and so is eliminated as unnecessary path product. Thus all unnecessary path products are removed and the remaining required path products are made into one state on the generated finite state machine.

[4] generating transitions between required path products

The transition of the finite state machine is generated from the relationship between the necessary path products having a one-to-one correspondence with each state of the finite state machine. The required path product set = {PE1, PE2, ..., PEi, ..., PEj, ..., PEm}, where PEi is the i-th required path product. The method for generating the transition is that for each seat node ps constituting PEi for one product PEi of the set of required path products, if the event node immediately after the seat node in the signal transition graph (STG) receives an event, When the path product converted to the position node pt to be delivered is within the required path product set, the product PEm generates a transition from the state Si corresponding to the current required path product PEi to the state Sm of the PEm.

When the "b" event occurs in the path product {p1, p2} required in the signal transition graph (STG) of FIG. 9a, the token is transferred from p1 to p3, and thus is changed to {p3, p2}. A transition is made from {p1, p2} to state {p3, p2}.

Step 4: minimize the state

When a state transition graph (STG) described in parallel is converted into a finite state that is sequentially expressed, there are inevitably many states. However, in some cases, unnecessary states are generated to increase the number of states of the finite state group and to slow down the operation speed of the synthesized circuit. Accordingly, the mergeable states are merged with each other from the generated finite state machine to minimize the overall number of states.

First, when the input D from the outside becomes 1 as shown in FIG. 10A, the signal transition graph STG outputting 1 to the output Q is generated in three states as shown in FIG. 10B when converted into a finite state. However, since the transition condition of S1-> S2 and the output of S2-> S3 can be merged, by removing the intermediate state S2 and merging each transition, it can be reduced to two states as shown in FIG. 10C.

As another example, in the case of the signal transition graph (STG) of FIG. 11B which outputs Q as 1 after the input R becomes 1 as shown in FIG. 11A and the respective inputs D1 and D2 become 1, It is a finite state group having six states as shown in FIG. 11C, which can be minimized as shown in FIG. 11D.

Step 5: State Transition Table and VHDL Code Output

The state minimized finite state machine is output to the state transition table and the finite state machine type VHDL program. If the input contains a description of the data path, the state transition table alone does not allow the interface module to be completed and outputs only as a VHDL file. The output state transition table and the VHDL file are synthesized into the interface circuit using a logic synthesizer.

As described above, the present invention provides a method for generating a synchronous interface between hardware IP modules implemented with different communication protocols.

By extending the signal transition graph (STG) used in the asynchronous interface technology, merging several transactions to create one finite state, and expressing the data path, the finite state of the interface module can be automatically extracted. In addition, the number of states is minimized by merging unnecessary states in the process of converting from a signal transition graph (STG) capable of describing parallelism to a finite state indicating sequential performance.

Interface synthesis is an important part of SOC design using IP modules. Therefore, the present invention enables the designer to directly input the operation of the interface module in the form of a timing diagram and synthesize the interface module that meets the designer's purpose.

Claims (4)

Inputting an operation of an interface module using a timing diagram editor; Reading the timing diagram information to generate a signal transition graph; Generating a finite state group from the generated signal transition graph; Merging the mergeable states from the generated finite state machine to minimize the number of states; Outputting the generated finite state group in the form of a state transition table or a VHDL program; And And synthesizing the state transition table and the VHDL program using a logic synthesizer. The method of claim 1, The signal transition graph is composed of an event node indicating a change in the signal, and a seat node where the token can be located, the method for creating an interface between the IP module, characterized in that branched from one seat node to a plurality of event nodes . The method of claim 1, The finite state machine searches for a graph from a start node on the signal transition graph to obtain a set of possible paths; Obtaining a path product set by calculating a path product between spot nodes constituting each path in the path set; Obtaining the required path products from the set of path products obtained; Converting the necessary path products into respective states on the finite state machine, and obtaining a transition between the states to convert to the finite state state. The method of claim 3, wherein The necessary path product is obtained by obtaining a dependency set for each position node, Checking whether the position nodes constituting each path product depend on each other; Method of creating an interface between IP modules, characterized in that obtained by the step of removing the product of the path if there is a dependency.