CN117634404A - Method, system, equipment and medium for realizing state machine circuit based on petri net - Google Patents
Method, system, equipment and medium for realizing state machine circuit based on petri net Download PDFInfo
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Abstract
The invention relates to the field of state machines, and provides a method, a system, equipment and a medium for realizing a state machine circuit based on a petri net, wherein the method comprises the following steps: in response to receiving the functional requirement, acquiring a circuit element with library and transition functions, combining the circuit element into a neural node, combining to obtain a network structure, and further combining to obtain a state machine structure meeting the functional requirement; modularization is carried out on the neural nodes in the state machine structure, the modules are connected, and input triggering conditions of the modules are set; in response to the presence of a high fanout first control signal, a neural node in the state machine structure that generated the first control signal is cloned. According to the characteristics of serial in branches and parallel among branches of the state machine, the invention can realize a transmission stage circuit which is closer to a register, improves the reliability and performance of circuit design, reduces single-node load by copying neuron nodes, further optimizes circuit time sequence, and improves the fault tolerance, maintainability and portability of the design.
Description
Technical Field
The present invention relates to the field of state machines, and in particular, to a method, a system, an apparatus, and a medium for implementing a petri net-based state machine circuit.
Background
Finite state machines (Finite State Machine), abbreviated FSMs, have been widely used in digital logic systems to represent mathematical models of finite states and transitions and actions between these states. State jumps in FSM finite state machines are described using Verilog HDL language in chip design, a circuit that transitions between finite states according to a certain rule, which can be considered a combination of combinational logic and sequential logic.
The combination logic in the existing control circuit (state machine) structure cannot be accurately described by a hardware description language (Verilog HDL), and the circuit structure is mostly dependent on the optimization of a comprehensive tool; when the control signals generated by the state machine drive more circuits, the signal path delay is larger, and the circuit performance may be affected; for complex state machines, write-missing or write-miss state transitions are easy; in addition, for the design of the iterative version, the change of the design requirement or the technical specification often causes the change of the function of the original circuit design, and further causes the change of the function of the control state machine, so that the state machine needs to be redesigned; in addition, the code is filled with a large number of case sentences, the readability and maintainability are poor for designs with more branch conditions, the modification or optimization is easy to make mistakes, and the state machine circuit is a control flow design special for the module and does not have the reusability and portability of the module.
Disclosure of Invention
In view of the above, the invention provides a method, a system, a device and a medium for realizing a state machine circuit based on petri net, which realize the optimization of the circuit structure of the state machine, reduce the load of control signals, facilitate the adjustment layout of the state machine according to the actual requirements and improve the maintainability.
Based on the above objective, an aspect of the embodiments of the present invention provides a method, a system, a device and a medium for implementing a state machine circuit based on petri net, which specifically include the following steps:
the invention provides a method for realizing a state machine circuit based on a petri net, which comprises the following steps:
in response to receiving a functional demand, obtaining a circuit element having library and transition functions, combining the circuit elements into a neural node, the neural node comprising a serial branch and a concurrent branch;
combining the serial branch and the concurrent branch to obtain a network structure, wherein the network structure comprises a serial structure, a concurrent structure and a conflict structure;
obtaining a state machine structure meeting the functional requirements according to the combination of the serial structure, the concurrent structure and the conflict structure;
modularization is carried out on the neural nodes in the state machine structure, the modules are connected, and input triggering conditions of the modules are set;
in response to the presence of the high fanout first control signal, cloning the neural nodes in the state machine structure that generated the first control signal to obtain a plurality of identical neural nodes and respectively generate the first control signal based thereon, and commonly driving the output bus.
In some embodiments, the serial branch is defined as pulling the token signal high one clock cycle in response to the get signal being active and the place signal being inactive;
the expression of the serial branch is as follows:
A＝get1′b1：(put1′b0：place)；
B＝((！place)&&(！token)&&get)？1′b1：1′b0；
wherein put is an input condition signal capable of promoting state change, place is an output library signal, token is an output transition signal, get is a token signal for receiving the last neural node, 1'b1 is high level, and 1' b0 is low level.
In some embodiments, the concurrent branch is defined as pulling the token signal one clock cycle high in response to the put signal being active and the place signal falling edge;
the expression of the concurrent branches is as follows:
X＝get1′b1：(put1′b0：place)；
Y＝(place&&(！token)&&get)？′b1：1′b0。
in some embodiments, the expression of the serial structure is as follows:
wherein q x0 Is the zeroth node, q x1 For the first node, q x4 Is a fourth node;
q x0token is q x0 Transition signal, q x0place Is q x0 Library signals, q x1token Is q x1 Transition signal, q x1place Is q x1 A library signal;
get 0 to receive an input token signal, put 0 Is q x0 Get of the input signal of (2) 1 To receive q x0 Is a token signal, put 1 Is q x1 Is a signal input to the processor;
wherein the place responsive to the link is inLow level, q x0 Token signal trigger q x1 。
In some embodiments, the expression of the concurrency structure is:
wherein q a2 Second node of branch A, q b0 Zero node of branch B, q c0 Zero node of branch C;
q a2token is q a2 Transition signal, q a2place Is q a2 Library signals, q b0token Is q b0 Transition signal, q b0place Is q b0 Library signals, q c0token Is q c0 Transition signal, q c0place Is q c0 A library signal;
get a2 to receive an input token signal, put a2 Is q a2 Get of the input signal of (2) b0 To receive q b0 Is a token signal, put b0 Is q b0 Input of (a)Signal get c0 To receive q c0 Is a token signal, put c0 Is q c0 Is provided.
In some embodiments, the concurrent structure works as follows:
q in response to branch B, C being in an idle state and branch AB and branch AC being synchronized within the same clock domain a2 Directly and respectively trigger q b0 、q c0 ；
In response to branch B, C being in an idle state and neither branch AB nor branch AC being synchronized within the same clock domain, q a2 At q b0 And q c0 And respectively synchronizing the two clock domains to obtain an AB branch in the same clock domain and an AC branch in the same clock domain, and triggering other nodes of the B branch and the C branch.
In some embodiments, the expression of the conflict structure is as follows:
wherein q d2 For DSecond node of branch, q e2 Second node of E branch, q f0 Zero node of branch F;
q d2token is q d2 Transition signal, q d2place Is q d2 Library signals, q e2token Is q e2 Transition signal, q e2place Is q e2 Library signals, q f0token Is q f0 Transition signal, q f0place Is q f0 A library signal;
get d2 to receive an input token signal, put d2 Is q d2 Get of the input signal of (2) e2 To receive q e2 Is a token signal, put e2 Is q e2 Get of the input signal of (2) f0 To receive q f0 Is a token signal, put f0 Is q f0 Is a signal input to the processor;
wherein, in response to q d2 、q e2 Q when the Place signal of (1) is active and the DE branches are synchronized in the same clock domain d2 、q e2 Trigger q f0 ；
In response to DE branches not synchronizing in the same clock domain, q d2 At q f0 Mid-synchronization, q e2 At q f0 In synchronization, a DF branch synchronized in the same clock domain and an EF branch synchronized in the same clock domain are obtained, when q d2 、q e2 When the place signal of (2) is active, trigger q f0 。
The invention provides a realization system of a state machine circuit based on petri net, comprising:
a first unit configured to obtain circuit elements having library and transition functions in response to receiving a functional requirement, the circuit elements being combined into a neural node, the neural node comprising a serial branch and a concurrent branch;
a second unit configured to combine the serial branch and the concurrent branch to obtain a network structure, where the network structure includes a serial structure, a concurrent structure, and a collision structure;
a third unit configured to obtain a state machine structure satisfying the functional requirement according to a combination of the serial structure, the concurrent structure, and the conflict structure;
a fourth unit configured to modularize the neural nodes in the state machine structure, connect the modules, and set an input trigger condition of the module;
and a fifth unit configured to clone the neural nodes generating the first control signals in the state machine structure in response to the first control signals with high fanout, to obtain a plurality of identical neural nodes, and to generate the first control signals based on the same, respectively, so as to commonly drive the output bus.
The invention proposes a computer device comprising:
at least one processor; and a memory storing a computer program executable on the processor, the processor executing steps of the method of implementing the petri net based state machine circuit when the program is executed.
The invention proposes a computer readable storage medium storing a computer program which, when executed by a processor, performs the steps of the method of implementing a petri net based state machine circuit.
The invention has at least the following beneficial technical effects:
the invention provides a method, a system, equipment and a medium for realizing a state machine circuit based on a petri network, wherein the method comprises the following steps: in response to receiving the functional requirements, obtaining circuit elements with library and transition functions, combining the circuit elements into neural nodes, combining to obtain a network structure, and further combining to obtain a state machine structure meeting the functional requirements; modularization is carried out on the neural nodes in the state machine structure, the modules are connected, and input triggering conditions of the modules are set; in response to the presence of a high fanout first control signal, a neural node in the state machine structure that generated the first control signal is cloned. According to the characteristics of serial in branches and parallel among branches of the state machine, the invention can realize a circuit closer to a register transmission stage, improves the reliability and performance of circuit design, reduces single-node load by copying neuron nodes, further optimizes circuit time sequence, processes abnormal conditions and improves the fault tolerance, maintainability and portability of the design.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for implementing a petri net-based state machine circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of an implementation system of a petri net-based state machine circuit according to an embodiment of the present invention;
FIG. 3 is a basic petri network architecture diagram of a method for implementing a petri network-based state machine circuit according to an embodiment of the present invention;
FIG. 4 is a prior art state machine digital circuit schematic diagram of a method of implementing a petri net based state machine circuit;
FIG. 5 is a schematic diagram of a state machine based on petri net theory for a method for implementing a petri net-based state machine circuit according to an embodiment of the present invention;
FIG. 6 is a prior art state machine jump timing diagram of a method of implementing a petri net based state machine circuit;
FIG. 7 is a schematic diagram of a first type of neuron circuit according to an embodiment of the present invention for implementing a petri net based state machine circuit;
FIG. 8 is a first type of neuron timing diagram of a method for implementing a petri net based state machine circuit according to one embodiment of the present invention;
FIG. 9 is a circuit diagram of a second type of neurons implementing a state machine circuit based on petri nets according to an embodiment of the present invention;
FIG. 10 is a timing diagram of a second type of neurons implementing a state machine circuit based on a petri net according to an embodiment of the present invention;
FIG. 11 is a serial block diagram of a petri net circuit for implementing a petri net-based state machine circuit according to an embodiment of the present invention;
FIG. 12 is a concurrent block diagram of a petri net circuit for implementing a petri net-based state machine circuit according to an embodiment of the present invention;
FIG. 13 is a conflict structure diagram of a petri net circuit according to an embodiment of the present invention;
FIG. 14 is a prior art application example diagram of a state machine circuit implementation method based on petri nets;
FIG. 15 is a diagram of an embodiment of a petri net based state machine application of a method for implementing a petri net based state machine circuit according to an embodiment of the present invention;
FIG. 16 is a schematic diagram illustrating a computer device according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of an embodiment of a computer readable storage medium according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
The invention provides a method for realizing a state machine circuit based on a petri net, referring to fig. 1, 3, 5 and 15, the method comprises the following steps:
s1: in response to receiving a functional demand, obtaining a circuit element with library and transition functions, combining the circuit element into a neural node, the neural node comprising a serial branch and a concurrent branch;
s2: combining the serial branch and the concurrent branch to obtain a network structure, wherein the network structure comprises a serial structure, a concurrent structure and a conflict structure;
s3: obtaining a state machine structure meeting the functional requirements according to the combination of the serial structure, the concurrent structure and the conflict structure;
s4: modularization is carried out on the neural nodes in the state machine structure, the modules are connected, and input triggering conditions of the modules are set;
s5: in response to the presence of the high fanout first control signal, cloning the neural nodes in the state machine structure that generated the first control signal to obtain a plurality of identical neural nodes and respectively generate the first control signal based thereon, and commonly driving the output bus.
The finite state machine can be considered as a combination of combinational logic and sequential logic, a state register in the state machine is composed of a group of triggers and is used for memorizing the current state of the state machine, the state change can only occur on the jump edge of a clock, the state change form depends on the output of the combinational logic of the next state, the state change is triggered by positive jump or negative jump, and depending on the type of the triggers, the circuit design is usually triggered by a D trigger triggered by the positive jump edge; depending on whether the output signal depends on the input, state machines fall into two categories:
mole (Moore) state machine: the output of the combinational logic depends only on the current state; i.e. the output signal-current state (G).
Miller (Mealy) state machine: the output of the combinational logic depends not only on the current state but also on the input signal; i.e. output signal-current state, input signal (G).
The Petri net is a graphical modeling tool for a system, has a solid mathematical foundation, has strong asynchronous and concurrent description capability, and is very suitable for the design of a parallel state machine. Petri networks use six tuples Σ= (S, T, F, K, W, M) 0 ) Description is made, called P/T system, where n= (S, T, F) is a directed network, abbreviated as network, satisfying:
SUT≠；
S∩T＝；
(. Times.is Cartesian product)
dom (F) cod (F) =s ∈t; wherein dom (F) = { x|y: (x, y) ∈f }, cod (F) = { y|x: (x, y) ∈F } is the F's domain and value range, respectively.
Wherein, K, W, M are the capacity function, weight function, label of N in proper order, K: S→IN { ω }, W: F→IN, M: S→IN0, IN 0= {0,1,2, … }, IN= {1,2, … }, M 0 Is an initial flag.
For a Petri network, if it transitions T j And condition C j And event E j Association, library S i And operation O i And delay D i The association, which may be that the transition is associated with a delay, is called a basic Petri net.
The petri net shown in the following figure 3 contains three types of elements, namely a library, a transition and a connection arc, and a passive entity: such as a state or resource, a naming convention, represented as a circle or oval; active entity: for example, action or function naming transitions, represented as rectangles or bars, where a library can only connect to transitions, where a transition can only connect to a library, where a resource within the library is named as a Token: s is S 1 、S 2 、S 3 、S 4 Representation warehouse, T 1 、T 2 、T 3 、T 4 Representing a tokay.
The left half of the diagram in fig. 4 shows a state machine digital circuit schematic of the prior art. The state machine may be defined by a finite number of state sets Q, q= { Q 1 ，q 2 ，q 3 ，q 4 A set of finite input signals Σ Σ= { a1, a2, a3, a4}, state transitionRepresenting the next state when the condition a is entered in the current state q, e.g.Start state q1, reset signal active time stateReturning the state machine to q 1 A state; the state machine circuit in the upper left picture uses a group of register outputs to combine into bus signal to describe current state, according to different coding modes, calculates the required register quantity of state machine, in which f_cur is represented current state, and the value in collection Q is represented as { Q } 1 ，Q 2 ，...，Q n }，Q 1 ，Q 2 ，...，Q n All are register output signals, the combinational logic outputs a next state signal f_nxt, and the next state is calculated according to the state transition theta, namely, the current state value and the input condition, and the current state f_cur value is updated in the next clock beat.
A state machine jump timing diagram of the prior art is depicted in fig. 6.
As shown in fig. 5, the right half is a basic circuit element with library and transition functions implemented according to the design scheme of the present invention, and these elements are combined to form a complete state machine control circuit. The basic element is simplified, the functions of the library and the transition are fused in a basic single neuron circuit, and two control signals of a state machine corresponding to the library and the transition are defined as follows:
each neuron contains four elements: put, get, token, place;
the element put inputs the condition signal causing the state change, denoted by put_x, as can be expressed as put_a in the above-described neuron 1 1 All neuron put elements make up the signal set Σx, Σx= { put_a 1 ，put_a 2 ，put_a 3 ，put_a 4 The set Σx corresponds to the set Σ described above;
the element planes are used for outputting library signals, and each library represents the state of the current state machine, which is represented by plane_x, such as plane_q in neuron 1 1 Then the finite set of states is Q x Q is then x ＝{place_q 1 ，place_q 2 ，place_q 3 ，place_q 4 Set Q x Corresponds to the set Q described above;
element token outputs transition signals, each transition triggering the next neuron library, e.g. nerveT in element 1 1 Corresponding to f_cur=q in fig. 2 1 &f_nxt＝q 2 A signal;
the element get is used to receive the token signal of the last neuron.
As shown in fig. 14, the control signal fsm_q generated by the state machine in the prior art x From the figure, it can be seen that fsm_q x The drive output bus forms a high fan-out network, which is too capacitive due to the high load, and also delays, which may form a critical path in the design.
As shown in FIG. 15, a neural network controller is shown, the load is shared by cloning nodes, the relevant control signals are used for driving the buses to perform de-duplication, fan-out is reduced, and the time sequence is optimized, and as can be seen from FIG. 15, the load is shared by cloning 3 parts of square nodes q x1 The three clone nodes respectively drive two groups of output buses, load is evenly spread, and the problem of high fan-out of a single signal is solved. The petri network controller based on the RTL description has the advantages that the fanout of signals can be reduced by copying a plurality of nodes, register logic output is adopted between the nodes, time sequence is easy to converge, in the design, through modularization of each neuron node and completion of interconnection among modules in the RTL description, the problem that the logic comprehensive result of a state machine is out of control can be solved, and the petri network controller can reduce the workload of functional modification or redesign of the state machine caused by chip version iteration by cloning other parts of related node signal driving circuits.
The invention combines the library and the transition into the neural node, and the node is linked through the input trigger signal to form the complex control network. Defining two types of nerve nodes, wherein one type is a serial branch formed by the nodes, the other type is a synchronous concurrent branch, three network structures are formed by combination, and then three basic network structures are combined again to form any complex state machine structure, so that a circuit which is closer to a register transmission stage circuit can be realized and can be described more accurately according to the characteristics of serial in the state machine branch and parallel among the branches; by using the method, the reliability and performance of the circuit design can be improved, the single-node load can be reduced by copying the neuron nodes, the circuit time sequence is further optimized, the controller based on the petri net can also process abnormal conditions, and the fault tolerance, maintainability and portability of the design are improved.
In some embodiments, referring to FIGS. 7 and 8, the serial branch is defined as pulling the token signal high one clock cycle in response to the get signal being active and the place signal being inactive;
the expression of the serial branch is as follows:
A＝get1′b1：(put1′b0：place)；
B＝((！place)&&(！token)&&get)？1′b1：1′b0；
wherein put is an input condition signal capable of promoting state change, place is an output library signal, token is an output transition signal, get is a token signal for receiving the last neural node, 1'b1 is high level, and 1' b0 is low level.
As can be seen from the circuit of FIG. 7 and the timing diagram of FIG. 8, the signal get is used to trigger the signal place output signal to be active and to maintain the active state, the condition for the release of the place signal is the time for generating and maintaining one clock cycle when the put signal is active and the place signal is inactive.
The serial branch is used as a basic unit format, so that the design and implementation are simpler, the transmission is more stable, and the reliability is high.
In some embodiments, referring to FIGS. 9 and 10, the concurrent branch is defined as pulling the token signal high by one clock cycle in response to the put signal being active and the place signal falling edge;
the expression of the concurrent branches is as follows:
X＝get1′b1：(put1′b0：place)；
Y＝(place&&(！token)&&get)？′b1：1′b0。
as can be seen from the circuit of FIG. 9 and the timing diagram of FIG. 10, the signal get is used to trigger the signal place to output the signal valid and keep the high-valid state, the condition of the place signal release is the next beat when the put signal is valid, and the place signal release is performed at the placeThe next beat of e signal release, and put signal is active high, produces t for one cycle o k e n signals, which is different from the first type of neuron circuits.
The concurrent branch is taken as one of basic units, so that a plurality of inputs are simultaneously executed, and the running efficiency can be greatly improved. The development and maintenance cost of the complex state machine can be reduced, better performance can be provided, and writing and maintenance are easier.
In some embodiments, referring to fig. 5 and 11, the expression of the serial structure is as follows:
wherein q x0 Is the zeroth node, q x1 For the first node, q x4 Is a fourth node;
q x0token is q x0 Transition signal, q x0place Is q x0 Library signals, q x1token Is q x1 Transition signal, q x1place Is q x1 A library signal;
get 0 to receive an input token signal, put 0 Is q x0 Get of the input signal of (2) 1 To receive q x0 Is a token signal, put 1 Is q x1 Is a signal input to the processor;
wherein q is in response to the position of the link being low x0 Token signal trigger q x1 。
As shown in FIG. 11, the petri net controller of this architecture implements the functions of the state machine of FIG. 5, where q x1 The node is formed by a reset signal and q x4 Ending the state pulse signal triggering, wherein the round node is a serial branch, the plane signal of the round node is high level to indicate that the link is in a working state, and is low to indicate that the link is in an idle state.
Round node q x0 The token signal of (1) is from start t0 Signal trigger, start t0 When the signal releases the reset signal, a token signal is sent to excite the next square node q x1 Square node q in formula (3) x1 From q x0 Transition signal q x0_token Excitation, generating a transition signal at the end signal put=x1 triggers the next node q x2 。
Same reason q x2 、q x3 、q x4 And q x1 The expressions are substantially identical.
The serial structure triggers neural nodes in proper order, and when the interference appears, the network structure is easily controlled to improve transmission rate, simultaneously because the design is simple, when the design demand or technical specification change in the face, the convenience changes the circuit, improves work efficiency.
In some embodiments, referring to fig. 12, the expression of the concurrency structure is:
wherein q a2 Second node of branch A, q b0 Zero node of branch B, q c0 Zero node of branch C;
q a2token is q a2 Transition signal, q a2place Is q a2 Library signals, q b0token Is q b0 Transition signal, q b0place Is q b0 Library signals, q c0token Is q c0 Transition signal, q c0place Is q c0 A library signal;
get a2 to receive an input token signal, put a2 Is q a2 Get of the input signal of (2) b0 To receive q b0 Is a token signal, put b0 Is q b0 Get of the input signal of (2) c0 To receive q c0 Is a token signal, put c0 Is q c0 Is provided.
q a2 Triggering two round nodes q b0 、q c0 Put in formula (5) a2 The effect of the signal to synchronize the state of the downstream node, q b0 、q c0 The expression of (2) is as shown in the formulas (7) - (10).
As shown in fig. 12, a concurrent structure is shown in the dashed box, and the concurrent structure is a structure in which a plurality of serial structures are connected together and has A, B, C branches, wherein a square node q in the branch a a2 Can trigger branch B, C and branch round node q at the same time b0 、q c0 Status information of the branches is recorded.
In the face of multiple branches, the speed of executing tasks can be increased through synchronous direct triggering or asynchronous triggering, the time of resource scheduling is effectively reduced, meanwhile, the readability and maintainability can be improved through asynchronous triggering, and errors in modification or optimization can be avoided when the adjustment is carried out according to actual working conditions.
In some embodiments, referring to fig. 12, the concurrent structure works as follows:
q in response to branch B, C being in an idle state and branch AB and branch AC being synchronized within the same clock domain a2 Directly and respectively trigger q b0 、q c0 ；
In response to branch B, C being in an idle state and neither branch AB nor branch AC being synchronized within the same clock domain, q a2 At q b0 And q c0 And respectively synchronizing the two clock domains to obtain an AB branch in the same clock domain and an AC branch in the same clock domain, and triggering other nodes of the B branch and the C branch.
As shown in FIG. 12, like the serial structure, the square node q of branch A is triggered when branch B, C is in an idle state a2 Is valid. Under this concurrent structure, branches A and B, C may be asynchronous or synchronous with each other, and if branches A and B, A and C are synchronous, then the token signal may trigger branch B, C directly, otherwise the token signal would be at the round node q of branches B, C b0 、q c0 And the subsequent state of the branch can be continuously triggered only by making one time of synchronization.
Through concurrency control, the integrity of signal transmission can be protected, the problem of repeated reading is avoided, a plurality of signal requests are processed simultaneously, service splitting is convenient, and circuit performance and anti-interference capability are improved.
In some embodiments, referring to fig. 13, the expression of the conflict structure is as follows:
wherein q d2 Second node of branch D, q e2 Second node of E branch, q f0 Zero node of branch F;
q d2token is q d2 Transition signal, q d2place Is q d2 Library signals, q e2token Is q e2 Transition signal, q e2place Is q e2 Library signals, q f0token Is q f0 Transition signal, q f0place Is q f0 A library signal;
get d2 to receive an input token signal, put d2 Is q d2 Get of the input signal of (2) e2 To receive q e2 Is a token signal, put e2 Is q e2 Get of the input signal of (2) f0 To receive qf0 token signal, put f0 Is q f0 Is a signal input to the processor;
wherein, in response to q d2 、q e2 Q when the Place signal of (1) is active and the DE branches are synchronized in the same clock domain d2 、q e2 Trigger q f0 ；
In response to DE branches not synchronizing in the same clock domainWhen q is as follows d2 At q f0 Mid-synchronization, q e2 At q f0 In synchronization, a DF branch synchronized in the same clock domain and an EF branch synchronized in the same clock domain are obtained, when q d2 、q e2 When the place signal of (2) is active, trigger q f0 。
As shown in fig. 13, which illustrates a collision structure, a scenario in which branches D, E converge to branch F, this type of petri net circuit has two modes as well: synchronous concurrency of branch D, E, asynchronous concurrency of branch D, E;
synchronous concurrency of branches D, E is similar to the concurrency structure, square node q d2 、q e2 When the plane signal of (1) is active, it indicates that both nodes are in active state, and the round node q of branch F can be triggered at this time f0 If asynchronous concurrency, then the square node q in each branch needs to be synchronized after the branches D, E are synchronized d2 、q e2 The circle node q of branch F is triggered only when the place signal of (1) is active f0 。
As shown in the above formula, node q d2 、q e2 Is two conflicting nodes, expressed as follows, node q in equation (11) d2 Is equal to the round node q for the library f0 Ending after excitation, node q of formula (13) e2 Wait in the same way, so q f0 Can realize the synchronization of two nodes q d2 、q e2 . Center-circle node q in (15) f0 The trigger condition of (a) is node q in branch D, E d2 、q e2 Simultaneously and effectively
If branch D and branch E trigger q f0 The conflict is generated, the triggering priority of the branch D and the branch E can be judged according to the actual working condition, and the q is triggered according to the priority in sequence f0 . When conflict concurrency occurs, branches are judged through priority, and control signals meeting requirements are selected to be released, so that abnormal conditions cannot occur in the task proceeding process, follow-up concurrency activities cannot be affected by selection, and stability of a circuit is improved.
The invention provides a realization system of a state machine circuit based on petri net, referring to fig. 1, comprising:
a first unit 100 configured to obtain, in response to receiving a functional requirement, a circuit element having a library and a transition function, the circuit element being combined into a neural node, the neural node comprising a serial branch and a concurrent branch;
a second unit 200 configured to combine the serial branch and the concurrent branch to obtain a network structure, where the network structure includes a serial structure, a concurrent structure, and a collision structure;
a third unit 300 configured to obtain a state machine structure satisfying the functional requirement according to a combination of the serial structure, the concurrent structure, and the conflict structure;
a fourth unit 400 configured to modularize the neural nodes in the state machine structure, connect the modules, and set an input trigger condition of the module;
the fifth unit 500 is configured to clone the neural nodes generating the first control signal in the state machine structure in response to the presence of the first control signal with high fanout, to obtain a plurality of identical neural nodes and generate the first control signal based on the same, respectively, and to commonly drive the output bus.
The invention provides a method, a system, equipment and a medium for realizing a state machine circuit based on a petri network, which realize the optimization of the circuit structure of the state machine, reduce the load of control signals, facilitate the adjustment layout of the state machine according to actual requirements and improve maintainability.
According to another aspect of the present invention, as shown in fig. 16, according to the same inventive concept, an embodiment of the present invention further provides a computer device 30, in which the computer device 30 includes a processor 310 and a memory 320, the memory 320 storing a computer program 321 executable on the processor, and the processor 310 executing the steps of the method as above.
According to another aspect of the present invention, as shown in fig. 17, there is also provided a computer-readable storage medium 40, the computer-readable storage medium 40 storing a computer program 410 which, when executed by a processor, performs the above method.
Embodiments of the invention may also include corresponding computer devices. The computer device includes a memory, at least one processor, and a computer program stored on the memory and executable on the processor, the processor executing any one of the methods described above when the program is executed.
The memory is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions/modules in the embodiments of the present application. The processor performs the various functional applications of the device and data processing, i.e., implements the methods described above, by running non-volatile software programs, instructions, and modules stored in memory.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the device, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In an embodiment, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the local module through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program may include the procedures of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (10)
1. The method for realizing the state machine circuit based on the petri net is characterized by comprising the following steps of:
in response to receiving a functional demand, obtaining a circuit element with library and transition functions, combining the circuit elements into a neural node, the neural node comprising a serial branch and a concurrent branch;
combining the serial branch and the concurrent branch to obtain a network structure, wherein the network structure comprises a serial structure, a concurrent structure and a conflict structure;
obtaining a state machine structure meeting the functional requirements according to the combination of the serial structure, the concurrent structure and the conflict structure; modularization is carried out on the neural nodes in the state machine structure, the modules are connected, and input triggering conditions of the modules are set;
in response to the presence of the high fanout first control signal, cloning the neural nodes in the state machine structure that generated the first control signal to obtain a plurality of identical neural nodes and respectively generate the first control signal based thereon, and commonly driving the output bus.
2. The method of claim 1, wherein the serial branch is defined as pulling the token signal high by one clock cycle in response to the get signal being active and the place signal being inactive;
the expression of the serial branch is as follows:
A＝get1′b1:(put1 ′ b0:place)；
B＝((！place)&&(！token)&&get)？1′b1∶1′b0；
wherein put is an input condition signal capable of promoting state change, place is an output library signal, token is an output transition signal, get is a token signal for receiving the last neural node, 1'b1 is high level, and 1' b0 is low level.
3. The method of claim 2, wherein the concurrent branch is defined as pulling up a token signal one clock cycle in response to a put signal being active and a place signal falling edge;
the expression of the concurrent branches is as follows:
X＝get1′b1：(put1′b0：place)；
Y＝(place&&(！token)&&get)？′b1：1′b0。
4. the method of claim 1, wherein the expression of the serial structure is as follows:
wherein q x0 Is the zeroth node, q x1 For the first node, q x4 Is a fourth node;
q x0token is q x0 Transition signal, q x0place Is q x0 Library signals, q x1token Is q x1 Transition signal, q x1place Is q x1 A library signal;
get 0 to receive an input token signal, put 0 Is q x0 Get of the input signal of (2) 1 To receive q x0 Is a token signal, put 1 Is q x1 Is a signal input to the processor;
wherein q is in response to the position of the link being low x0 Token signal trigger q x1 。
5. The method for implementing a petri net based state machine circuit according to claim 1, wherein the expression of the concurrency structure is:
wherein q a2 Second node of branch A, q b0 Zero node of branch B, q c0 Zero node of branch C;
q a2token is q a2 Transition signal, q a2place Is q a2 Library signals, q b0token Is q b0 Transition ofSignal, q b0place Is q b0 Library signals, q c0token Is q c0 Transition signal, q c0place Is q c0 A library signal;
get a2 to receive an input token signal, put a2 Is q a2 Get of the input signal of (2) b0 To receive q b0 Is a token signal, put b0 Is q b0 Get of the input signal of (2) c0 To receive q c0 Is a token signal, put c0 Is q c0 Is provided.
6. The method for implementing a petri net based state machine circuit according to claim 5, wherein the concurrent structure works as follows:
q in response to branch B, C being in an idle state and branch AB and branch AC being synchronized within the same clock domain a2 Directly and respectively trigger q b0 、q c0 ；
In response to branch B, C being in an idle state and neither branch AB nor branch AC being synchronized within the same clock domain, q a2 At q b0 And q c0 And respectively synchronizing the two clock domains to obtain an AB branch in the same clock domain and an AC branch in the same clock domain, and triggering other nodes of the B branch and the C branch.
7. The method of claim 1, wherein the expression of the conflict structure is as follows:
wherein q d2 Second node of branch D, q e2 Second node of E branch, q f0 Zero node of branch F;
q d2token is q d2 Transition signal, q d2place Is q d2 Library signals, q e2token Is q e2 Transition signal, q e2place Is q e2 Library signals, q f0token Is q f0 Transition signal, q f0place Is q f0 A library signal;
get d2 to receive an input token signal, put d2 Is q d2 Get of the input signal of (2) e2 To receive q e2 Is a token signal, put e2 Is q e2 Get of the input signal of (2) f0 To receive q f0 Is a token signal, put f0 Is q f0 Is a signal input to the processor;
wherein, in response to q d2 、q e2 Q when the Place signal of (1) is active and the DE branches are synchronized in the same clock domain d2 、q e2 Trigger q f0 ；
In response to DE branches not synchronizing in the same clock domain, q d2 At q f0 Mid-synchronization, q e2 At q f0 In synchronization, a DF branch synchronized in the same clock domain and an EF branch synchronized in the same clock domain are obtained, when q d2 、q e2 When the play signal of (c) is active,trigger q f0 。
8. A system for implementing a petri net based state machine circuit, comprising:
a first unit configured to obtain circuit elements having library and transition functions in response to receiving a functional requirement, the circuit elements being combined into a neural node, the neural node comprising a serial branch and a concurrent branch;
a second unit configured to combine the serial branch and the concurrent branch to obtain a network structure, where the network structure includes a serial structure, a concurrent structure, and a collision structure;
a third unit configured to obtain a state machine structure satisfying the functional requirement according to a combination of the serial structure, the concurrent structure, and the conflict structure;
a fourth unit configured to modularize the neural nodes in the state machine structure, connect the modules, and set an input trigger condition of the module;
and a fifth unit configured to clone the neural nodes generating the first control signals in the state machine structure in response to the first control signals with high fanout, to obtain a plurality of identical neural nodes, and to generate the first control signals based on the same, respectively, so as to commonly drive the output bus.
9. A computer device, comprising:
at least one processor; and a memory storing a computer program executable on the processor, characterized in that the processor executes the steps of the method for implementing a petri net based state machine circuit according to any of claims 1 to 7.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method of implementing a petri net based state machine circuit according to any of claims 1 to 7.
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