KR100441436B1 - Flat Panel Display with Improved Transmittance and Method for Fabricating the Same - Google Patents

Abstract

The present invention relates to a CMOS thin film transistor organic light emitting display device and a method for manufacturing the same, which simplifies the process by using a halftone mask, improves the transmission efficiency by prioritizing the transparent electrode forming process, and prevents damage to the source / drain electrodes. It is about.

A method of manufacturing an organic light emitting display device according to the present invention includes forming a semiconductor layer on an insulating substrate; Forming a gate insulating film on the entire surface of the substrate; Forming a gate electrode on a portion of the gate insulating film corresponding to the semiconductor layer; Forming a source / drain doped region in the semiconductor layer using a gate as a mask; Forming a pixel electrode using a halftone mask; Forming an interlayer insulating film on the entire surface of the substrate; Etching the interlayer insulating film to form a contact hole exposing the source / drain doped region and exposing the pixel electrode; Forming a source / drain electrode connected to the source / drain doped region through the contact hole and directly contacting the exposed pixel electrode; And forming a planarization film having an opening that exposes a portion of the pixel electrode.

Description

Flat Panel Display with Improved Transmittance and Method for Fabricating the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, a CMOS thin film transistor capable of simplifying a process using a halftone mask, prioritizing a transparent electrode forming process, improving transmittance, and preventing damage to source / drain electrodes. An organic light emitting display device and a method of manufacturing the same.

1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional CMOS thin film transistor organic light emitting display device.

Referring to FIG. 1A, a buffer oxide film 110 is formed on a transparent insulating substrate 100, and a semiconductor is formed by using a first mask (not shown) for forming a semiconductor layer on the buffer oxide film 110. Layers 121, 123, 125 are formed. The first semiconductor layer 121 is formed in the first region 101 in which the driving NMOS transistor is to be formed, and the second semiconductor layer 123 is formed in the second region 103 in which the driving PMOS transistor is to be formed. The third semiconductor layer 125 is formed in the third region 105 where the pixel PMOS transistor is to be formed.

A gate insulating film 130 is formed on the entire surface of the substrate, a gate metal material is deposited on the gate insulating film 130, and then a driving PMOS transistor is formed by using a gate forming second mask (not shown in the figure) of the PMOS transistor. A gate electrode 143 and a gate electrode 145 of the pixel PMOS transistor are formed. Meanwhile, when the gate electrodes 143 and 145 of the PMOS transistor are formed, the conductive pattern 140 is formed in the first region 101. The conductive pattern 140 serves as a mask for preventing ion implantation into the first semiconductor layer 121 for the NMOS transistor in a subsequent P + type ion implantation process, and is patterned in a subsequent process to form a gate electrode for the NMOS transistor. do.

P + type impurities are implanted into the second and third semiconductor layers 123 and 125 by using the conductive patterns 140 and the gate electrodes 143 and 145 as masks, respectively, to form a high concentration source / drain of the PMOS transistor. Doped regions 153 and 155 are formed.

Referring to FIG. 1B, the photoresist layer 210 is coated on the entire surface of the substrate, and then the photoresist layer 210 is patterned using a third mask (not shown) for forming a gate of the NMOS transistor. The photoresist pattern 211 of the photoresist 210 serves as a gate forming mask of the NMOS transistor, and the photoresist pattern 212 formed on the gate insulating layer 130 except for the first region 101 has a subsequent N-type. The ion implantation process acts as a mask to prevent the implantation of N-type impurities into the second region 103 and the third region 105 and the fourth region 107 where the pixel electrode is formed in a subsequent process.

The conductive pattern 140 is patterned using the photoresist film 210 as a mask to form a gate 141 of an NMOS transistor, and then ion implantation of N-type impurities into the semiconductor layer 121 results in a low concentration source of the NMOS transistor. / Drain doped region 151 is formed.

Referring to FIG. 1C, after removing the photoresist layer 210, the photoresist layer 220 is applied to the entire surface of the substrate and patterned by using a fourth mask (not shown) for LDD formation. The photoresist layer pattern 221 of the photoresist layer 220 serves as an ion implantation mask for forming an LDD of an NMOS transistor, and the photoresist layer pattern 222 excludes the first region 101 during the N + type ion implantation process in a subsequent process. It acts as a mask to prevent the implantation of N + -type impurities into the portion.

N + type impurities are ion-implanted into the semiconductor layer 121 using the photoresist film 220 as a mask to form a high concentration source / drain doped region 152 of the NMOS transistor, thereby forming a source / drain doped region having an LDD structure. Form.

Referring to FIG. 1D, after removing the photoresist layer 220, an interlayer insulating layer 160 is formed on the entire surface of the substrate, and the interlayer insulating layer 160 is formed by using a fifth mask for contact hole formation (not shown). And the gate insulating layer 130 are etched to expose the contact holes 161, 163, and 165 which expose the high concentration source / drain doped region 152 of the NMOS transistor and the high concentration source / drain doped regions 153 and 155 of the PMOS transistor. ) Respectively.

Subsequently, a source / drain electrode material is deposited on the entire surface of the substrate, and then the source / drain electrode material is patterned using a sixth mask (not shown) for forming a source / drain electrode to form the contact holes 161, 163, and the like. Source / drain electrodes 171 of the NMOS transistors contacting the source / drain doped regions 152, 153, and 155, respectively, and source / drain electrodes 173 and 175 of the PMOS transistors are formed through 165. . In this case, one of the source / drain electrodes of the switching NMOS transistor and the PMOS transistor, that is, the drain electrodes 171 and 173 is connected to each other.

After the passivation layer 180 is formed on the entire surface of the substrate, the passivation layer 180 is etched using a seventh mask for forming a via hole (not shown) to form one of the source / drain electrodes 175 of the pixel PMOS transistor. For example, the via hole 185 exposing the drain electrode is formed. Subsequently, a transparent conductive film is deposited on the entire surface of the substrate, and then the transparent conductive film is patterned by using an eighth mask (not shown) for forming a pixel electrode and connected to the drain electrode 175 through the via hole 185. The pixel electrode 190 is formed in the fourth region 107.

Next, the planarization layer 200 is formed on the entire surface of the substrate, and then the openings 205 are formed to expose the pixel electrode 190 by etching the planarization layer using a ninth mask for opening formation (not shown in the drawing). . Although not shown in the drawing, an organic light emitting layer is formed on the pixel electrode 190 in the opening and a cathode is formed thereon.

As a result, a driving CMOS transistor including an NMOS transistor formed in the first region 101 and a PMOS transistor formed in the second region 103 is formed, and a pixel PMOS transistor is formed in the third region 105. In the region 107, a conventional CMOS thin film transistor organic light emitting display device having a pixel electrode 190 exposed through an opening 205 is obtained.

However, the conventional method of manufacturing the organic light emitting display device described above has a problem that the process is very complicated because it is manufactured using nine masks. In addition, since the pixel electrode is formed after the source / drain electrode is formed, there is a problem that the lower source / drain electrode is damaged during the patterning process for forming the pixel electrode. In addition, since light emitted from the organic light emitting layer passes through a multilayer insulating film, for example, a protective film, an interlayer insulating film, a gate insulating film, and a buffer film, there is a problem that the transmittance is lowered.

Accordingly, an object of the present invention is to provide a method for manufacturing a CMOS thin film transistor organic electroluminescent display device in which the process is simplified by using a halftone mask.

Another object of the present invention is to provide a CMOS thin film transistor organic light emitting display device and a method of manufacturing the same, which can improve transmittance and prevent damage to source / drain electrodes.

1A through 1D are cross-sectional views illustrating a method of manufacturing a conventional CMOS thin film transistor organic light emitting display device;

2A to 2F are cross-sectional views illustrating a method of manufacturing a CMOS thin film transistor organic light emitting display device having improved transmittance according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

300: insulating substrate 310: buffer layer

321, 323, 325: semiconductor layer 330: gate insulating film

341, 343, 345: gate

352, 353, 355: source / drain doping region

360: transparent conductive film 365: pixel electrode

370: interlayer insulating film 381, 383, 385: source / drain electrodes

390: planarization film 395: opening

In order to achieve the above object, the present invention comprises the steps of forming a semiconductor layer on an insulating substrate; Forming a gate insulating film on the entire surface of the substrate; Forming a gate electrode on a portion of the gate insulating film corresponding to the semiconductor layer; Forming a source / drain doped region in the semiconductor layer using a gate as a mask; Forming a pixel electrode using a halftone mask; Forming an interlayer insulating film on the entire surface of the substrate; Etching the interlayer insulating film to form a contact hole exposing the source / drain doped region and exposing the pixel electrode; Forming a source / drain electrode connected to the source / drain doped region through the contact hole and directly contacting the exposed pixel electrode; A method of manufacturing a flat panel display device, the method comprising: forming a planarization film having an opening exposing a portion of the pixel electrode.

In addition, the present invention is a semiconductor layer formed on an insulating substrate; A gate insulating film formed on the front surface of the substrate; A gate formed over the semiconductor layer of the gate insulating film; A pixel electrode formed on the gate insulating layer at a predetermined distance from the gate; An interlayer insulating film formed on the entire surface of the substrate to expose the pixel electrode; A source / drain electrode formed on the interlayer insulating layer and connected to the semiconductor layer and in direct contact with the exposed pixel electrode; A flat panel display device having a planarization film having an opening that exposes a portion of the pixel electrode is provided.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2A through 2F are cross-sectional views illustrating a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, a buffer oxide film 310 is deposited to a thickness of 3000 Å on a transparent insulating substrate 300 by PECVD. An amorphous silicon film (a-Si: H) containing hydrogen is deposited on the buffer oxide film 310 to a thickness of 500 kPa by PECVD, and then dehydrogenation is performed for 13 minutes at a temperature of 470 ° C. . Next, the amorphous silicon film is crystallized into a polysilicon film through an ELA (Excimer Laser Annealing) process.

A first region 301 in which a driving NMOS transistor is formed by patterning a polysilicon film crystallized using a first mask (not shown in the drawing) for forming a semiconductor layer, and a second region in which a driving PMOS transistor is formed 303 and semiconductor layers 321, 323, and 325 are formed in the third region 305 where the PMOS transistors for pixels are formed.

A gate insulating film 330 is formed over the substrate, and a gate metal material is deposited on the gate insulating film 330. The gate electrodes 343 and 345 of the PMOS transistor are formed using a second mask for gate formation (not shown in the drawing) of the PMOS transistor, and a conductive pattern 340 is formed in the first region 301. do. The conductive pattern 340 serves as a mask in an ion implantation process of a P + type impurity for forming a source / drain doped region of a PMOS transistor, and is patterned in a subsequent process to become a gate electrode for an NMOS transistor.

P + type impurities are implanted into the semiconductor layers 323 and 325 using the conductive patterns 340, the gate electrodes 343 and 345 as masks, and thus the high concentration source / drain doping region 353 of the PMOS transistor, Form 355. At this time, P + type impurities are not implanted into the NMOS transistor semiconductor layer 321 by the conductive pattern 340.

Referring to FIG. 2B, the photoresist layer 410 is coated on the entire surface of the substrate, and then the photoresist layer 410 is patterned by using a gate forming third mask (not shown) of the NMOS transistor. The photoresist pattern 411 of the photoresist 410 serves as a gate forming mask of the NMOS transistor, and the photoresist pattern 412 has a second region 303 and a third region 305 during the N-type impurity ion implantation process. And an N-type impurity into the fourth region 307 where the pixel electrode is formed.

The conductive pattern 340 is patterned using the photoresist 410 as a mask to form a gate 341 of the NMOS transistor, and then ion implantation of low concentration N-type impurities into the semiconductor layer 321 is used to form the NMOS transistor. A low concentration source / drain doped region 351 is formed.

Referring to FIG. 2C, after removing the photosensitive film 410, the transparent conductive film 360 is deposited on the front surface of the substrate, and the photosensitive film 420 is coated on the transparent conductive film 360. Next, the photosensitive film 420 is patterned using the halftone mask 500 as a fourth mask. The halftone mask 500 includes a blocking region 510, a transflective region 520, and a transmissive region.

The blocking region 510 corresponds to the fourth region 307 in which the pixel electrode is to be formed, and a blocking film such as chromium is formed on the substrate to block all light. The transmission region corresponds to a portion where the N + -type impurity is ion implanted, and transmits all light as a portion where a blocking film is not formed on the substrate. The semi-transmissive region 520 corresponds to the second and third regions 303 and 305 and corresponds to a portion of the first region 301 except for the portion where N + -type impurities are ion implanted, and the barrier layer on the substrate. It is formed in a lattice shape and semi-transmissive by adjusting the amount of light transmitted.

Accordingly, the photoresist layer 420 patterned using the halftone mask 500 is patterned to correspond to the blocking region 510 rather than the photoresist pattern 421 patterned to correspond to the transflective region 520. The photoresist film 420 is removed from the portion of the semiconductor layer 321 of the first region 301 that is thicker than that of the first region 301.

Referring to FIG. 2D, the transparent conductive film 360 below is patterned using the photosensitive films 420 having photosensitive film patterns 421 and 422 having different thicknesses as masks. Accordingly, the transparent conductive film 360 is removed from the portion corresponding to the transmissive region of the halftone mask 500, that is, the portion where the N + type impurity is ion implanted in a subsequent process, thereby exposing the gate insulating film 330.

Next, when the photoresist 420 is etched by the dry etching method, the photoresist pattern 422 is present only in the fourth region corresponding to the blocking region 510, and the photoresist pattern is formed in the remaining region corresponding to the transflective region 520. 421 is removed to expose the transparent conductive film 360.

Subsequently, when the N + type impurities are ion-implanted into the first semiconductor layer 321, the transparent conductive film 360 and the photosensitive film pattern 422 act as masks, and thus the first semiconductor layer 321 has a high concentration N + type high concentration source / drain doping. Region 352 is formed.

Next, when the exposed transparent conductive film 360 of the first region 301, the second region 303, and the third region 305 is removed by dry etching, the first photoresist pattern 422 is used as a mask. In the third to third regions 301, 303, and 305, the gate electrodes 341, 343, and 345 are exposed. Subsequently, when the photoresist pattern 422 remaining in the fourth region 307 is removed, the pixel electrode 365 is formed.

According to the exemplary embodiment of the present invention, since the pixel electrode 365 is formed on the gate insulating film 330, light emitted from the organic light emitting layer to be formed in a subsequent process does not pass through the multilayer insulating film, unlike the conventional art. Can be improved. In addition, by forming the pixel electrode 365 using a halftone mask and simultaneously forming an N + type high concentration source / drain doped region, one mask process for forming an LDD region is eliminated.

Instead of the method of forming the N + type impurity and the pixel electrode using the halftone mask according to the embodiment of the present invention, ion implantation of the N + type impurity is performed by using photosensitive film patterns 421 and 422 having different thicknesses. By forming the high concentration source / drain regions 352, the photoresist layer 420 may be dry-etched such that the photoresist pattern 422 remains only in the fourth region 307.

That is, by using the photoresist film 420 having photoresist patterns 421 and 422 having different thicknesses, the transparent conductive film 360 of the portion where the N + type impurity of the first region 310 is to be formed is etched. N + type impurities are ion-implanted into the first region 310 using the photoresist layer 420 as a mask to form an N + type high concentration source / drain region 352, and the photoresist pattern 422 remains only in the fourth region 307. Dry etching the photosensitive film 420 to expose the transparent conductive film 360, and etching the exposed transparent conductive film 360 using the photosensitive film pattern 420, and removing the remaining photosensitive film pattern 422 to remove the pixel electrode. To form 365.

Referring to FIG. 2F, the NMOS transistor and the PMOS transistor are formed by etching the interlayer insulating layer 370 using a fifth mask for contact hole formation (not shown). Contact holes 371, 373, and 375 exposing portions of the source / drain doped regions 352, 353, and 355 of the semiconductor substrate 370 are exposed.

Subsequently, the source / drain electrode material is deposited on the entire surface of the substrate, and then the source / drain electrode material is patterned using a sixth mask (not shown) to form the source / drain doped regions 351, 353, Source / drain electrodes 381, 383, and 385 are respectively contacted with 355. At this time, one of the source / drain electrodes of the driving NMOS transistor and the PMOS transistor, that is, the drain electrodes 381 and 383 are formed to be connected to each other.

In the exemplary embodiment of the present invention, the source / drain electrodes of the pixel electrode 365 are etched by forming the pixel electrode 365 and then forming the source / drain electrodes 381, 383, and 385. In addition to preventing damage, the source / drain electrodes are formed to be in direct contact with the exposed pixel electrode 365, thus eliminating the mask forming process and the mask process for forming via holes by etching the protective film. Can be.

Subsequently, a planarization film 390 such as acryl is deposited on the entire surface of the substrate, and the openings 395 are formed by etching the planarization film 390 by using an opening forming seventh mask (not shown).

Although not shown in the drawing, an organic light emitting layer is formed on the pixel electrode 365 in the opening 395 and a cathode is formed thereon. As a result, a driving CMOS transistor including an NMOS transistor formed in the first region 301 and a PMOS transistor formed in the second region 303 is formed, and a pixel PMOS transistor is formed in the third region 305. In the region 307, the CMOS thin film transistor organic light emitting display device of the present invention having the pixel electrode 365 exposed through the opening 395 is obtained.

Although the exemplary embodiment of the present invention exemplifies a driving thin film transistor as a CMOS thin film transistor, the pixel thin film transistor may be implemented as a CMOS thin film transistor.

According to the present invention as described above, a CMOS thin film transistor organic electroluminescent display device can be manufactured by using a halftone mask using seven mask processes in which two mask processes are reduced compared to the conventional nine mask processes. This has the advantage of simplifying the process.

In addition, damage to the source / drain electrodes can be prevented by forming the pixel electrode before forming the source / drain electrodes. In addition, since the pixel electrode is formed directly on the substrate, there is an advantage in that the transmittance of light emitted from the organic light emitting layer can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (5)

Forming a semiconductor layer on the insulating substrate; Forming a gate insulating film on the entire surface of the substrate; Forming a gate electrode on a portion of the gate insulating film corresponding to the semiconductor layer; Forming a source / drain doped region in the semiconductor layer using a gate as a mask; Forming a pixel electrode using a halftone mask; Forming an interlayer insulating film on the entire surface of the substrate; Etching the interlayer insulating film to form a contact hole exposing the source / drain doped region and exposing the pixel electrode; Forming a source / drain electrode connected to the source / drain doped region through the contact hole and directly contacting the exposed pixel electrode; And forming a planarization film having an opening for exposing a portion of the pixel electrode. The flat panel of claim 1, wherein when the pixel electrode is formed using a halftone mask, a doping concentration is higher than that of the source / drain doping region, and a high concentration source / drain doping region having the same conductivity type is formed. Method for manufacturing a display device. The method of claim 2, wherein the pixel electrode and the high concentration source / drain region are formed using a halftone mask. Forming a transparent conductive film on the entire surface of the substrate; Forming a photosensitive film on the transparent conductive film; Exposing a transparent conductive film in a portion corresponding to the high concentration source / drain doped region by using a halftone mask, and forming a photoresist pattern having a thicker portion in the portion corresponding to the pixel electrode; Etching the exposed transparent conductive film using the photosensitive film patterns having different thicknesses; Dry etching the photoresist pattern, leaving the photoresist pattern only on a portion corresponding to the pixel electrode, and exposing the transparent conductive film on the remaining portion; Forming the high concentration source / drain doped region in the semiconductor layer using the transparent conductive layer and the photosensitive layer as a mask; Etching the exposed transparent conductive film using the remaining photoresist pattern as a mask; And removing the remaining photoresist pattern to form the pixel electrode. The method of claim 2, wherein the pixel electrode and the high concentration source / drain doped region are formed using a halftone mask. Forming a transparent conductive film on the entire surface of the substrate; Forming a photosensitive film on the transparent conductive film; Exposing a transparent conductive film in a portion corresponding to the high concentration source / drain doped region by using a halftone mask, and forming a photoresist pattern having a thicker portion in the portion corresponding to the pixel electrode; Etching the exposed transparent conductive film using the photosensitive film pattern; Forming the high concentration source / drain doped region in the semiconductor layer using the photoresist pattern as a mask; Dry etching the photoresist pattern to expose only the portion corresponding to the pixel electrode and to expose the transparent conductive film; Etching the exposed transparent conductive film using the remaining photoresist pattern as a mask; And removing the remaining photoresist pattern to form the pixel electrode. A semiconductor layer formed on the insulating substrate; A gate insulating film formed on the front surface of the substrate; A gate formed over the semiconductor layer of the gate insulating film; A pixel electrode formed on the gate insulating film at a predetermined distance from the gate; An interlayer insulating film formed on the entire surface of the substrate to expose the pixel electrode; A source / drain electrode formed on the interlayer insulating layer and connected to the semiconductor layer and in direct contact with the exposed pixel electrode; And a flattening film having an opening for exposing a portion of the pixel electrode.