KR100440070B1 - A method for forming a transistor of a semiconductor device - Google Patents
A method for forming a transistor of a semiconductor device Download PDFInfo
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- KR100440070B1 KR100440070B1 KR10-2001-0077409A KR20010077409A KR100440070B1 KR 100440070 B1 KR100440070 B1 KR 100440070B1 KR 20010077409 A KR20010077409 A KR 20010077409A KR 100440070 B1 KR100440070 B1 KR 100440070B1
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000001052 transient effect Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 21
- 230000010354 integration Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Abstract
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 얕은 접합 ( shallow junction )을 용이하게 형성할 수 있도록 하기 위하여, 반도체기판 상에 활성영역을 정의하는 소자분리막을 형성하고 상기 활성영역에 고농도의 불순물 접합영역으로 예정된 부분에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역을 형성한 다음, 게이트전극 영역으로 예정된 부분의 반도체기판을 식각하여 제1트렌치를 형성하고 상기 제1트렌치를 매립하는 게이트산화막 및 게이트전극용 도전층의 적층구조를 형성한 다음, 상기 활성영역 상부에 살리사이드층을 형성하고 저농도의 불순물 접합영역으로 예정된 부분이 제거된 감광막패턴을 형성한 다음, 상기 감광막패턴을 마스크로 하여 상기 살리사이드층, 게이트전극용 도전층 및 게이트산화막을 순차적으로 건식 이방성식각함으로써 상기 제1트렌치 저부에 상기 게이트산화막이 남는 제2트렌치를 형성하고 상기 감광막패턴을 마스크로 하여 상기 게이트산화막 하부에 저농도의 불순물 접합영역을 형성한 다음, 상기 감광막패턴을 제거하고 상기 제2트렌치를 매립하는 절연막 스페이서를 형성하는 공정으로 게이트전극이 고농도의 불순물 접합영역보다 낮게 형성되어 초저접합을 용이하게 형성할 수 있는 공정마진을 확보할 수 있어 반도체소자의 고집적화를 가능하게 하고 그에 따른 소자의 소자의 특성을 확보할 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, in order to form a shallow junction easily, a device isolation film defining an active region is formed on a semiconductor substrate and a high concentration of impurities are formed in the active region. A high concentration of impurity junction regions are formed by ion implanting a high concentration of impurities into a portion intended for the junction region, and then etching the semiconductor substrate of the portion intended for the gate electrode region to form a first trench and filling the first trench. And forming a laminate structure of the conductive layer for the gate electrode, forming a salicide layer on the active region, and forming a photoresist pattern having a predetermined portion as a low concentration impurity junction region, and then using the photoresist pattern as a mask. The salicide layer, the gate electrode conductive layer and the gate oxide film are sequentially Dry anisotropic etching to form a second trench in the bottom of the first trench, the second oxide leaving the gate oxide film; and forming a low concentration impurity junction region under the gate oxide film using the photoresist pattern as a mask, and then removing the photoresist pattern. In the process of forming the insulating layer spacer to fill the second trench, the gate electrode is formed lower than the high concentration impurity junction region to secure the process margin for easily forming the ultra low junction, thereby enabling high integration of the semiconductor device. It is a technology that can ensure the characteristics of the device of the device according to.
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 보다 상세하게는 고농도의 불순물 접합영역 보다 낮은 지역에 게이트전극을 형성하여 얕은 접합을 용이하게 형성함으로써 그에 따른 공정마진을 확보할 수 있는 기술에 관한 것이다.The present invention relates to a method of forming a transistor of a semiconductor device, and more particularly, to a technique capable of easily forming a shallow junction by forming a gate electrode in a region lower than a high concentration impurity junction region to thereby secure a process margin. will be.
반도체 소자가 고집적화 됨에 따라 트렌지스터의 소스와 드레인의 간격이 좁아질 뿐만 아니라 채널이 길이도 짧아지게 되었다. 이로 인해 SCE(short channel effect), HCE(hot carrier effect)에 의한 소자의 열화 등 많은 소자구조적 문제가 야기된다. 이러한 문제를 해결하고 양호한 트렌지스터 특성을 얻기 위해서 소자 구조 측면에서 여러 가지 방안들이 강구되고 있다.As semiconductor devices become more integrated, not only the gap between the source and drain of the transistor is narrower but also the channel length is shorter. This causes many device structural problems, such as deterioration of the device due to short channel effect (SCE) and hot carrier effect (HCE). In order to solve this problem and to obtain good transistor characteristics, various measures have been taken in terms of device structure.
종래의 트렌지스터 형성방법은 LDD(light doped drain)구조를 이용하는 것인데, LDD 구조역시 0.13㎛ 혹은 0.1㎛이하의 미세구조의 소자제조에 이용될 경우 LDD 소자의 구조적 문제 때문에 반도체 장치에 악영향을 미치거나 원하는 소자 특성을 얻을 수 없다. 즉 0.1㎛ 기술에서는 1000Å 이하의 얕은 접합면 형성기술과 400Å 이하의 얕은 LDD 형성기술이 필요하게 되는데, 상기의 기술은 반도체 공정장비의 한계 및 공정자체의 어려움 등으로 현재 많은 논의 및 공정개발 대안들이 제시되고 있다.Conventional transistor formation method is to use a light doped drain (LDD) structure, LDD structure also adversely affect the semiconductor device due to structural problems of the LDD device when used in the fabrication of microstructures of less than 0.13㎛ or 0.1㎛ Device characteristics cannot be obtained. In other words, the 0.1 ㎛ technology requires a shallow junction surface formation technology of 1000Å or less and a shallow LDD formation technology of 400Å or less. Is being presented.
예를 들면, 낮은 에너지로 이온을 주입하는 장비를 이용하여 접합면 두께를 조정하는 경우라도 확산 메커니즘에 의해 후속 공정에서 접합면이 확장되어 SCH, 트렌지스터 펀치쓰루, 오프전류(Ioff)가 증가하게 되어, 동작전류 대 오프전류(Ion/Ioff)마진이 감소할 뿐 아니라 임계전압이 불안정해지는 등의 문제가 발생한다.For example, even in the case of adjusting the junction thickness by using a device for implanting ions with low energy, the junction surface is expanded in a subsequent process by the diffusion mechanism so that the SCH, transistor punchthrough, and off current (I off ) are increased. As a result, not only the operating current versus off current (I on / I off ) margin is reduced, but also a problem such as the threshold voltage becomes unstable.
본 발명은 상기의 문제점을 해결하기 위한 것으로서, 반도체기판에 고농도의 불순물 접합영역을 형성하고 그 사이에 게이트전극이 형성될 영역의 반도체기판을 식각하여 트렌치를 형성한 다음, 후속공정으로 게이트전극을 형성하고 게이트전극과 고농도의 불순물 접합영역 사이의 계면에 절연막 스페이서를 형성하며, 상기 절연막 스페이서 사이에 저농도의 불순물 접합영역을 형성하여 반도체소자의 고집적화에 충분한 특성을 갖는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, to form a high concentration impurity junction region on the semiconductor substrate and to form a trench by etching the semiconductor substrate of the region where the gate electrode will be formed therebetween, and then the gate electrode And forming an insulating film spacer at an interface between the gate electrode and a high concentration impurity junction region, and forming a low concentration impurity junction region between the insulating film spacers to provide a method of forming a transistor of a semiconductor device having characteristics sufficient for high integration of the semiconductor device. Its purpose is to.
도 1a 내지 도 1i는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1A to 1I are cross-sectional views showing a transistor forming method of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체기판 11 : 소자분리막10 semiconductor substrate 11: device isolation film
12 : 고농도의 불순물 접합영역 13 : 제1감광막패턴12: high concentration impurity junction region 13: first photosensitive film pattern
15 : 제2감광막패턴 16 : 제1트렌치15: second photosensitive film pattern 16: first trench
18 : 게이트산화막 20 : 게이트전극용 도전층18 gate oxide film 20 conductive layer for gate electrode
22 : 살리사이드층 24 : 게이트전극22: salicide layer 24: gate electrode
26 : 제2트렌치 28 : 저농도의 불순물 접합영역26: second trench 28: low concentration impurity junction region
30 : 절연막 스페이서30: insulating film spacer
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
반도체기판 상에 활성영역을 정의하는 소자분리막을 형성하는 공정과,Forming a device isolation film defining an active region on the semiconductor substrate;
상기 활성영역에 고농도의 불순물 접합영역으로 예정된 부분에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역을 형성하는 공정과,Forming a high concentration impurity junction region by ion implanting a high concentration of impurities into a portion predetermined as a high concentration impurity junction region in the active region;
게이트전극 영역으로 예정된 부분의 반도체기판을 식각하여 제1트렌치를 형성하는 공정과,Forming a first trench by etching the semiconductor substrate of the predetermined portion as the gate electrode region;
상기 제1트렌치를 매립하는 게이트산화막 및 게이트전극용 도전층의 적층구조를 형성하는 공정과,Forming a stacked structure of a gate oxide film and a gate electrode conductive layer filling the first trench;
상기 활성영역 상부에 살리사이드층을 형성하는 공정과,Forming a salicide layer on the active region;
저농도의 불순물 접합영역으로 예정된 부분이 제거된 감광막패턴을 형성하는공정과,Forming a photoresist pattern in which a portion predetermined as a low concentration impurity junction region is removed;
상기 감광막패턴을 마스크로 하여 상기 살리사이드층, 게이트전극용 도전층 및 게이트산화막을 순차적으로 건식 이방성식각하여 상기 제1트렌치 저부에 상기 게이트산화막이 남는 제2트렌치를 형성하는 공정과,Sequentially dry anisotropically etching the salicide layer, the gate electrode conductive layer, and the gate oxide film using the photoresist pattern as a mask to form a second trench in which the gate oxide film remains in the bottom of the first trench;
상기 감광막패턴을 마스크로 하여 상기 게이트산화막 하부에 저농도의 불순물 접합영역을 형성하고 상기 감광막패턴을 제거하는 공정과,Forming a low concentration impurity junction region under the gate oxide film using the photoresist pattern as a mask and removing the photoresist pattern;
상기 제2트렌치를 매립하는 절연막 스페이서를 형성하는 공정을 포함하는 것과,Forming an insulating film spacer filling the second trench;
상기 소자분리막은 3300 ∼ 3700 Å 두께로 형성하는 것과,The device isolation film is formed to a thickness of 3300 ~ 3700 Å,
상기 고농도 불순물의 이온주입공정은 2E15 ∼ 5E15 atoms/cm2의 B11농도를 10 ∼ 20 KeV의 에너지로 주입하는 것과,In the ion implantation step of the high concentration impurity, the B 11 concentration of 2E15 to 5E15 atoms / cm 2 is injected at an energy of 10 to 20 KeV,
상기 고농도의 불순물 접합영역은 1500 ∼ 2100 Å 넓이, 800 ∼ 1200 Å 깊이로 형성하는 것과,The high concentration impurity junction region is formed to a width of 1500 ~ 2100 ,, 800 ~ 1200 Å,
상기 제1트렌치 형성공정을 압력 13 ∼ 17 mTorr, 소오스 전력 430 ∼ 470 Watt, 바이어스 전력 180 ∼ 220 Watt, 식각가스 6 ∼ 10 sccm 의 O2, 8 ∼ 12 SCCM의 N2, 30 ∼ 40 SCCM의 Cl2, 130 ∼ 170 SCCM의 HBr 유량, 진행시간 60 ∼ 70 초 동안으로 하는 조건으로 실시하는 것과,The first trench forming process was carried out at a pressure of 13 to 17 mTorr, source power of 430 to 470 Watts, bias power of 180 to 220 Watts, etching gas of 6 to 10 sccm, O 2 , 8 to 12 SCCM of N 2 , and 30 to 40 SCCM. Conducting under conditions of Cl 2 , HBr flow rate of 130 to 170 SCCM and running time for 60 to 70 seconds,
상기 제1트렌치는 700 ∼ 900 Å 깊이, 2500 ∼ 3500 Å 넓이로 형성하는 것과,The first trench is formed to be 700 to 900 mm deep and 2500 to 3500 mm wide;
상기 게이트산화막은 20 ∼ 40 Å 두께로 형성하고, 상기 게이트전극용 도전층은 1800 ∼ 2200 Å 두께의 폴리실리콘으로 형성하는 것과,The gate oxide film is formed to have a thickness of 20 to 40 GPa, and the conductive layer for the gate electrode is formed of polysilicon having a thickness of 1800 to 2200 GPa,
상기 살리사이드층은 코발트, 티타늄 또는 텅스텐과 같은 고융점금속 중에서 한가지를 증착하고 2차례의 열처리공정을 실시하여 활성영역 상에만 형성하되,The salicide layer is formed on the active region by depositing one of high melting point metals such as cobalt, titanium, or tungsten and performing two heat treatment processes.
상기 열처리공정은 650 ∼ 750 ℃ 의 온도에서 10 내지 30초간 실시하는 제1열처리공정과, 800 ∼ 900 ℃ 의 온도에서 10 ∼ 30초 동안 실시하는 제2열처리공정으로 실시하는 것과,The heat treatment step is performed by the first heat treatment step performed for 10 to 30 seconds at a temperature of 650 ~ 750 ℃, and the second heat treatment step carried out for 10 to 30 seconds at a temperature of 800 ~ 900 ℃,
상기 건식 이방성 식각공정은 주식각공정, 식각종말점의 식각공정 및 과도식각공정의 3단계로 실시하되,The dry anisotropic etching process is carried out in three steps of the stock etching process, the etching process of the etching end point and the transient etching process,
상기 주식각공정은 챔버압력 8 ∼ 12 mTorr, 소오스 전력 450 ∼ 550 Watt, 바이어스 전력 100 ∼ 140 Watt, 식각가스 80 ∼ 120 SCCM 의 HBr, 35 ∼ 45 SCCM 의 Cl2유량, 식각시간 35 ∼ 45 초로 하는 조건에서 실시하고,The stock angle process is performed at a chamber pressure of 8 to 12 mTorr, source power of 450 to 550 Watt, bias power of 100 to 140 Watt, HBr of etching gas 80 to 120 SCCM, Cl 2 flow rate of 35 to 45 SCCM, and etching time of 35 to 45 seconds. Under the conditions of
상기 식각종말점의 식각공정은 챔버압력 8 ∼ 12 mTorr, 소오스 전력 250 ∼ 350 Watt, 바이어스 전력 35 ∼ 45 Watt, 식각가스 80 ∼ 100 SCCM 의 HBr, 20 ∼ 40 SCCM 의 Cl2, 5 ∼ 9 SCCM 의 HeO2유량, 시간 18 ∼ 24 초로 하는 조건으로 실시하고,The etching process of the etching end point is the chamber pressure of 8-12 mTorr, source power 250-350 Watt, bias power 35-45 Watt, etching gas 80-100 SCCM HBr, 20-40 SCCM Cl 2 , 5-9 SCCM HeO 2 flow rate is carried out under the conditions of 18 to 24 seconds.
상기 과도식각공정은 챔버압력 80 ∼ 100 mTorr, 소오스 전격 550 ∼ 650 Watt, 바이어스 전력 120 ∼ 180 Watt, 식각가스 50 ∼ 70 SCCM 의 HBr, 8 ∼ 12 SCCM 의 HeO2유량, 식각시간 35 ∼ 45 초로 하는 조건으로 실시하는 것과,The transient etching process is performed at a chamber pressure of 80 to 100 mTorr, source electric power of 550 to 650 Watt, bias power of 120 to 180 Watt, etching gas of 50 to 70 SCCM of HBr, of 8 to 12 SCCM of HeO 2 , and etching time of 35 to 45 seconds To perform on condition to do,
상기 저농도의 불순물 이온주입공정은 BF2를 10 ∼ 20 KeV의 에너지로 5E13 ∼ 2E14 atoms/cm2만큼 주입하여 실시하는 것과,The low concentration impurity ion implantation step is performed by injecting BF 2 by 5E13 to 2E14 atoms / cm 2 at an energy of 10 to 20 KeV,
상기 절연막 스페이서는 질화막으로 형성하되, 상기 질화막은 700 ∼ 740 ℃ 의 온도의 노(furnace) 안에서 160 ∼ 200 분 동안 NH3과 SiC2H6를 소오스로 하여 증착하는 것을 특징으로 한다.The insulating film spacer may be formed of a nitride film, and the nitride film may be deposited using a source of NH 3 and SiC 2 H 6 for 160 to 200 minutes in a furnace at a temperature of 700 to 740 ° C.
한편, 본 발명의 원리는,On the other hand, the principle of the present invention,
반도체기판에 고농도의 불순물 접합영역을 형성하고 상기 고농도의 불순물 접합영역 사이의 반도체기판을 식각하여 형성된 트렌치에 게이트전극을 형성한 다음, 상기 게이트전극과 고농도의 불순물 접합영역 사이에 절연막 스페이서가 구비되며 그 하부에 저농도의 불순물 접합영역이 구비되는 구조로 트랜지스터를 형성함으로써 얕은 접합 트랜지스터의 공정 마진을 용이하게 확보할 수 있도록 하는 것이다.A high concentration impurity junction region is formed on the semiconductor substrate, a gate electrode is formed in the trench formed by etching the semiconductor substrate between the high concentration impurity junction regions, and an insulating film spacer is provided between the gate electrode and the high concentration impurity junction region. By forming a transistor having a structure having a low concentration of impurity junction regions at the bottom thereof, it is possible to easily secure a process margin of a shallow junction transistor.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1i는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.1A to 1I are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체기판(10) 상에 소자분리막(11)을 트렌치형으로 형성한다.Referring to FIG. 1A, the device isolation layer 11 is formed in a trench on the semiconductor substrate 10.
이때, 상기 소자분리막(11)은 3300 ∼ 3700 Å 두께로 형성한다.In this case, the device isolation layer 11 is formed to a thickness of 3300 ~ 3700Å.
도 1b를 참조하면, 상기 반도체기판(10) 상부에 제1감광막패턴(13)을 형성한다. 이때, 상기 제1감광막패턴(13)은 고농도의 불순물 접합영역을 형성하기 위한 노광마스크를 이용한 노광 및 현상공정으로 형성한 것이다.Referring to FIG. 1B, a first photoresist layer pattern 13 is formed on the semiconductor substrate 10. In this case, the first photoresist layer pattern 13 is formed by an exposure and development process using an exposure mask for forming a high concentration impurity junction region.
그리고, 상기 제1감광막패턴(13)을 마스크로 하여 상기 반도체기판(10)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역(12)을 형성한다.A high concentration of impurity junction regions 12 are formed by ion implanting high concentrations of impurities into the semiconductor substrate 10 using the first photoresist pattern 13 as a mask.
이때, 상기 이온주입공정은 2E15 ∼ 5E15 atoms/cm2의 B11농도를 10 ∼ 20 KeV의 에너지로 주입한 것이다.At this time, in the ion implantation step, a B 11 concentration of 2E15 to 5E15 atoms / cm 2 is injected at an energy of 10 to 20 KeV.
그리고, 상기 고농도의 불순물 접합영역(12)은 1500 ∼ 2100 Å 넓이, 800 ∼ 1200 Å 두께로 형성한다.The high concentration impurity junction region 12 is formed to have a width of 1500 to 2100 mm 3 and a thickness of 800 to 1200 mm 3.
도 1c를 참조하면, 상기 제1감광막패턴(13)을 제거하고 상기 반도체기판(10) 상에 제2감광막패턴(15)을 형성한다.Referring to FIG. 1C, the first photoresist pattern 13 is removed and a second photoresist pattern 15 is formed on the semiconductor substrate 10.
이때, 상기 제2감광막패턴(15)은 게이트전극 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성하되, 게이트전극이 형성될 부분이 제거된 것이다.In this case, the second photoresist pattern 15 is formed by an exposure and development process using a gate electrode mask (not shown), and the portion where the gate electrode is to be formed is removed.
그 다음, 상기 제2감광막패턴(15)을 마스크로 하여 상기 반도체기판(10)을 식각하여 게이트전극이 형성될 영역의 반도체기판을 건식식각함으로써 제1트렌치(16)를 형성한다.Next, the first trench 16 is formed by etching the semiconductor substrate 10 using the second photoresist pattern 15 as a mask to dry-etch the semiconductor substrate in the region where the gate electrode is to be formed.
이때, 상기 건식식각공정은 다음과 같은 조건으로 실시한다.At this time, the dry etching process is carried out under the following conditions.
먼저, 압력은 13 ∼ 17 mTorr, 소오스 전력은 430 ∼ 470 Watt, 바이어스 전력은 180 ∼ 220 Watt, 식각가스는 6 ∼ 10 sccm 의 O2, 8 ∼ 12 SCCM의 N2, 30 ∼ 40 SCCM의 Cl2, 130 ∼ 170 SCCM의 HBr, 진행시간은 60 ∼ 70 초 동안으로 한다.First, pressure is 13-17 mTorr, source power is 430-470 Watt, bias power is 180-220 Watt, etching gas is 6-10 sccm O 2 , 8-12 SCCM N 2 , 30-40 SCCM Cl 2 , 130-170 SCCM HBr, the running time is 60-70 seconds.
그리고, 상기 제1트렌치(16)는 700 ∼ 900 Å 깊이, 2500 ∼ 3500 Å 넓이로 형성한 것이다.The first trench 16 is formed to have a depth of 700 to 900 mm, and a width of 2500 to 3500 mm.
도 1d를 참조하면, 상기 제2감광막패턴(15)을 제거하고 상기 제1트렌치(16)을 매립하는 게이트산화막(18) 및 게이트전극용 도전층(20)을 전체표면상부에 형성한다.Referring to FIG. 1D, the second photoresist layer pattern 15 is removed and a gate oxide layer 18 and a gate electrode conductive layer 20 filling the first trench 16 are formed on the entire surface.
이때, 상기 게이트산화막은 20 ∼ 40 Å 두께로 형성하고, 상기 게이트전극용 도전층(20)은 1800 ∼ 2200 Å 두께의 폴리실리콘으로 형성한다.In this case, the gate oxide film is formed with a thickness of 20 to 40 kPa, and the conductive layer 20 for the gate electrode is made of polysilicon having a thickness of 1800 to 2200 kPa.
도 1e를 참조하면, 상기 반도체기판(10) 상의 활성영역에 살리사이드층(22)을 형성한다.Referring to FIG. 1E, the salicide layer 22 is formed in the active region on the semiconductor substrate 10.
이때, 상기 살리사이드층(22)은 코발트, 티타늄 또는 텅스텐과 같은 고융점금속 중에서 한가지를 증착하고 2차례의 열처리공정을 실시하여 활성영역 상에만 형성한 것이다.In this case, the salicide layer 22 is formed only on the active region by depositing one of high melting point metals such as cobalt, titanium, or tungsten and performing two heat treatment processes.
여기서, 상기 열처리공정은 650 ∼ 750 ℃ 의 온도에서 10 내지 30초간 실시하는 제1열처리공정과, 800 ∼ 900 ℃ 의 온도에서 10 ∼ 30초 동안 실시하는 제2열처리공정으로 실시한다.Here, the heat treatment step is carried out in a first heat treatment step performed for 10 to 30 seconds at a temperature of 650 ~ 750 ℃, and a second heat treatment step carried out for 10 to 30 seconds at a temperature of 800 ~ 900 ℃.
도 1g를 참조하면, 상기 살리사이드층(22)을 포함한 반도체기판(10) 상에 제3감광막패턴(23)을 형성한다.Referring to FIG. 1G, a third photoresist pattern 23 is formed on the semiconductor substrate 10 including the salicide layer 22.
이때, 상기 제3감광막패턴(23)을 저농도의 불순물 접합영역을 노출시킬 수 있는 노광마스크를 이용한 노광 및 현상공정으로 형성한 것이다.In this case, the third photoresist layer pattern 23 is formed by an exposure and development process using an exposure mask capable of exposing a low concentration impurity junction region.
그 다음, 상기 제3감광막패턴(23)을 마스크로 하여 상기 살리사이드층(22),게이트산화막(18) 및 게이트전극용 도전층(20)을 건식 이방성식각하여 상기 제1트렌치(16) 저부의 게이트산화막(18)만을 남기는 제2트렌치(26)를 형성한다.Next, dry anisotropic etching of the salicide layer 22, the gate oxide layer 18, and the conductive layer 20 for the gate electrode using the third photoresist pattern 23 as a mask is performed to form a bottom portion of the first trench 16. The second trench 26 leaving only the gate oxide film 18 is formed.
이때, 상기 건식 이방성 식각공정은 다음과 같은 3단계로 실시한다.At this time, the dry anisotropic etching process is carried out in three steps as follows.
제1단계인 주식각(main etch)공정은 다음과 같은 조건으로 실시한다.The first step, the main etch process, is carried out under the following conditions.
먼저, 챔버압력은 8 ∼ 12 mTorr, 소오스 전력은 450 ∼ 550 Watt, 바이어스 전력은 100 ∼ 140 Watt, 식각가스는 80 ∼ 120 SCCM 의 HBr, 35 ∼ 45 SCCM 의 Cl2, 식각시간은 35 ∼ 45 초로 한다.First, the chamber pressure is 8 to 12 mTorr, source power is 450 to 550 Watt, bias power is 100 to 140 Watt, etching gas is HBr of 80 to 120 SCCM, Cl 2 of 35 to 45 SCCM, and etching time is 35 to 45 Do it in seconds.
제2단계인 식각종말점(end of point, EOP)의 식각은 다음과 같이 실시한다.The etching of the second end of the end point (EOP) is performed as follows.
먼저, 챔버압력은 8 ∼ 12 mTorr, 소오스 전력은 250 ∼ 350 Watt, 바이어스 전력은 35 ∼ 45 Watt, 식각가스는 80 ∼ 100 SCCM 의 HBr, 20 ∼ 40 SCCM 의 Cl2, 5 ∼ 9 SCCM 의 HeO2, 시간은 18 ∼ 24 초로 한다.First, chamber pressure is 8-12 mTorr, source power is 250-350 Watt, bias power is 35-45 Watt, etching gas is HBr of 80-100 SCCM, Cl 2 of 20-40 SCCM, HeO of 5-9 SCCM 2 , time shall be 18 to 24 seconds.
제3단계인 과도식각공정은 다음과 같은 조건으로 실시한다.The third step, the transient etching process, is carried out under the following conditions.
먼저, 챔버압력은 80 ∼ 100 mTorr, 소오스 전격은 550 ∼ 650 Watt, 바이어스 전력은 120 ∼ 180 Watt, 식각가스는 50 ∼ 70 SCCM 의 HBr, 8 ∼ 12 SCCM 의 HeO2, 식각시간은 35 ∼ 45 초로 한다.First, the chamber pressure is 80 to 100 mTorr, source electric potential is 550 to 650 Watt, bias power is 120 to 180 Watt, etching gas is HBr of 50 to 70 SCCM, HeO 2 of 8 to 12 SCCM, and etching time is 35 to 45 Do it in seconds.
도 1h를 참조하면, 상기 제3감광막패턴(23)을 마스크로 하여 상기 게이트산화막(18) 하부로 저농도의 불순물을 이온주입하여 저농도의 불순물 접합영역(28)을 형성한다.Referring to FIG. 1H, a low concentration of impurity junction region 28 is formed by ion implanting a low concentration of impurities under the gate oxide layer 18 using the third photoresist pattern 23 as a mask.
이때, 상기 이온주입공정은 BF2를 10 ∼ 20 KeV의 에너지로 5E13 ∼ 2E14 atoms/cm2만큼 주입한 것이다.At this time, in the ion implantation step, BF 2 is injected by 5E13 to 2E14 atoms / cm 2 at an energy of 10 to 20 KeV.
도 1i를 참조하면, 상기 제3감광막패턴(23)을 제거하고 상기 제2트렌치(26)를 매립하는 질화막(30)을 전체표면상부에 형성한다.Referring to FIG. 1I, the third photoresist layer pattern 23 is removed, and a nitride layer 30 filling the second trench 26 is formed on the entire surface.
이때, 상기 질화막(30)은 700 ∼ 740 ℃ 의 온도의 노(furnace) 안에서 160 ∼ 200 분 동안 NH3과 SiC2H6를 소오스로 하여 증착한다.At this time, the nitride film 30 is deposited with a source of NH 3 and SiC 2 H 6 for 160 to 200 minutes in a furnace at a temperature of 700 ~ 740 ℃.
그 다음, 상기 질화막(30)을 평탄화식각하여 상기 제2트렌치(26)를 매립하는 질화막(30) 스페이서를 형성한다.Next, the nitride layer 30 is planarized and etched to form a nitride layer 30 spacer filling the second trench 26.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 불순물 접합영역을 보다 낮게 위치하므로 종래의 소자제조 기술로는 구현할 수 없는 얕은 접합 ( shallow junction )을 형성하기 위한 공정 마진을 용이하게 확보할 수 있는 효과가 있다. 그리고, 얕은 접합을 형성하기 위한 장비상의 한계를 극복할 수 있을 뿐 아니라, LDD 형성에도 충분한 여유를 가질 수 있다.As described above, the method for forming a transistor of a semiconductor device according to the present invention has a lower impurity junction region, thereby facilitating a process margin for forming a shallow junction that cannot be realized by conventional device fabrication techniques. There is an effect that can be secured. In addition, it is possible not only to overcome the equipment limitations for forming the shallow junction, but also have sufficient margin for forming the LDD.
또한 0.15㎛ 기술 이하의 소자에서 발생하는 단채널효과 및 HCE(hot carrier effect), 불순물 접합영역의 펀치스루 문제 등을 해소할 수 있으며, 누설전류를 감소시키고 동작전류 대 오프전류 마진을 향상시킬 수 있을 뿐 아니라 접합깊이를 자유롭게 조절함으로써 원하는 접합의 면저항값을 용이하게 얻을 수 있는 효과가 있다.In addition, short channel effects, HCE (hot carrier effect) and impurity junction punch-through problems that occur in devices below 0.15㎛ technology can be solved, and leakage current can be reduced and operating current vs. off current margin can be improved. In addition, by controlling the junction depth freely, there is an effect that can easily obtain the sheet resistance value of the desired junction.
Claims (16)
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| KR20030047034A KR20030047034A (en) | 2003-06-18 |
| KR100440070B1 true KR100440070B1 (en) | 2004-07-14 |
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| KR10-2001-0077409A KR100440070B1 (en) | 2001-12-07 | 2001-12-07 | A method for forming a transistor of a semiconductor device |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0684942A (en) * | 1992-08-31 | 1994-03-25 | Sanyo Electric Co Ltd | Semiconductor device |
| JPH06169088A (en) * | 1992-08-05 | 1994-06-14 | Philips Electron Nv | Semiconductor device and its manufacture |
| JPH07106560A (en) * | 1993-09-29 | 1995-04-21 | Ricoh Co Ltd | Groove type semiconductor device and manufacture of the same |
| US5453635A (en) * | 1994-08-23 | 1995-09-26 | United Microelectronics Corp. | Lightly doped drain transistor device having the polysilicon sidewall spacers |
| KR100200757B1 (en) * | 1996-11-18 | 1999-06-15 | 윤종용 | Semiconductor device and manufacturing method thereof |
| KR19990069063A (en) * | 1998-02-04 | 1999-09-06 | 김규현 | Morse transistor and its manufacturing method using trench gate structure |
-
2001
- 2001-12-07 KR KR10-2001-0077409A patent/KR100440070B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06169088A (en) * | 1992-08-05 | 1994-06-14 | Philips Electron Nv | Semiconductor device and its manufacture |
| JPH0684942A (en) * | 1992-08-31 | 1994-03-25 | Sanyo Electric Co Ltd | Semiconductor device |
| JPH07106560A (en) * | 1993-09-29 | 1995-04-21 | Ricoh Co Ltd | Groove type semiconductor device and manufacture of the same |
| US5453635A (en) * | 1994-08-23 | 1995-09-26 | United Microelectronics Corp. | Lightly doped drain transistor device having the polysilicon sidewall spacers |
| KR100200757B1 (en) * | 1996-11-18 | 1999-06-15 | 윤종용 | Semiconductor device and manufacturing method thereof |
| KR19990069063A (en) * | 1998-02-04 | 1999-09-06 | 김규현 | Morse transistor and its manufacturing method using trench gate structure |
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| Publication number | Publication date |
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| KR20030047034A (en) | 2003-06-18 |
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