KR100435784B1 - Fabricating method of metal wire in semiconductor device - Google Patents
Fabricating method of metal wire in semiconductor device Download PDFInfo
- Publication number
- KR100435784B1 KR100435784B1 KR10-2001-0082948A KR20010082948A KR100435784B1 KR 100435784 B1 KR100435784 B1 KR 100435784B1 KR 20010082948 A KR20010082948 A KR 20010082948A KR 100435784 B1 KR100435784 B1 KR 100435784B1
- Authority
- KR
- South Korea
- Prior art keywords
- diffusion barrier
- forming
- metal wiring
- via contact
- trench
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 비아 콘택홀(via contact hole)과 트렌치(trench)를 갖는 듀얼 다마신 패턴(dual damascene pattern) 형성 공정을 개선하여, 금속 배선 형성 공정의 안정성 확보와 웨이퍼 전면의 균일성(uniformity)을 개선시킬 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것으로서, 본 발명의 반도체 소자의 금속배선 형성 방법은 반도체 기판 상에 층간절연막을 적층하는 단계;와, 상기 층간절연막의 소정 부위를 선택적으로 식각하여 트렌치 및 비아 콘택홀을 형성하는 단계;와, 상기 트렌치 및 비아 콘택홀을 포함한 기판 전면 상에 확산 방지막을 형성하는 단계;와, 상기 트렌치 및 비아 콘택홀을 충분히 채우도록 상기 확산 방지막 상에 금속 배선용 물질을 매립하는 단계;와, 상기 금속 배선용 물질 및 확산 방지막을 화학기계적연마 공정을 이용하여 평탄화하되, 상기 확산 방지막의 전체 두께의 1/3 정도 두께를 연마하는 단계;와, 상기 연마된 확산 방지막을 포함한 기판 전면 상에 박막의 금속층을 형성하는 단계;와, 상기 층간절연막이 노출되도록 상기 박막의 금속층 및 상기 확산 방지막을 재연마하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention improves the process of forming a dual damascene pattern having via contact holes and trenches, thereby ensuring the stability of the metal wiring forming process and the uniformity of the entire surface of the wafer. A method of forming a metal wiring of a semiconductor device that can be improved, the method of forming a metal wiring of a semiconductor device of the present invention comprises the steps of: laminating an interlayer insulating film on a semiconductor substrate; and selectively etching a predetermined portion of the interlayer insulating film Forming a trench and via contact hole; and forming a diffusion barrier on the entire surface of the substrate including the trench and via contact hole; and for forming a metal wiring on the diffusion barrier to sufficiently fill the trench and via contact hole. Embedding the material; and planarizing the metallization material and the diffusion barrier layer using a chemical mechanical polishing process, wherein Polishing a thickness of about one third of the total thickness of the diffusion barrier layer; and forming a metal layer of the thin film on the entire surface of the substrate including the polished diffusion barrier layer; and the metal layer of the thin film to expose the interlayer dielectric layer; And regrinding the diffusion barrier.
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로서, 특히 비아 콘택홀(via contact hole)과 트렌치(trench)를 갖는 듀얼 다마신 패턴(dual damascene pattern) 형성 공정을 개선하여, 금속 배선 형성 공정의 안정성 확보와웨이퍼 전면의 균일성(uniformity)을 개선시킬 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, to improve a process of forming a dual damascene pattern having via contact holes and trenches. The present invention relates to a method for forming metal wirings in a semiconductor device capable of securing stability and improving uniformity of a front surface of a wafer.
일반적으로, 반도체 소자 형성 공정중 금속배선은 구리, 알루미늄, 텅스텐과 같은 고전도성 물질을 증착한 후, 포토리소그래피(Photo lithography) 공정 및 식각 공정에 의해 형성된다.In general, the metallization is formed by a photolithography process and an etching process after depositing a highly conductive material such as copper, aluminum, and tungsten.
이 경우 반도체 소자가 고집적화 및 소형화되어감에 따라 감광막의 애스펙트 비(aspect ratio)가 높아져 감광막 패턴이 쓰러지거나, 건식 식각 후에 부식(corrosion) 발생 가능성 등의 문제점이 있었다. 또한, 금속 배선 재료가 바뀔 때마다 새로운 식각 레시피를 개발해야 하는 번거로움이 있고, 특히 구리(Cu)는 휘발성이 낮은 화합물을 형성하므로 건식 식각이 어렵다. 이러한 문제를 해결하기 위해 최근 개발된 방법으로 싱글 다마신(single damascene) 공정을 개선한 듀얼 다마신 공정이 있다.In this case, as the semiconductor device is highly integrated and miniaturized, the aspect ratio of the photoresist film is increased, so that the photoresist pattern may collapse, or corrosion may occur after dry etching. In addition, it is cumbersome to develop a new etching recipe every time the metal wiring material is changed, and in particular, copper (Cu) forms a low volatility compound, making dry etching difficult. To solve this problem, a recently developed method is a dual damascene process which improves on a single damascene process.
이러한 듀얼 다마신 공정을 이용한 금속배선 형성 방법을 설명하면 다음과 같다.Referring to the metallization method using the dual damascene process as follows.
도 1 내지 3은 종래의 일반적인 듀얼 다마신 공정을 이용한 금속배선 형성 방법을 설명하기 위한 공정단면도이다.1 to 3 is a cross-sectional view illustrating a method for forming metal wiring using a conventional dual damascene process.
먼저, 도 1에 도시한 바와 같이, 기판(101) 상에 제 1 층간절연막(102) 및 에치 스토퍼(etch stopper)(103)를 차례로 형성한 다음, 포토리소그래피 공정 및 식각 공정으로 상기 제 1 층간절연막(102) 및 에치 스토퍼(103)의 소정 부위를 식각하여 기판이 노출되는 비아 콘택홀(via contact hole)(104)을 형성한다. 이어,상기 비아 콘택홀(104)을 포함한 상기 에치 스토퍼 상에 포토레지스트 물질을 도포한 후 선택적으로 패터닝하여 포토레지스트 패턴(105)을 형성한다.First, as shown in FIG. 1, a first interlayer insulating film 102 and an etch stopper 103 are sequentially formed on the substrate 101, and then the first interlayer is formed by a photolithography process and an etching process. Predetermined portions of the insulating layer 102 and the etch stopper 103 are etched to form via contact holes 104 through which the substrate is exposed. Next, a photoresist material is coated on the etch stopper including the via contact hole 104 and then selectively patterned to form a photoresist pattern 105.
여기서, 상기 기판(101)은 웰(well) 및 접합부가 형성된 반도체 기판이거나, 다층 금속 배선 구조에서 하부 금속 배선이거나, 반도체 소자의 전극으로 사용되는 도전성 패턴을 포함하고 있다.The substrate 101 may include a semiconductor substrate having wells and junctions, a lower metal wiring in a multilayer metal wiring structure, or a conductive pattern used as an electrode of a semiconductor device.
도 2에 도시한 바와 같이, 상기 포토레지스트 패턴(105)을 포함한 기판 전면에 극저온의 산화막을 증착하여 제 2 층간절연막(106)을 형성한다. 이어, 상기 포토레지스트 패턴의 상부가 노출되도록 화학 기계적 연마(Chemical Mechanical Polishing, 이하, CMP) 공정으로 상기 포토레지스트 패턴(105) 및 제 2 층간절연막(106)을 연마한다.As shown in FIG. 2, a cryogenic oxide film is deposited on the entire surface of the substrate including the photoresist pattern 105 to form a second interlayer insulating film 106. Subsequently, the photoresist pattern 105 and the second interlayer insulating layer 106 are polished by chemical mechanical polishing (CMP) to expose the upper portion of the photoresist pattern.
마지막으로, 도 3에 도시한 바와 같이, 상기 노출된 포토레지스터 패턴(105)을 식각, 제거하여 트렌치(107)를 형성하고, 이로 인하여 최초 형성된 비아 콘택홀(104)과 함께 듀얼 다마신 패턴이 완성된다. 이어, 상기 비아 콘택홀(104)과 트렌치(107)로 이루어진 듀얼 다마신 패턴을 포함한 상기 제 2 층간절연막(106) 상에 확산 방지막(108)을 형성한 후, 상기 확산 방지막(108) 상에 금속층을 증착한 후 CMP 공정으로 듀얼 다마신 패턴 내에 금속배선(109)을 형성한다(도 4 참조).Finally, as shown in FIG. 3, the exposed photoresist pattern 105 is etched and removed to form a trench 107, whereby a dual damascene pattern is formed together with the first via contact hole 104. Is completed. Subsequently, after the diffusion barrier 108 is formed on the second interlayer insulating layer 106 including the dual damascene pattern formed of the via contact hole 104 and the trench 107, the diffusion barrier 108 is formed on the diffusion barrier 108. After depositing the metal layer, the metal wiring 109 is formed in the dual damascene pattern by the CMP process (see FIG. 4).
이 때, 상기 확산 방지막으로 주로 탄탈륨 질화물(TaN)이 사용되며 금속배선 용 물질로는 구리(Cu)가 쓰인다.At this time, tantalum nitride (TaN) is mainly used as the diffusion barrier and copper (Cu) is used as a material for metal wiring.
그러나, 종래 기술에 따른 반도체 소자의 금속배선 형성 방법은 다음과 같은문제점이 있었다.However, the metal wiring formation method of the semiconductor device according to the prior art has the following problems.
금속배선 물질을 비아 콘택홀 및 트렌치에 채운 후, CMP 공정을 수행할 때 금속배선용 물질인 구리와 확산방지막 재료인 탄탈륨 질화물은 슬러리(slurry)와 CMP의 연마력에 영향을 받게 된다. 즉, 구리와 탄탈륨 질화물은 기계적 강도의 차이가 있기 때문에 연마속도가 틀리게 되고 그에 따라 트렌치 부분에 침식(erosion) 등의 현상이 발생하게 된다(도 4 참조, 도면부호 110). 또한, 슬러리와 구리와의 화학적 반응에 의해 부식(corrosion)이 발생하여 막(layer)을 중첩시킴에 따라 웨이퍼 전면의 균일성(uniformity)이 크게 떨어지게 되고 그 결과 금속배선의 전기적 특성에도 큰 영향을 미친다.After the metal wiring material is filled in the via contact hole and the trench, when the CMP process is performed, copper, which is a metal wiring material, and tantalum nitride, which is a diffusion barrier material, are affected by the slurry and the polishing force of the CMP. That is, since copper and tantalum nitride have a difference in mechanical strength, the polishing rate is incorrect, and thus erosion and the like occur in the trench portion (see FIG. 4 and reference numeral 110). In addition, due to the chemical reaction between the slurry and copper, corrosion occurs and the layers overlap, resulting in a large drop in the uniformity of the front surface of the wafer, which in turn affects the electrical properties of the metallization. Crazy
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서, 기계적 강도가 상이한 확산방지막과 금속배선용 물질의 CMP 공정 수행시 기판의 안정적인 균일성을 담보할 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, to provide a method for forming a metal wiring of a semiconductor device that can ensure a stable uniformity of the substrate when performing the CMP process of the diffusion barrier film and the metal wiring material having different mechanical strength. There is a purpose.
도 1 내지 4는 종래의 일반적인 듀얼 다마신 공정을 이용한 금속배선 형성 방법을 설명하기 위한 공정단면도1 to 4 is a process cross-sectional view for explaining a metal wiring forming method using a conventional general dual damascene process
도 5 내지 8은 본 발명의 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도.5 to 8 is a cross-sectional view for explaining a method for forming a metal wiring of the semiconductor device of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
201 : 기판 202 : 제 1 층간절연막201: substrate 202: first interlayer insulating film
203 : 에치 스토퍼(Etch stopper) 204 : 제 2 층간절연막203: Etch stopper 204: Second interlayer insulating film
207 : 확산 방지막 208 : 금선배선용 물질207: diffusion barrier 208: gold wiring material
209 : 박막의 금속층209: thin metal layer
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선 형성 방법은 반도체 기판 상에 층간절연막을 적층하는 단계;와, 상기 층간절연막의 소정 부위를 선택적으로 식각하여 트렌치 및 비아 콘택홀을 형성하는 단계;와, 상기 트렌치 및 비아 콘택홀을 포함한 기판 전면 상에 확산 방지막을 형성하는 단계;와, 상기 트렌치 및 비아 콘택홀을 충분히 채우도록 상기 확산 방지막 상에 금속 배선용 물질을 매립하는 단계;와, 상기 금속 배선용 물질 및 확산 방지막을 화학기계적연마 공정을 이용하여 평탄화하되, 상기 확산 방지막의 전체 두께의 1/3 정도 두께를 연마하는 단계;와, 상기 연마된 확산 방지막을 포함한 기판 전면 상에 박막의 금속층을 형성하는 단계;와, 상기 층간절연막이 노출되도록 상기 박막의 금속층 및 상기 확산 방지막을 재연마하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal interconnection of a semiconductor device, the method comprising: laminating an interlayer insulating film on a semiconductor substrate; and selectively etching a predetermined portion of the interlayer insulating film to form trenches and via contact holes. And forming a diffusion barrier on the entire surface of the substrate including the trench and the via contact hole, and filling a metal wiring material on the diffusion barrier to fill the trench and the via contact hole. Planarizing the metallization material and the diffusion barrier using a chemical mechanical polishing process, and polishing a thickness of about 1/3 of the total thickness of the diffusion barrier; and a thin film on the entire surface of the substrate including the polished diffusion barrier Forming a metal layer of the thin film; and reposing the metal layer and the diffusion barrier of the thin film to expose the interlayer insulating layer. It characterized in that it comprises a step of polishing.
여기서, 상기 박막의 금속층은 텅스텐으로 이루어지는 것을 특징으로 하며, 상기 트렌치 영역의 금속배선 상단에는 박막의 텅스텐이 남아 있는 것을 특징으로 한다.The metal layer of the thin film may be formed of tungsten, and the tungsten of the thin film may remain on the upper end of the metal wiring of the trench region.
본 발명에 따른 반도체 소자의 금속배선 형성 방법은 CMP 공정 수행 후의 기판 표면의 균일성 문제가 개선되어 금속배선의 전기적 특성이 향상되는 작용을 한다.The metallization method of the semiconductor device according to the present invention improves the uniformity problem of the substrate surface after performing the CMP process, thereby improving the electrical characteristics of the metallization.
이하, 도면을 참조하여 본 발명의 반도체 소자의 금속배선 형성 방법을 상세히 설명하기로 한다.Hereinafter, a method of forming metal wirings of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 5 내지 8은 본 발명의 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도이다.5 to 8 are process cross-sectional views for explaining a method for forming metal wirings of a semiconductor device of the present invention.
참고로, 본 발명은 비아 콘택홀과 트렌치가 형성되는 듀얼 다마신 공정을 이용하며 상기 듀얼 다마신 공정은 종래의 방법을 그래도 이용하기 때문에 본 발명에서는 그에 대한 상세한 설명은 생략한다.For reference, the present invention uses a dual damascene process in which a via contact hole and a trench are formed, and since the dual damascene process still uses a conventional method, detailed description thereof will be omitted.
먼저, 도 5에 도시한 바와 같이, 일련의 듀얼 다마신 공정을 이용하여 형성된 비아 콘택홀(205)과 트렌치 구조(206)를 갖으며 제 1 및 제 2 층간절연막(202, 204)을 구비하는 반도체 소자의 금속 배선 형성 방법에 있어서, 상기 비아콘택홀(205)과 트렌치(206)를 포함한 제 2 층간 절연막(204) 상에 확산 방지막(207)을 스퍼터링(sputtering) 방법을 이용하여 형성한다.First, as shown in FIG. 5, a via contact hole 205 and a trench structure 206 formed using a series of dual damascene processes are provided, and the first and second interlayer insulating films 202 and 204 are provided. In the method for forming a metal wiring of a semiconductor device, a diffusion barrier film 207 is formed on the second interlayer insulating film 204 including the via contact hole 205 and the trench 206 by a sputtering method.
여기서, 상기 확산 방지막(207)의 재료로는 탄탈륨 질화물(TaN)이 주로 쓰인다.Here, tantalum nitride (TaN) is mainly used as a material of the diffusion barrier 207.
이어, 상기 비아 콘택홀과 트렌치를 충분히 채워지도록 상기 확산 방지막 상에 금속배선용 물질(208)을 증착한다. 이 때, 상기 금속배선용 물질(208)로는 구리(Cu)가 사용되며 화학기상증착(CVD) 또는 물리기상증착법(PVD)을 이용하여 증착한다.Subsequently, a metal wiring material 208 is deposited on the diffusion barrier layer so as to sufficiently fill the via contact hole and the trench. At this time, copper (Cu) is used as the metal wiring material 208 and is deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD).
도 6에 도시한 바와 같이, 기판 표면의 균일성을 담보하기 위해 상기 금속배선용 물질(208)을 CMP(Chemical Mechanical Polishing) 공정을 이용하여 연마한다. 이 때, 상기 CMP를 이용한 연마는 제 2 층간절연막(204) 상에 형성되어 있는 확산 방지막(207)의 1/3 정도의 두께가 제거될 때 한다.As shown in FIG. 6, the metal wiring material 208 is polished using a chemical mechanical polishing (CMP) process to ensure uniformity of the substrate surface. At this time, the polishing using the CMP is performed when the thickness of about one third of the diffusion barrier film 207 formed on the second interlayer insulating film 204 is removed.
상기와 같이 CMP 공정을 이용한 연마공정을 수행하면, 확산 방지막인 탄탈륨 질화물(TaN)과 금속배선용 물질인 구리가 서로 기계적 강도가 다르기 때문에 연마되는 속도의 차이가 생겨 결과적으로 연마 두께의 차이가 발생하게 된다.When the polishing process using the CMP process is performed as described above, since the diffusion barrier film, tantalum nitride (TaN) and copper, which is a metal wiring material, have different mechanical strengths, there is a difference in polishing rate, resulting in a difference in polishing thickness. do.
이에 따라, 도 6에 도시된 바와 같이 트렌치 부분의 금속배선용 물질(208)이 제 2 층간절연막(204) 상의 확산 방지막(207)보다 더 연마되어 있음을 알 수 있다.Accordingly, as shown in FIG. 6, it can be seen that the metal wiring material 208 of the trench portion is polished more than the diffusion barrier film 207 on the second interlayer insulating film 204.
이어, 도 7에 도시한 바와 같이, 상기 연마된 확산 방지막(207)을 포함한 기판 전면상에 박막의 금속층(209)을 증착하여 상기 트렌치 영역의 과(過)연마된 부위를 충분히 채워지도록 한다. 여기서 상기 박막의 금속층(209)은 텅스텐(W)이 주로 사용된다.Subsequently, as shown in FIG. 7, a thin metal layer 209 is deposited on the entire surface of the substrate including the polished diffusion barrier layer 207 to sufficiently fill the over-polishing portion of the trench region. Herein, tungsten (W) is mainly used as the thin metal layer 209.
마지막으로, 도 8에 도시한 바와 같이, 상기 제 2 층간절연막(204)이 드러나도록 상기 박막의 금속층(209)과 확산 방지막(207)을 재연마하여 제거하면 본 발명의 반도체 소자의 금속배선 형성 방법은 완료된다.Finally, as shown in FIG. 8, when the metal layer 209 and the diffusion barrier 207 of the thin film are repolished and removed so that the second interlayer insulating film 204 is exposed, metal wiring of the semiconductor device of the present invention is formed. The method is complete.
한편, 상기 박막의 금속층의 재료로서 텅스텐이 사용되는 이유는 도 8의 재연마 공정시 동일 속도의 연마 속도를 갖도록 하기 위함이며, 따라서, 본 발명에 사용된 텅스텐 이외에도 상기 확산 방지막과 동일한 연마 속도를 가질 수 있는 기계적 강도를 갖는 재료라면 그 적용이 가능하다.Meanwhile, the reason why tungsten is used as a material of the metal layer of the thin film is to have the same polishing rate in the regrinding process of FIG. 8, and therefore, in addition to tungsten used in the present invention, The application is possible as long as the material has a mechanical strength that can have.
상술한 바와 같은 본 발명의 반도체 소자의 금속배선 형성 방법은 다음과 같은 효과가 있다.The metal wiring forming method of the semiconductor device of the present invention as described above has the following effects.
금속배선용 물질을 매립한 후의 CMP 공정을 거친 다음, 소정의 금속층을 증착하여 재연마함으로써 기판 표면의 균일성을 향상시킬 수 있으며, 이에 따라 종래 발생하던 슬러리와 금속배선 물질의 화학적 반응에 따른 부식 또는 확산 방지막과 금속배선용 물질의 기계적 강도 차이에 따른 침식의 문제점을 해결할 수 있는 장점이 있다.After embedding the metal wiring material through the CMP process, by depositing a predetermined metal layer and regrinding, it is possible to improve the uniformity of the surface of the substrate, and thus corrosion or corrosion caused by the chemical reaction between the slurry and the metal wiring material There is an advantage that can solve the problem of erosion according to the mechanical strength difference between the diffusion barrier and the metal wiring material.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0082948A KR100435784B1 (en) | 2001-12-21 | 2001-12-21 | Fabricating method of metal wire in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0082948A KR100435784B1 (en) | 2001-12-21 | 2001-12-21 | Fabricating method of metal wire in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030052832A KR20030052832A (en) | 2003-06-27 |
| KR100435784B1 true KR100435784B1 (en) | 2004-06-12 |
Family
ID=29577574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0082948A KR100435784B1 (en) | 2001-12-21 | 2001-12-21 | Fabricating method of metal wire in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100435784B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR980005575A (en) * | 1996-06-28 | 1998-03-30 | 김주용 | Method of forming plug of semiconductor device |
| EP0881673A2 (en) * | 1997-05-30 | 1998-12-02 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
| US6017803A (en) * | 1998-06-24 | 2000-01-25 | Chartered Semiconductor Manufacturing, Ltd. | Method to prevent dishing in chemical mechanical polishing |
| US6251786B1 (en) * | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
| US6323554B1 (en) * | 1992-02-26 | 2001-11-27 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD |
-
2001
- 2001-12-21 KR KR10-2001-0082948A patent/KR100435784B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323554B1 (en) * | 1992-02-26 | 2001-11-27 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD |
| KR980005575A (en) * | 1996-06-28 | 1998-03-30 | 김주용 | Method of forming plug of semiconductor device |
| EP0881673A2 (en) * | 1997-05-30 | 1998-12-02 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
| US6017803A (en) * | 1998-06-24 | 2000-01-25 | Chartered Semiconductor Manufacturing, Ltd. | Method to prevent dishing in chemical mechanical polishing |
| US6251786B1 (en) * | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030052832A (en) | 2003-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100442474C (en) | Method of manufacturing semiconductor device | |
| EP1869700B1 (en) | Interconnect structure and method of fabrication of same | |
| US20030139034A1 (en) | Dual damascene structure and method of making same | |
| KR20030053055A (en) | A mask layer and dual damascene interconnect structure in a semiconductor device | |
| KR20030027817A (en) | Mask layer and interconnect structure for dual damascene semiconductor manufacturing | |
| US6406992B1 (en) | Fabrication method for a dual damascene structure | |
| US20050266679A1 (en) | Barrier structure for semiconductor devices | |
| JP2003508896A (en) | Method of manufacturing an integrated circuit having at least one metallization surface | |
| KR100482179B1 (en) | Fabricating method of semiconductor device | |
| KR100419021B1 (en) | Method of fabricating Copper line of semiconductor device | |
| US6204096B1 (en) | Method for reducing critical dimension of dual damascene process using spin-on-glass process | |
| US6913990B2 (en) | Method of forming isolation dummy fill structures | |
| US20060094220A1 (en) | Methods of forming a metal line in a semiconductor device | |
| US20020127849A1 (en) | Method of manufacturing dual damascene structure | |
| KR20020056010A (en) | method for forming metal line of semiconductor device | |
| KR100435784B1 (en) | Fabricating method of metal wire in semiconductor device | |
| US6977216B2 (en) | Method for forming metal wire in semiconductor device | |
| US7279415B2 (en) | Method for forming a metallization layer stack to reduce the roughness of metal lines | |
| US7662711B2 (en) | Method of forming dual damascene pattern | |
| US7112537B2 (en) | Method of fabricating interconnection structure of semiconductor device | |
| KR20090024854A (en) | Metal line and method for fabricating metal line of semiconductor device | |
| KR20070052452A (en) | Method of manufacturing metalline of semiconductor device | |
| KR100955838B1 (en) | Semiconductor device and method for forming metal line in the same | |
| KR100784105B1 (en) | Method of manufacturing a semiconductor device | |
| KR100579856B1 (en) | Metal line formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100518 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |