KR100434136B1 - Plc system including a flash memory a cpu - Google Patents

Plc system including a flash memory a cpu Download PDF

Info

Publication number
KR100434136B1
KR100434136B1 KR1019970037780A KR19970037780A KR100434136B1 KR 100434136 B1 KR100434136 B1 KR 100434136B1 KR 1019970037780 A KR1019970037780 A KR 1019970037780A KR 19970037780 A KR19970037780 A KR 19970037780A KR 100434136 B1 KR100434136 B1 KR 100434136B1
Authority
KR
South Korea
Prior art keywords
program
flash memory
control program
control
plc system
Prior art date
Application number
KR1019970037780A
Other languages
Korean (ko)
Other versions
KR19990015591A (en
Inventor
양성운
Original Assignee
엘지산전 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지산전 주식회사 filed Critical 엘지산전 주식회사
Priority to KR1019970037780A priority Critical patent/KR100434136B1/en
Publication of KR19990015591A publication Critical patent/KR19990015591A/en
Application granted granted Critical
Publication of KR100434136B1 publication Critical patent/KR100434136B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/056—Programming the PLC
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13084—Rom or eprom with conditional instructions
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13161—Easily exchangable rom, eprom cassette, earom
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15018—Communication, serial data transmission, modem

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: A PLC system is provided, which changes an OS program of the PLC system rapidly and also reduces time and cost required in changing the OS program. CONSTITUTION: According to the PLC system, a flash memory(30) stores a boot ROM program in an area which is performed at first after a power is turned on, and stores a control program of the PLC system in another area. And a CPU(24) stores the control program received with serial communication by performing the boot ROM program when changing the control program in a control program area of the flash memory.

Description

피엘씨장치PD device

본 발명은 피엘씨장치에 관한 것으로, 특히 오/에스 메모리를 플래시메모리를 사용하여 변경할 프로그램을 메모리 교체없이 수정할 수 있게 한 피엘씨장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLC device, and more particularly, to a PLC device capable of modifying a program to be modified using an O / S memory using a flash memory without replacing the memory.

피엘씨장치는 사용자가 작성한 프로그램을 반복 수행하여 제어대상을 제어하는 것으로서 일반적으로 마이크로프로세서를 사용하여 수행한다.The PLC device repeatedly executes a program written by a user to control a control object, and is generally performed by using a microprocessor.

도1은 종래 피엘씨장치의 블록구성도로서, 이에 도시된 바와같이교류전원(AC)을 입력받아 이를 직류전원(DC)으로 변환하여 출력하는 전원부(10)와; 상기 전원부(10)의 직류전원(DC)에 의해 동작되어 제어대상(14)의 상태를 입력받는 입력부(11)와; 상기 입력부(11)를 통해 제어대상(14)의 상태를 읽어들인후 사용자가 작성한 프로그램을 수행하는 씨피유(12)와; 상기 씨피유(12)의 제어신호를 출력하는 출력부(13)로 구성된다.1 is a block diagram of a conventional PLC device, and as shown therein, a power supply unit 10 for receiving an AC power supply and converting it into a DC power supply DC; An input unit 11 operated by a direct current power source DC of the power source unit 10 to receive a state of the control object 14; A CPI 12 that reads the state of the control object 14 through the input unit 11 and executes a program written by a user; The output unit 13 for outputting the control signal of the CPI (12).

도 2는 상기 씨피유(12)의 내부 블록구성도로서, 이에 도시된 바와같이 오/에스 프로그램이 저장되는 이피롬(20)과; 사용자가 작성한 프로그램과 운전데이터가 저장되는 에스램(21)과; 제어대상(14)의 제어상태를 입력단(22)을 통해 읽어들인후 상기 이피롬(20) 또는 상기 에스램(21)에 저장된 데이터를 입력받아 그에 해당되는 프로그램을 수행하여 출력단(23)을 통하여 제어신호를 출력하는 마이크로프로세서(24)로 구성되며, 이와같이 구성된 종래 피엘씨 장치의 동작을 설명한다.FIG. 2 is an internal block diagram of the CPI 12, and as shown therein, an EPI ROM 20 in which an O / S program is stored; An SRAM 21 in which a user-written program and operation data are stored; After reading the control state of the control target 14 through the input terminal 22, and receives the data stored in the pyramid 20 or the SRAM 21, and performs the corresponding program through the output terminal 23 The operation of the conventional PLC device, which is composed of a microprocessor 24 for outputting a control signal, is described.

먼저, 전원부(10)는 교류전원(AC)을 입력받아 이를 직류전원(DC)으로 변환하여 출력하고, 이때 씨피유(12)는 상기 전원부(10)의 직류전원(DC)에 의해 동작되어 제어대상(14)의 상태를 입력부(11)를 통하여 읽어들이고 사용자가 작성한 프로그램을 수행한다.First, the power supply unit 10 receives an AC power source (AC) and converts it to a DC power source (DC) and outputs it, and at this time, the CPI 12 is operated by the DC power source (DC) of the power source unit 10 to be controlled. The state of (14) is read through the input unit 11, and a user-written program is executed.

이후, 상기 씨피유(12)는 제어신호를 출력부(13)를 통해 제어대상(14)에 출력하게 된다.Thereafter, the CPI 12 outputs a control signal to the control object 14 through the output unit 13.

이와같은 방법으로 피엘씨장치는 제어대상(14)을 제어하는데 있어서 마이크로프로세서(24)를 사용하여 구현하며, 이때 상기 마이크로프로세서(24)가 해야 할 일들은 이피롬(20)에 저장되어 있다.In this way, the PLC device is implemented using the microprocessor 24 to control the control target 14, wherein the work to be done by the microprocessor 24 is stored in the pyrom 20.

그러나 상기와 같이 동작하는 종래 장치는 출하된 피엘씨장치의 오/에스 프로그램 변경시에는 상기 피엘씨장치가 운전중인 장소를 방문하여 변경된 이피롬으로 교체하여야만 하기 때문에 신속한 교체가 불가능하고 또한 교체에 많은 시간과 비용이 필요한 문제점이 있었다.However, in the conventional device operating as described above, when the O / S program of the shipped PLC device is changed, the PLC device needs to visit the place where it is operating and replace it with a modified Ipyrom, so that it is impossible to replace it quickly, There was a problem that required time and money.

따라서, 본 발명은 변경된 오/에스 프로그램을 직렬통신으로 직접 변경할 수 있도록하여 피엘씨장치의 오/에스 프로그램을 신속하게 변경할 수 있도록 하고 아울러 변경에 필요한 많은 시간과 비용을 줄일 수 있도록 한 피엘씨장치를 제공함에 그 목적이 있다.Accordingly, the present invention enables a P / S program to be changed directly by serial communication so that the P / S program of the P / C device can be quickly changed, and also a time and cost required for the change can be reduced. The purpose is to provide.

도 1은 종래 피엘씨장치의 블록 구성도.1 is a block diagram of a conventional PLC device.

도 2는 도1에 있어서, 씨피유의 블록 구성도.FIG. 2 is a block diagram of CPI in FIG. 1; FIG.

도 3은 본 발명에 있어서, 씨피유의 블록 구성도.Figure 3 is a block diagram of a CFI oil in the present invention.

*****도면의 주요부분에 대한 부호의 설명********** Description of the symbols for the main parts of the drawings *****

21:에스램 22: 입력단21: SRAM 22: Input terminal

23:출력단 24:마이크로프로세서23: output stage 24: microprocessor

30:플래시메모리30: flash memory

상기와 같은 목적은 전원이 온된후 최초 수행되는 영역에 부트롬 프로그램을 저장하고, 다른 영역에 피엘씨 장치의 제어프로그램을 저장하는 플래시 메모리와; 제어 프로그램 변경시 상기 부트롬 프로그램을 수행하여 직렬통신으로 수신한 제어 프로그램을 상기 플래시 메모리의 제어 프로그램 영역에 저장하는 씨피유를 포함하여 구성함으로써 달성되는 것으로, 이와 같은 본 발명의 동작을 설명한다.The above object includes a flash memory for storing a boot ROM program in a region which is initially performed after power is turned on, and a control program of a PLC device in another region; When the control program is changed, this is achieved by including the CPU to store the control program received in the serial communication by executing the boot ROM program in the control program area of the flash memory. The operation of the present invention will be described.

본 발명의 구성은 종래 장치의 블록 구성도인 도1과 동일하고, 다만 도3과 같이 씨피유(12)의 내부에 이피롬(20) 대신에 플래시메모리(30)를 사용한 것만이 다르며, 이와같이 구성된 본 발명의 동작을 설명하면 다음과 같다.The configuration of the present invention is the same as that of FIG. 1, which is a block diagram of a conventional apparatus, except that the flash memory 30 is used instead of the pyromium 20 as shown in FIG. The operation of the present invention will be described as follows.

먼저, 전원부(10)는 교류전원(AC)을 입력받아 직류전원(DC)을 씨피유(12)와 입력부(11) 및 출력부(13)에 공급하며, 이때 씨피유(12)는 제어하는 제어대상(14)의 상태를 입력부(11)를 통하여 읽어들이고 플래시메모리(30)에 저장된 프로그램을 수행한 후 출력부(13)를 통하여 제어신호를 출력하게 된다.First, the power supply unit 10 receives an AC power source AC and supplies a DC power source DC to the CPI 12, the input unit 11, and the output unit 13, where the CPI 12 is controlled. The state of (14) is read through the input unit 11, a program stored in the flash memory 30 is executed, and then a control signal is output through the output unit 13.

이와같은 일련의 제어는 상기 씨피유(12)의 마이크로프로세서(24)를 사용하여 구현하며, 이때 마이크로프로세서(24)가 해야 할 일들은 플래시메모리(30)에 저장되어 있다.This series of control is implemented using the microprocessor 24 of the CPI 12, where the work of the microprocessor 24 is stored in the flash memory 30.

여기서, 상기 씨피유(12)의 플래시메모리(30)는 영역별로 저장된 데이터를 지울 수가 있으므로 마이크로프로세서(24)가 전원이 온된후 최초 수행되는 영역에 부트롬 프로그램이 위치하고 다른 영역에는 피엘씨장치의 제어 프로그램이 위치한다.In this case, the flash memory 30 of the CPI 12 can erase data stored for each area, so that a boot ROM program is located in an area where the microprocessor 24 is first performed after the power is turned on, and a control program of a PLC device is located in another area. This is located.

이때, 전원이 온되면 마이크로프로세서(24)는 부트롬 프로그램을 수행하여 시스템을 초기화 하고 피엘씨장치의 제어 프로그램이 정상인지를 확인하여 정상이면 피엘씨장치의 제어프로그램을 반복 수행하며 제어대상(14)을 제어한다.At this time, when the power is turned on, the microprocessor 24 performs a boot ROM program to initialize the system and checks whether the control program of the PLC device is normal. If the control is normal, the microprocessor 24 repeatedly performs the control program of the PLC device. To control.

만약, 운전중에 상기 피엘씨장치의 오/에스 프로그램을 변경하려면 피엘씨장치에 새로운 오/에스 프로그램으로 변경하겠다는 명령을 하면 마이크로프로세서(24)는 반복 수행하던 제어 프로그램의 수행을 중지하고 부트롬 프로그램을 수행하며 아울러 직렬통신을 통하여 변경된 오/에스 프로그램을 피엘씨장치의 제어프로그램 영역에 저장하게 된다.If the O / S program of the PLC device is changed during operation, if the command to change the P / S device to a new O / S program is executed, the microprocessor 24 stops executing the control program that has been repeatedly performed and executes the boot ROM program. In addition, the OS program changed through serial communication is stored in the control program area of the PLC device.

이후, 저장이 완료되면 부트롬 프로그램의 수행을 멈추고 변경된 피엘씨장치의 제어프로그램을 반복 수행하여 제어대상(14)을 제어한다.Thereafter, when the saving is completed, the execution of the boot ROM program is stopped, and the control target 14 is controlled by repeatedly executing the control program of the changed PLC device.

상기와 같이 동작하는 본 발명은 별도의 장비를 사용하지 않고 피엘씨장치의 오/에스 프로그램을 신속하게 변경할 수 있도록하여 변경시에 필요한 많은 시간과 비용을 줄일 수 있는 효과가 있다.The present invention operating as described above is able to quickly change the O / S program of the PLC device without using a separate device has the effect of reducing the time and cost required for the change.

Claims (1)

전원이 온된후 최초 수행되는 영역에 부트롬 프로그램을 저장하고, 다른 영역에 피엘씨 장치의 제어프로그램을 저장하는 플래시 메모리와; 제어 프로그램 변경시 상기 부트롬 프로그램을 수행하여 직렬통신으로 수신한 제어 프로그램을 상기 플래시 메모리의 제어 프로그램 영역에 저장하는 씨피유를 포함하여 구성된 것을 특징으로 하는 피엘씨장치.A flash memory for storing a boot ROM program in an area to be initially executed after the power is turned on, and storing a control program of a PLC device in another area; And a CPI storing the control program received in serial communication by executing the boot ROM program in a control program area of the flash memory when the control program is changed.
KR1019970037780A 1997-08-07 1997-08-07 Plc system including a flash memory a cpu KR100434136B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970037780A KR100434136B1 (en) 1997-08-07 1997-08-07 Plc system including a flash memory a cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970037780A KR100434136B1 (en) 1997-08-07 1997-08-07 Plc system including a flash memory a cpu

Publications (2)

Publication Number Publication Date
KR19990015591A KR19990015591A (en) 1999-03-05
KR100434136B1 true KR100434136B1 (en) 2004-08-25

Family

ID=37341007

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970037780A KR100434136B1 (en) 1997-08-07 1997-08-07 Plc system including a flash memory a cpu

Country Status (1)

Country Link
KR (1) KR100434136B1 (en)

Also Published As

Publication number Publication date
KR19990015591A (en) 1999-03-05

Similar Documents

Publication Publication Date Title
KR20070061086A (en) High energy efficiency processor using dynamic voltage scaling
EP0797152A1 (en) Single-chip microcomputer with memory controller
JP2636691B2 (en) Microcomputer
KR970066888A (en) Microcomputers Using Nonvolatile Memory
CN103150288B (en) A kind of SOC of quick turn-on and its implementation
US5673417A (en) Electronic organizer with a flash memory and associated data archiving
KR19980020900A (en) Synchronous semiconductor memory device with macro command function and how to store and execute macro commands
EP0587445A2 (en) Semiconductor integrated circuit and IC card using the same
JP2003044303A (en) Computer system
KR100434136B1 (en) Plc system including a flash memory a cpu
KR20000003404A (en) Micro controller for accessing an external memory
JP4348664B2 (en) Programmable controller control method
KR100201005B1 (en) Power management control method
KR100199477B1 (en) Memory saving method and system
KR100225985B1 (en) Apparatus and method of saving power of computer
KR970002396B1 (en) A initialized method for a computer
JPH01181146A (en) Single-chip microcomputer
KR100241892B1 (en) Method for changing program code
CN115686177A (en) Processor, processing method of processor and electronic equipment
KR100383001B1 (en) On-board programing method for main control unit
JPH04105110A (en) Power controller
KR940011045B1 (en) Interrupt vector addressing method in micro controller unit
KR100261557B1 (en) Local system
JPH06259264A (en) Clock control circuit
CN113760376A (en) Method for simultaneous operation and operation of TP chip CPU on Eflash

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120327

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20130222

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20160401

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee