KR100431104B1 - Interface circuit using a multi flag and an interface method of the same - Google Patents

Abstract

The present invention relates to an interface circuit using a multi-flag and an interface method thereof, wherein a buffer memory unit is divided into virtual memory regions having a predetermined size according to a plurality of flags, and each divided virtual memory region is assigned to each flag. And write data into each virtual memory region according to the write signal of the decoder, and control to read data written according to the read signal of the processing unit. present.

Description

Interface circuit using a multi flag and an interface method of the same}

The present invention relates to an interface circuit using multiple flags and an interface method thereof, and more particularly to an interface circuit using multiple flags and an interface method thereof capable of reducing the size of a buffer memory constituting a digital audio decoder. .

The Motion Pictures Expert Group (MPEG) is a group of video and multimedia experts that have been developed by experts in this field under the umbrella of international standards bodies such as the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC). Technical criteria were established, such as compressing the signal, transmitting it, and restoring it again.

MPEG-1 and MPEG-2 are currently in use, and MPEG-4 is being enacted. In the case of audio, MPEG-1 is generally referred to as MPEG standard. The audio part of the MPEG standard is divided into a first layer (Layer-1), a second layer ('Layer-2) and a third layer (Layer-3). The first layer was used for the PASC compression algorithm developed by Philips for the Digital Compact Cassette (DDC), and further developed into the second and third layers to provide superior sound quality even with greater compression.

The most popular MPEG-1 Audio Layer-3, or Digital Audio Decoder, was developed by the Fraunhorer Institute in Germany for digital audio broadcasting. It is a method of compressing by using man's hearing sound recognition pattern artfully.

In general, when a loud note and a loud note are heard at the same time, the small note is buried in the sound of the loud note so that it is hard to hear. This auditory recognition effect is called a masking effect. In the digital audio decoder, the audio frequency is first divided into 32 parts, and each part is further divided into 18 parts and 576 detailed parts. Then, the masking effect is applied to each part, leaving only the loudest component in each of the 576 parts, removing the remaining parts, and then compositing each part. Basically, the compression method and concept used by DDC and Mini Disk (MD) are similar, but they are much improved.

1 is a block diagram illustrating the configuration of a general digital audio decoder.

Referring to FIG. 1, the digital audio decoder includes an input means 100 for inputting compressed audio data (EAD), a decoded output signal output from the input means 100, and audio data (Decoded Audio). A decoding block (200) for restoring data (DAD) and an output unit (300) for outputting an output signal output from the decoding unit (200) to an external output unit (400).

The input means 100 includes a pre processing block 110 for importing data EAD from a memory element (not shown) in which the compressed audio data EAD is stored, and the preprocessing unit ( Input interface 120 for controlling the transmission of the output signal output from the 100, and for temporarily storing the output signal of the pre-processing unit 100 in accordance with the control signal of the input interface unit 120 An input buffer 130 is provided.

The output unit 300 outputs an output signal of the decoding unit 200 according to an output interface 310 for controlling the output signal of the decoding unit 200 and a control signal of the output interface 310. Post-processing for taking the data stored in the output buffer memory unit 320 and the output buffer memory unit 320 for temporarily storing the data stored in the output buffer memory unit 320 according to the control signal of the output interface unit 310. And a post processing block 330.

The external output unit 400 converts the output signal from the output means 300 into a D / A converter 410 for analog-converting the output signal, and outputs the output signal of the D / A converter 410 to a predetermined size. It consists of an amplifier 420 for amplifying. In addition, the output signal of the external output unit 400 is output through the speaker 500.

FIG. 2 is a detailed circuit diagram of the output unit 300 shown in FIG. 1 and illustrates an example of an output buffer memory unit 320 including first and second buffer memories Buffer_A and Buffer_B.

As shown in FIG. 2, the output buffer memory unit 320 includes first and second buffer memories Buffer_A and Buffer_B, and each buffer memory Buffer_A and Buffer_B has a 1152 word single port SRAM (1152 word single). port SRAM). The output interface 310 includes a flag 311 composed of the first and second flags Flag_A and Flag_B, and an access between the decoding unit 200, the post processing unit 330, and the output buffer memory unit 320. Bus arbiter block (312) for controlling the.

As illustrated in FIG. 3, the bus arbiter 312 may include a decoding address signal Dec_addr and a post processing unit 330 of the decoding unit 200 according to the first flag signal FS_A output from the flag unit 310. A first multiplexer 10 that selects one of the post-address signals Post_addr and outputs an address signal A_addr for selecting an address of the first buffer memory Buffer_A in response to the selected signal; To select one of the decoding address signal Dec_addr and the post address signal Post_addr according to the second flag signal FS_B, and to select an address of the second buffer memory Buffer_B according to the selected signal. The second multiplexer 20 outputs an address signal B_addr.

In addition, the write signal A_write of the first buffer memory Buffer_A corresponding to the decoding_write signal Dec_write of the decoding unit 200 is activated according to the first flag signal FS_A, or the post processing unit ( According to the first logic unit 30 for activating the read signal A_read of the first buffer memory Buffer_A corresponding to the post read signal Post_read of 330 and the second flag signal FS_B. The write signal B_write of the second buffer memory Buffer_B corresponding to the decoding_write signal Dec_write is activated or the read signal of the second buffer memory Buffer_B corresponding to the post read signal Post_read ( And a second logic unit 40 for activating B_read).

In addition, the input data signal A_data_in is output to store the decoded data Dec_data of the decoding unit 200 in the first buffer memory Buffer_A according to the first flag signal FS_A, and the second flag signal According to FS_B, the third logic unit 50 for outputting the input data signal B_data_in to store the decoded data signal Dec_data in the second buffer memory Buffer_B, and to the first flag signal FS_A. Accordingly, the output data signal A_data_out is output to transmit the data stored in the first buffer Buffer_A to the post processing unit 330, and the data stored in the second buffer memory Buffer_A according to the second flag signal FS_B. The fourth logic unit 60 is configured to output the output data signal B_data_out to transmit the data to the post processing unit 330. Here, the third and fourth logic units 50 and 60 are configured as a three-stage buffer.

Referring to the operation of the bus arbiter 312 configured as described above as an example.

If the first flag signal FS_A is '0' and the second flag signal FS_B is '1', the first multiplexer 10 may perform a decoding address signal Dec_addr and a post address signal Dec_addr. The decoding address signal Dec_addr is selected and output, and the second multiplexer 20 selects and outputs the post address signal Dec_addr. Accordingly, the address signal A_addr of the first buffer Buffer_A corresponding to the decoding address signal Dec_addr is selected through the first multiplexer 10, and the address signal A_addr is selected through the second multiplexer 20 to the post address signal Post_addr. The address signal B_addr of the corresponding second buffer memory Buffer_B is selected.

The first logic unit 30 outputs the decoded write signal Dec_write among the decoded write signal Dec_write and the post read signal Post_read, and the second logic unit 40 outputs the post read signal Post_read. As a result, the write signal A_write of the first buffer memory Buffer_A is activated, and the read signal B_read of the second buffer memory Buffer_B is activated. The third logic unit 50 outputs the input data signal A_data_in to store the decoded data signal Dec_data transmitted from the decoding unit 200 in the first buffer memory Buffer_A. The fourth logic unit 60 outputs an output data signal B_data_out to transmit the data stored in the second buffer memory Buffer_B to the post processing unit 330.

However, as described above, the digital audio decoder can be implemented in a relatively simple manner, but there is room for improvement in that two buffer memories of the same size are used. In other words, the digital audio decoder uses two large-capacity single-port SRAM memories to form an output buffer memory section, which causes the total area to increase. To solve this problem, instead of using two single port SRAMs, one dual port SRAM (Dual port SRAM) can be used to configure the output buffer memory, but the dual port SRAM memory has a larger size than the single port SRAM memory. There is this.

Accordingly, the present invention has been made to solve the above problem, and when the write operation of the decoding unit and the read operation of the post processing unit are simultaneously performed, the read operation is given priority and the write operation is delayed by one cycle, thereby reducing the size of the output buffer memory unit. An object of the present invention is to provide an interface circuit using a multi-flag and an interface method thereof.

According to the present invention, the single port SRAM constituting the output buffer memory unit is virtually subdivided using a plurality of flags, and the memory size constituting the output buffer memory unit can be reduced by allocating the virtual segmented virtual memory to each flag. Another object of the present invention is to provide an interface circuit using a multi-flag and an interface method thereof.

1 is a block diagram showing the configuration of a general digital audio decoder.

FIG. 2 is a detailed circuit diagram of the output means shown in FIG.

3 is a detailed circuit diagram of a bus arbiter portion shown in FIG. 2;

4 is a block diagram illustrating a configuration of a digital audio decoder according to an embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the bus arbiter portion shown in FIG. 4. FIG.

FIG. 6 is a detailed circuit diagram of the first logic unit illustrated in FIG. 5. FIG.

FIG. 7 is a detailed circuit diagram of the second and third logic units shown in FIG. 5; FIG.

8 is an operation waveform diagram of the bus arbiter portion shown in FIG. 4;

<Explanation of symbols for the main parts of the drawings>

100: input means 110: preprocessing unit

120: input interface unit 130: input buffer memory unit

200, 600: decoding unit 300: output means

310: output interface unit 311: flag unit

312, 700: bus arbiter section 320, 900: output buffer memory section

330 and 800: Post processing unit 400: External output unit

410: D / A converter 420: amplifier

500: speakers 711 and 712: first and second comparators

713 and 714: first and second address decoders

715: Flag module unit 716: First logic unit

721 to 713: second to fourth logic unit

730: complete detection unit

The present invention provides an interface circuit that controls to temporarily write data output from a predetermined decoder into a buffer memory unit and controls the processing unit to read the written data, wherein one buffer memory unit is a virtual memory area having a predetermined size. A flag module unit comprising a plurality of flags which are divided and allocated to each virtual memory area; Data writing and reading means for writing data into a corresponding virtual memory area according to an output signal of the decoder and reading data written into the corresponding virtual memory area according to an output signal of the processing unit; Set means for setting a corresponding flag of the flag module unit according to the write operation state of the decoder; Reset means for resetting a corresponding flag of the flag module unit in accordance with a read operation state of the processing unit; And control means for logically combining the output signal of the flag module unit to output a first signal for controlling the write operation of the decoder and a second signal for controlling the read operation of the processing unit.

In addition, the present invention provides an interface method for controlling to temporarily write data output from a predetermined decoder to a buffer memory unit, and to control the processor to read the written data, wherein one buffer memory unit is set according to a plurality of flags. Dividing the virtual memory area into a predetermined size and allocating the divided virtual memory areas to the respective flags; And writing data into each virtual memory area according to the write signal of the decoder, and controlling to read the data written according to the read signal of the processing unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a digital audio decoder according to an embodiment of the present invention. Here, the description of other components of the digital audio decoder not shown in FIG. 4 is the same as in the prior art and will be omitted.

Referring to FIG. 4, the decoding unit 600 receives and decodes compressed audio data EAD, receives a buffer full signal Buffer_full from the bus arbiter 700, and then decodes the compressed audio data EAD to the buffer full signal Buffer_full. Accordingly, the decoding address signal Dec_addr and the decoding write signal Dec_write are output to the bus arbiter 700 so as to store the decoded decoded data Dec_data in a predetermined area of the output buffer memory unit 900.

The post processing unit 800 reads the post address signal Post_data corresponding to the data stored in the output buffer memory unit 900 according to the buffer enable signal Buffer_en input from the bus arbiter unit 700. The post_addr and the post_read signal Post_read are output to the bus arbiter 700.

The output buffer memory unit 900 is composed of 1152 word single port SRAMs, and the decoding unit 600 according to the control signals (data_in / out, addr, write / read) of the bus arbiter 700. Decoded data (Dec_data) transmitted from the data is stored in a predetermined region or the post processing unit 800 reads the data stored in the predetermined region. In addition, as the output buffer memory unit 900 is divided into 18 virtual memory regions (64 words) by 18 flags (Flag), one flag is allocated with one virtual memory region.

The bus arbiter 700 provides an interface between the decoding unit 600 and the output buffer memory unit 900, and an interface between the post processing unit 800 and the output buffer memory unit 900. .

Referring to FIG. 5, the bus arbiter 700 includes an output buffer memory unit state detector 710, a data write / read control unit 720, and a conflict detector 730.

The output buffer memory state detector 710 may include a first comparator 710 for detecting that the lower 6 bits of the decoding address signal Dec_addr output from the decoder 600 become 63 (ie, 111111), and The first address decoder 730 and the post processor 800 for decoding the upper 5 bits of the decoding address signal Dec_addr according to the output signal of the first comparator 710 and outputting them as 18 decoded signals. The second comparator 720 for detecting that the lower six bits of the post address signal Post_addr become 63 (that is, 111111) and the post address signal Post_addr according to the output signal of the second comparator 720. A second address decoder 740 for decoding the upper five bits of the first bit and outputting the eighteen decoding signals, and output signals of the first and second address decoders 730 and 740 to detect the decoding address signal Dec_addr. ) In addition The buffer enable signal Buffer_en and the buffer full signal Buffer_full by logically combining the flag module unit 715 for setting or resetting a flag corresponding to the post address signal Post_addr and the output signal of the flag module unit 715. ) Is a first logic unit 716 for outputting.

The flag module unit 715 is composed of 18 bits, that is, 18 flags, each of which is allocated a memory area of the output buffer memory unit 900 by 64 words. In addition, as illustrated in FIG. 6, the first logic unit 716 OR-gates OR for outputting the buffer enable signal Buffer_en by ORing the output signals (ie, 18) of the flag module unit 715. OR; and an end gate (AND gate) AND for outputting the buffer full signal Buffer_full by ANDing the output signal of the flag module unit 715. Here, the buffer enable signal Buffer_en is a signal input to the post processing unit 800 and indicates whether data for reading data from a predetermined memory region of the output buffer memory unit 900 is stored. The buffer full signal Buffer_full is a signal input to the decoding unit 600 to indicate whether data can be written to a predetermined memory area of the output buffer memory unit 900.

The data write / read controller 720 may be configured to delay the decoding address signal Dec_addr, the decoding write signal Dec_write, and the decoding data Dec_data output by the decoding unit 600 by one cycle. 721 and the output signal of the second logic unit 721 according to the output signal CS of the conflict detection unit 730 or the decoding address signal Dec_addr and the decoding write output from the decoding unit 600. A third logic unit 722 for outputting the signal Dec_write and the decoded data Dec_data, and an output signal of the third logic unit 722 in accordance with the post read signal Post_read of the post processing unit 800; The fourth logic unit 722 is configured to select and output any one of the post address signals Post_addr.

As illustrated in FIG. 7, the second logic unit 721 delays the first de-flip-flop D-FF1 for delaying the decoded data Dec_data by one cycle and the decoded write signal Dec_write by one cycle. A second de-flip flop D-FF2 for delaying the third de-flip flop D-FF3 for delaying the decoding address signal Dec_addr by one cycle. The third logic unit 722 selects one of the output signal of the decoded data Dec_data and the first de-flip flop D-FF1 according to the output signal CS of the conflict detector 730. Any one of the first multiplexer MUX1 for outputting and the output signal of the decoding write signal Dec_write and the second de-flip flop D-FF2 according to the output signal CS of the conflict detector 730. The output signal of the decoding address signal Dec_addr and the third de-flip flop D-FF3 according to the second multiplexer MUX2 for selecting and outputting the signal, and the output signal CS of the conflict detection unit 730. And a third multiplexer MUX3 for selecting and outputting any one of the signals. The fourth logic unit 723 selects and outputs one of an output signal of the third multiplexer MUX3 and a post address signal Post_addr according to the post read signal Post_read.

The conflict detector 730 determines a priority by detecting a collision between the decoding write signal Dec_write of the decoder 600 and the post read signal Post_read of the post processor 800.

The operation of the bus arbiter 700 configured as described above will be described with reference to FIG. 8 as follows.

8, the decoding write signal Dec_write is generated once every six cycles of the main clock MC from the decoding unit 600, and the post read signal Post_read is generated from the post processing unit 800. The waveform diagram shows the case where it occurs once every 14 cycles of MC).

First, a data read (Data_out) operation by the post processing unit 800 will be described. When the post read signal Post_read output from the post processing unit 800 is generated and the post address signal Post_addr is input to the bus arbiter 700, the fourth logic unit 723 of the bus arbiter 700 is provided. First selects the post address signal Post_addr, and outputs an address signal addr corresponding to the post address signal Post_addr (PA [0]). Subsequently, data of the output buffer memory unit 900 corresponding to the output address signal addr is read by the post read signal Post_read to perform a data read Data_out operation (PAD [0]). .

Subsequently, when the data readout operation is completed, the second comparator 712 of the bus arbiter 700 receives the post address signal Post_addr, compares the lower bits of the post address signal Post_addr, and then selects a predetermined signal. (That is, a read operation completion signal) is output to the second address decoder 714. Subsequently, the second address decoder 714 decodes the output signal of the second comparator 712 and outputs a decoding signal for resetting the corresponding flag of the flag module 715 to '0'. The flag module 715 resets a corresponding flag to '0' according to the decoding signal and outputs a predetermined output signal to the first logic unit 716 in order to inform the decoding unit 600 and the post processing unit 800. do. The first logic unit 716 logically combines the output signals output from the flag module unit 715 to activate the buffer full signal Buffer_full or the buffer enable signal Buffer_en.

Next, the data write (Data_in) operation by the decoding unit 600 will be described. When the decoding write signal Dec_write, the decoding address signal Dec_addr, and the decoding data Decc_data output from the decoding unit 600 are input to the second and third logic units 721 and 722 of the bus arbiter unit 700. The signals Dec_write, Dec_addr, and Dec_data are delayed for one cycle by the second logic unit 721 or bypassed by the third logic unit 722. Subsequently, when the output signal CS of the conflict detection unit 730 is not activated, the decoded data Dec_data is written in a predetermined memory area corresponding to the decoding address Dec_addr of the output memory unit 900 to write data ( Data_in) operation is made (DA [0]).

When the data write operation is completed, the first comparator 711 of the bus arbiter 700 receives the decoding address signal Dec_addr, compares the lower bits of the decoding address signal Dec_addr, and then selects a predetermined signal. (I.e., the write operation completion signal) is output to the first address decoder section 713. FIG. Subsequently, the first address decoder 713 decodes the output signal of the first comparator 711 and outputs a decoding signal for setting the corresponding flag of the flag module 715 to '1'. The flag module 715 sets a corresponding flag to '1' according to the decoding signal and outputs a predetermined output signal to the first logic unit 716 to inform the decoding unit 600 and the post processing unit 800. do. The first logic unit 716 logically combines the output signals output from the flag module unit 715 to activate the buffer full signal Buffer_full or the buffer enable signal Buffer_en.

Next, the operation of the bus arbiter 700 when the decoding write signal Dec_write and the post processing unit Post_read of the decoding unit 600 occur at the same time will be described.

As illustrated in FIG. 1, when the decoding write signal Dec_write and the post read signal Post_read occur at the same time, the conflict detection unit 730 detects the signals Dec_write and Post_read and generates a third logic unit ( A complete signal CS is output to the 722. Thereafter, the third logic unit 722 outputs the signals Dec_addr, Dec_data, and Dec_write latched by the second logic unit 21 to the fourth logic unit 723, and the fourth logic unit 723 By outputting the post address signal Post_addr, a read operation is performed in preference to a write operation. Accordingly, the data read operation is generally performed, whereas the data write operation is performed one cycle later than the decoded data Dec_data.

As described above, the present invention can be implemented by the speed difference between the read operation and the write operation.

In general, the time at which the post processing unit 800 reads data from the output buffer memory unit 900 is always kept constant by an audio sampling frequency, and accordingly, the decoding unit 600 decodes the data. This is done. For example, a music sampled at 44.1 KHz would have a period of 22.676 milliseconds since mono would require 44,100 audio samples per second. That is, the post processing unit 800 reads one sample per 22.6 Hz from the output buffer memory unit 900, whereas the decoding unit 600 outputs the operating speed of the decoding unit 600 because it is usually several tens of MHz. When data is written to the buffer memory unit 900, a read operation is performed once in several tens to hundreds of microseconds.

Accordingly, the present invention gives priority to the read operation when the write operation of the decoding unit 600 and the read operation of the post processing unit 800 are performed at the same time, and the bus arbiter unit 700 is delayed by one cycle. By configuring the output buffer memory unit 900 using one single port SRAM, the same operation characteristics as those of the related art can be realized. In addition, the present invention configures the output buffer memory unit 900 by assigning virtual flags that are virtually subdivided to each flag using a single port SRAM constituting the output buffer memory unit 900. Can reduce the memory size.

According to the present invention, when the write operation of the decoding unit and the read operation of the post processing unit are performed simultaneously, the read operation may be given priority and the write operation may be delayed by one cycle, thereby reducing the size of the output buffer memory unit.

According to the present invention, the single port SRAM constituting the output buffer memory unit is virtually subdivided using a plurality of flags, and the memory size constituting the output buffer memory unit can be reduced by allocating the virtual segmented virtual memory to each flag. have. Furthermore, the reduction of the output buffer memory unit can shorten the access time of the write operation of the decoding unit and the read operation of the post processing unit.

Claims (12)

An interface circuit for controlling to temporarily write data output from a predetermined decoder into a buffer memory unit, and to control the processing unit to read the written data. A flag module unit comprising a plurality of flags to which each virtual memory area is allocated by dividing one buffer memory unit into a virtual memory area having a predetermined size; Data writing and reading means for writing data into a corresponding virtual memory area according to an output signal of the decoder and reading data written into the corresponding virtual memory area according to an output signal of the processing unit; Set means for setting a corresponding flag of the flag module unit according to the write operation state of the decoder; Reset means for resetting a corresponding flag of the flag module unit in accordance with a read operation state of the processing unit; And And a control means for logically combining the output signal of the flag module unit to output a first signal for controlling the write operation of the decoder and a second signal for controlling the read operation of the processing unit. . The method of claim 1, The data writing and reading means includes: a first logic section for delaying an output signal output from the decoder for a predetermined cycle; A complete detector for detecting a write signal among the output signals of the decoder and a read signal among the output signals of the processing unit; A second logic unit which selects and outputs one of an output signal of the decoder and an output signal of the latch unit according to an output signal of the conflict detection unit; And And a third logic unit configured to output one of an output signal of the second logic unit and an address signal of the processing unit according to the read signal of the processing unit. The method of claim 2, The first logic unit comprises: a first de-flip-flop for delaying a data signal of the output signal of the decoder for a predetermined cycle; A second de-flip-flop for delaying a write signal of the output signal of the decoder for a predetermined cycle; And And a third de-flip-flop for delaying an address signal of the output signal of the decoder for a predetermined cycle. The method of claim 2, The second logic unit may include a first multiplexer configured to output one of a data signal among the output signals of the decoder and an output signal of the first de-flip flop according to the output signal of the conflict detector; A second multiplexer for outputting any one of a write signal among the output signals of the decoder and an output signal of the second de-flip flop according to the output signal of the conflict detector; And And a third multiplexer for outputting any one of an address signal and an output signal of the third de-flip flop among the output signals of the decoder according to the output signal of the conflict detector. The method of claim 1, The set means includes: a comparator for receiving a predetermined bit and comparing the lower bit of the address signal of the decoder; And And a decoder unit for decoding the upper bits of the address signal according to the output signal of the comparator. The method of claim 1, The reset means includes: a comparator for receiving a predetermined bit and comparing the lower bit of the address signal of the processing unit; And And a decoder unit for decoding the upper bits of the address signal according to the output signal of the comparator. The method of claim 1, The control means includes an OR circuit for outputting the first signal by ORing the output signal of the flag module unit; And And an ant circuit for outputting the first signal by ANDing the output signal of the flag module unit. An interface method for controlling to temporarily write data output from a predetermined decoder into a buffer memory unit, and to control the processing unit to read the written data. Dividing one buffer memory unit into a virtual memory region having a predetermined size according to a plurality of flags, and assigning each of the divided virtual memory regions to the respective flags; And writing data into each virtual memory region according to the write signal of the decoder, and controlling to read the data written according to the read signal of the processing unit. The method of claim 8, And the buffer memory unit is divided into virtual memory regions by the number of flags. The method of claim 8, And a virtual memory area in which data is written in accordance with the write signal of the decoder is selected according to the address signal of the decoder. The method of claim 8, And a virtual memory area in which data is read according to the read signal of the processor is selected according to the address signal of the processor. The method of claim 8, And the read signal of the processing unit is given priority over the write signal of the decoder.