KR100427041B1 - Apparatus for generating a reference voltage in ferroelectric memory device - Google Patents

Abstract

The present invention is to provide a reference voltage generator device of the ferroelectric memory which can improve the production yield by increasing the possibility of defective products of the FeRAM device, for this purpose, the reference voltage generator device of the present invention, the bit line; First and second reference word lines; First and second reference cell plates; One side is connected to the first reference cell plate, and is connected between a first ferroelectric capacitor for storing a first level of data, the sub bit line and the other side of the first ferroelectric capacitor, and the first reference word line is connected to the first reference cell plate. A first reference cell including a first switching transistor connected to a gate terminal; And a second side connected to the second reference cell plate, the second ferroelectric capacitor storing a second level of data, and the second bit line and the other side of the second ferroelectric capacitor. A second reference cell including a second switching transistor connected to the gate terminal, and simultaneously applying the voltage to the cell word line and the cell plate to read data stored in a specific cell; The same voltage as that of the cell word line is applied to the word line, and the voltage is applied to the first and second reference cell plates, but a reference voltage is generated by applying a voltage 0.2 to 0.8 times the voltage applied to the cell plate. A reference voltage generator for ferroelectric memory is provided.

Description

Apparatus for generating a reference voltage in ferroelectric memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric semiconductor memory device using ferroelectric capacitor memory cells, and more particularly, to a reference voltage generator in which two reference cells having the same structure as a memory cell are connected to one sub bit line.

First, the characteristics of the ferroelectric capacitor will be described. FIG. 1 shows the relationship between the voltages of both ends of the ferroelectric capacitor. (Hysterisys) is a ferroelectric capacitor. When the voltage at both ends is "0" V, the induced charges exist in two states, 'ga' and 'me', so that data in binary form (" 0 "," 1 ") can be stored. By utilizing these characteristics, the ferroelectric capacitor is used as a storage means of the nonvolatile memory device. In addition, the polarization state in the ferroelectric is changed according to the magnitude of the voltage applied to both ends of the ferroelectric capacitor, and the amount of charge stored in the capacitor is changed. As the capacitor is switched along the hysteresis curve of FIG. 1, the polarization state changes in the 'multi' direction, and when the negative voltage is removed to make the voltage across the capacitor as “0 V”, the state moves to the “I” state. That is, in the ferroelectric capacitor, the state of the charge amount changes in the direction of the arrow according to the voltage, and the information stored in the ferroelectric capacitor detects the degree of change in the charge amount induced when the voltage is applied across the capacitor and makes data.

In the process of reading the information stored in the ferroelectric memory cell, when a wordline (Wordline, WL) is opened, a bitline (hereinafter, referred to as BL) according to the information ("0" or "1") stored in the cell. Has different voltage values V0 or V1. For convenience, the smaller of the two voltages is called V0 and the larger of them is called V1, and the information corresponding to V0 and V1 is called "0" and "1", respectively. Since the voltages V0 and V1 are small signals, they must be amplified using a sense amplifier. For this purpose, a reference voltage having a value between V0 and V1 (hereinafter referred to as Vref) is a bit line (hereinafter, / BL). Must be authorized). That is, the sense amplifier senses and amplifies whether the voltage V0 or V1 of BL is lower than or higher than Vref applied to / BL to determine whether the information stored in the cell is '0' or '1'. Therefore, the reference voltage Vref should always be made to have a value between V0 and V1.

FIG. 2 is a unit cell circuit diagram of a ferroelectric memory device, in which the switching transistor T1 and the switching transistor T1 having a gate connected to one word line WL0 and a drain or source connected to one bit line BL0 are shown. It is connected to the other terminal, the other terminal is made of a ferroelectric capacitor (C1) for information storage that is connected to one cell plate (CP0) to form one memory cell (21).

The Ferro Electric Random Access Memory (FeRAM) having the above configuration has a structure similar to that of the Dynamic Random Access Memory (DRAM) in that each memory cell 21 has one transistor T1 and a capacitor C1. . A ferroelectric material, such as Pb (Zr, Ti) O ₃ (PZT) or SrBi ₂ Ta ₂ O ₉ (SBT), is used as a dielectric layer of the ferroelectric capacitor C1 that makes the FeRAM nonvolatile, and Pt is used as an electrode. Noble metals such as, Ir or Ru, RuO ₂ or IrO ₂ , which are oxides thereof, are used.

Therefore, the FeRAM has a difference from the DRAM in the driving method. In the case of DRAM, the voltage of CP, which is one electrode of the information storage capacitor C1, is fixed at 1/2 of the driving voltage VCC. In the case of FeRAM, the voltage of CP is driven from '0V' to 'VCC' each time each memory cell 21 is driven.

Herein, the time taken to drive the CP increases as the capacitance of the CP increases. To reduce the capacitance of the CP, the CP in the form of a line is taken, and the connected CP is selected every time the memory cell 21 is driven. To drive.

In addition, in the DRAM, the voltage of the BL rises or falls at VCC / 2 according to the stored data "1" or "0", and the rise or fall of such voltage is sensed at the VCC / 2 by a sense amplifier (not shown). The stored data "1" and "0" are distinguished by comparing and amplifying the voltage of / BL fixed with. However, in the FeRAM, when the CP is driven, the voltage of the BL increases without distinguishing the stored data "1" and "0". However, BL voltage rise (ΔV _{BL "1"} to Q _"1" / C _BL ) when " ₁ " is stored, BL voltage rise (ΔV _{BL "0"} to Q when "0" is stored _Greater than _"0" / C _BL ). Therefore, in order to distinguish between "1" and "0", an apparatus for generating a voltage rise of the intermediate value of the BL voltage rise when "1" is stored and the BL voltage rise when "0" is stored is separately. need.

3 is a circuit diagram of a conventional reference voltage generator.

Referring to FIG. 3, the reference voltage generator includes two reference cells 31 and 32 having the same structure as ferroelectric memory cells per two / BLs (/ BL0 and / BL1) in order to apply a reference voltage to each / BL. ), And the two reference cells 31 and 32 always store "1" and "0", respectively. Specifically, referring to the configuration of two reference cells 31 and 32 for applying Vref to / BL0 and / BL1, one side of the reference cell 31 is referred to as a reference cell plate (hereinafter referred to as RCP). Connected between the ferroelectric capacitor C31 and / BL0 for storing data "1" and the other side of the ferroelectric capacitor C31, and a reference word line (hereinafter referred to as RWL) is gated. And a switching transistor T31 connected to a stage, and the reference cell 32 has one side connected to the RCP, and the information storage ferroelectric capacitor C32 and the ferroelectric capacitor C32 storing data "0". The switching transistor T32 is connected between the other side and / BL1 and the RWL is connected to the gate terminal. The configuration of the remaining reference cells not shown here is the same.

The operation of the reference voltage generator having the above configuration will be described below.

When RWL and RCP are driven while "1" and "0" are stored in the reference cells 31 and 32, respectively, a charge having a size that will generate ΔV _{BL ″ 1 ”} and ΔV _{BL ″ 0”} in each cell. Is generated. At this time, if / BL1 and / BL0 are connected, the voltage rises to two / BL simultaneously due to the charge generated in the two reference cells 31 and 32, and the magnitude is (ΔV _{BL "1"} + ΔV _{BL "0). The} data " 1 " and " 0 " stored in the memory cell can be distinguished by a sense amplifier (not shown).

By using the conventional reference voltage generator as described above, it is possible to generate a very stable reference voltage. This is because the change of residual polarization due to fatigue and hysteresis distortion of the ferroelectric capacitor is canceled by two capacitors T31 and T32 having opposite data.

In general, in the process of performing a semiconductor device manufacturing process, various defects may occur, for example, two electrodes of a capacitor are connected to each other. These defects should be eliminated as much as possible but have limitations, so that the defective device is classified as a defective product and becomes a major factor in lowering the production yield.

Therefore, in the case of a memory device or the like, a redundant cell is provided, and a defective cell of the device classified as a defective product due to a defect in the memory cell is replaced with a spare cell to make a good product. At this time, the more the extra cells are more likely to remedy defective products, but because it is a factor that increases the size of the chip (chip) only a certain amount is placed. Such defects may occur in FeRAM in the same way and may occur in a reference cell having a structure similar to that of a memory cell.

If a defect occurs in the reference cell, all cells connected to the BL using the defective reference cell are not operated (Column fail). However, since the conventional reference voltage generator uses two / BL signals output from two reference cells, even if a defect occurs in only one of the reference cells, the cells connected to the two BLs do not operate. Since two extra cell columns are used, relief is possible. Therefore, since the possibility of repair of defective products is lowered, there is a problem that the yield is lowered.

The present invention is to solve the above problems, by providing a reference voltage generator in a ferroelectric memory device that can improve the yield by increasing the possibility of repair of defective products by connecting two reference cells to one sub bit line. The purpose is.

1 is a graph showing hysteresis characteristics according to voltages across both ferroelectric capacitors.

2 is a unit cell circuit diagram of a ferroelectric memory device.

3 is a circuit diagram showing a reference voltage generator in a ferroelectric memory according to the prior art.

4 is a circuit diagram showing a reference voltage generator according to an embodiment of the present invention.

5 is a timing chart showing the characteristics of each signal according to the present invention;

* Description of the main parts of the drawing

41: first reference cell

42: second reference cell

The present invention for achieving the above object, a bit line; First and second reference word lines; First and second reference cell plates; One side is connected to the first reference cell plate, and is connected between a first ferroelectric capacitor for storing a first level of data, the sub bit line and the other side of the first ferroelectric capacitor, and the first reference word line is connected to the first reference cell plate. A first reference cell including a first switching transistor connected to a gate terminal; And a second side connected to the second reference cell plate, the second ferroelectric capacitor storing a second level of data, and the second bit line and the other side of the second ferroelectric capacitor. A second reference cell including a second switching transistor connected to the gate terminal, and simultaneously applying the voltage to the cell word line and the cell plate to read data stored in a specific cell; The same voltage as that of the cell word line is applied to the word line, and the voltage is applied to the first and second reference cell plates, but a reference voltage is generated by applying a voltage 0.2 to 0.8 times the voltage applied to the cell plate. A reference voltage generation device for a ferroelectric memory is provided. Hereinafter, a person skilled in the art will appreciate. In order to detail the extent that can be easily implemented by the scope, with reference to the accompanying drawings the preferred embodiments of the present invention will be described.

4 is a circuit diagram illustrating a reference voltage generator according to an embodiment of the present invention.

Referring to FIG. 4, the reference voltage generator of the present invention includes a sub bit line / BL0, first and second reference word lines RWL_H and RWL_L, and voltages of 0.2 to 0.8 times the cell plate voltage. One side is connected to the applied first and second reference cell plates RCP_H and RCP_L and the sub bit line / BL0 or / BL1, and the other side is connected to the first reference cell plate RCP_H and is always One side of the first reference cell 41 having one level of data (“1”) and the second reference cell plate are connected in common with the first reference cell 41 to the sub bit line / BL0. The other side is connected to RCP_L and includes a second reference cell 42 which always has a second level of data ("0").

In addition, the first reference cell 41 is connected to the first reference cell plate RCP_H on one side thereof, and includes a first ferroelectric capacitor C41 and the data storing the first level data “1” and the first reference cell 41. A first switching transistor T41 connected between the sub bit line / BL0 and the other side of the first ferroelectric capacitor C41 and the first reference word line RWL_H connected to a gate terminal. ,

The second reference cell 42 has one side connected to the second reference cell plate RCP_L and a second ferroelectric capacitor C42 and the sub-bit storing the second level of data "0". A second switching transistor T42 is connected between the line / BL0 and the other side of the second ferroelectric capacitor C42 and the second reference word line RWL_L is connected to a gate terminal.

For convenience of description, in FIG. 4, the reference voltage generator is limited to four reference cells connected to two sub-bit lines / BL0 and / BL1, which are fully expandable.

In the reference voltage generator of the present invention configured as shown in FIG. 4, the reference cell 41 always writes " 1 " data in the reference cells 41 and 42 having the same structure as that of the memory cell. The reference cell 42 that writes data is connected to the same / BL0, but the voltage lower than the voltage applied to the memory cell plate applied to the RCP when performing a read operation, for example, 0.2 of the voltage applied to the memory cell plate. A reference voltage is generated by applying a voltage of -0.8 times.

On the other hand, a cell which always writes "1" data in one / BL and a cell which always writes "0" data is arranged to configure the reference cell, and then the voltage applied to the RCP in the same manner as described above. When the voltages applied to the memory cell plates are made the same, the reference voltage is approximately ΔV _{BL ″ 1 ″} + ΔV _{BL ″ 0 ”} , and thus cannot serve as a reference voltage.

However, the signal voltages ΔV _{BL ″ 1 ″} and ΔV _{BL ″ 0 ″} are generated by the polarization-voltage hysteresis characteristics of the ferroelectric capacitor, and the magnitude of the voltage is applied to the ferroelectric capacitor, that is, the cell plate. It is a function of the voltage applied. Therefore, if the voltage applied to the RCP in the reading process is sufficiently low compared to the voltage applied to the memory cell plate, the reference cell 41 always writes "1" data in one / BL and always "0" data. Even if the reference cell 42 is written, Vref can be generated which can be normally read.

In this case, the first and second ferroelectric capacitors C41 and C42 have an area of 0.5 to 1.5 times the memory cell capacitor.

5 is a timing chart showing the characteristics of each signal according to the present invention.

Referring to FIG. 5, when voltages WL and CP are applied to a word line and a cell plate to read data stored in a specific cell, the same voltage as WL is also applied to the RWLs RWL_H and RWL_L. In addition, Vref is generated by applying a voltage to the RCPs RCP_H and RCP_L but applying a voltage 0.2 to 0.8 times the voltage CP applied to the cell plate.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the production yield can be increased by increasing the possibility of defective products for FeRAM.

Claims (3)

delete Boobyline; First and second reference word lines; First and second reference cell plates; One side is connected to the first reference cell plate, and is connected between a first ferroelectric capacitor for storing a first level of data, the sub bit line and the other side of the first ferroelectric capacitor, and the first reference word line is connected to the first reference cell plate. A first reference cell including a first switching transistor connected to a gate terminal; And One side is connected to the second reference cell plate, and is connected between a second ferroelectric capacitor for storing a second level of data, the sub bit line and the other side of the second ferroelectric capacitor, and the second reference word line A second reference cell including a second switching transistor connected to a gate terminal, When a voltage is applied to a cell word line and a cell plate to read data stored in a specific cell, the same voltage as the cell word line is also applied to the first and second reference word lines simultaneously. A reference voltage generator of a ferroelectric memory, comprising applying a voltage to a cell plate but applying a voltage that is 0.2 to 0.8 times the voltage applied to the cell plate. The method of claim 2, The first and second ferroelectric capacitors, the reference voltage generator, characterized in that 0.5 to 1.5 times the memory cell capacitor.