KR100713063B1 - Apparatus for generating reference voltage in ferroelectric memory device - Google Patents

Abstract

The present invention is to provide a reference voltage generator of a ferroelectric memory device that can increase the reliability of the device by generating a stable reference voltage even after the ferroelectric memory device is stored at a high temperature for a long time, and the present invention provides a reference of the ferroelectric memory device 12. A voltage generating device comprising: a first switching transistor connected between a first sub bit line and a first storage node and having a gate connected to a reference word line; A first ferroelectric capacitor for storage connected between the first storage node and the reference plate line and always storing a first level of data; And a first reference cell connected between the first storage node and the first reference initialization line and having a second switching transistor connected at a gate thereof to the reference initialization control line. And a third switching transistor connected between the second sub bit line and the second storage node and having a gate connected to the reference word line. A second ferroelectric capacitor for storage connected between the second storage node and the reference plate line and always storing a second level of data; And a second reference cell connected between the second storage node and the second reference initialization line, the second reference cell having a fourth switching transistor having a gate connected to the reference initialization control line.

Ferroelectric memory device, ferroelectric capacitor, polarization relaxation phenomenon, reference voltage generator, reference voltage

Description

Reference voltage generator for ferroelectric memory devices {APPARATUS FOR GENERATING REFERENCE VOLTAGE IN FERROELECTRIC MEMORY DEVICE}             

1 is a hysteresis curve graph of the electric field-polarization characterizing a ferroelectric capacitor.

2 is a circuit diagram of a basic cell of a ferroelectric memory device using a ferroelectric capacitor.

3 is a circuit diagram of a reference voltage generator according to the prior art.

4 is a hysteresis curve graph of electric field-polarization converted by polarization relaxation.

5A is a hysteresis curve graph showing the positions of polarizations in which the absolute values of P _"1" and P _"0" of the ferroelectric capacitor in the reference cell are reduced by polarization relaxation phenomenon.

Fig. 5B is a hysteresis curve graph showing the polarization position when a predetermined voltage is applied to the ferroelectric capacitor of the reference cell to recover the lost polarization.

5C is a hysteresis curve graph showing the polarization position at which the polarization lost at the time of driving the reference cell is recovered.

6 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

* Description of the main parts of the drawing

N1, N2, N3, N4: switching transistor

FC1, FC2: Ferroelectric Capacitors for Data Storage

200, 220: reference cell

The present invention relates to a nonvolatile ferroelectric semiconductor memory device using a ferroelectric capacitor memory cell, and more particularly, to a reference voltage generator for generating a reference voltage which becomes a reference voltage of a sense amplification operation upon 'reading' stored information.

1 is a hysteresis curve of an electric field-polarization characterizing a ferroelectric capacitor. The ferroelectric capacitor is defined as "1" and "0" according to the polarization direction because residual polarization exists when the voltage at both ends is "0" V. Can store binary data. By utilizing these characteristics, the ferroelectric capacitor is used as a storage means of the nonvolatile memory device.

On the other hand, the cell array of the ferroelectric memory device is configured in a matrix form where a plurality of word lines and a plurality of bit lines cross each other, one memory cell as shown in Figure 2, one switching transistor and the information storage capacitor 1 Consists of dogs.

FIG. 2 is a circuit diagram of a basic cell of a ferroelectric memory device using a ferroelectric capacitor having the above characteristics, wherein a source of the switching transistor T1 is connected to a positive bit line BL0, and a gate of the switching transistor T1 is a word line. One of the electrodes of the ferroelectric capacitor C1 is connected to the drain of the switching transistor T1, and the other of the electrodes of the ferroelectric capacitor C1 is connected to the cell plate line CP0 for driving the ferroelectric capacitor C1.

The base cell of the ferroelectric memory device as described above is made of 1T1C and has the same configuration as a DRAM storage cell. However, a ferroelectric material such as Pb (Zr, Ti) O ₃ (PZT), SrBi ₂ Ta ₂ O ₉ (SBT) is used as the dielectric layer of the information storage capacitor C1 which makes the ferroelectric memory device nonvolatile. The electrode is made of a noble metal such as Pt, Ru, Ir, or an oxide of a noble metal such as RuO ₂ or IrO ₂ .

The difference between the ferroelectric memory device and the DRAM in the driving method is that in the case of DRAM, the voltage of the cell plate CP, which is one electrode of the information storage capacitor, is fixed at half of the driving voltage (V _cc / 2). In the case of the memory device, the voltage of the cell plate CP is variably driven from " 0 " V to " V _cc " for each memory basic cell. At this time, the time taken to drive the cell plate CP increases as the capacitance of the cell plate increases. In order to reduce the capacitance, the cell plate is in the form of a line, and the connected cell plate CP is connected every time the memory cell is driven. Select drive

Further, the data stored in the DRAM, i.e., the rise or drop of the voltage from "1" or "0", the voltage of the maintenance Tra of (BL) precharging is raised or drop in voltage of V _cc / 2, depending on the sense amplifier The " 1 " or " 0 " of the stored data is read by comparing / amplifying with the reference voltage of the sub bit line / BL fixed at V _cc / 2.

However, when the cell plate line CP is driven during read driving of the ferroelectric memory device, the voltage of the positive bit line BL always increases regardless of the data "1" or "0" stored in the ferroelectric capacitor. However, when "1" is stored in the ferroelectric capacitor, the voltage change amount of the positive bit line BL when the voltage change amount ΔV _{BL "1"} of the positive bit line BL is stored as "0" ( ΔV _{BL ″ 0 ″} ).

Therefore, between the positive bit line voltage value when reading data "1" and the positive bit line voltage value when reading data "0" in order to sense and amplify the minute voltage change of the positive bit line in the sense amplifier during a read operation. There is a need for a separate reference voltage generator for generating a reference voltage of an intermediate voltage value.

3 is a circuit diagram of a reference voltage generator according to the related art, and includes two reference cells 100 and 110 having the same structure as a ferroelectric memory cell to generate a reference voltage.

The two reference cells 100 and 110 always store "1" and "0", respectively. When the reference word line RWL is "high" and the switching transistors RT1 and RT2 are turned on during the read operation, and the reference plate line RCP is driven "high", ΔV _{BL "1"} A charge is generated that will generate ΔV _{BL ″ 0 ”} . At this time, if the sub bit lines / BL1 and / BL0 are connected, the voltages of the two sub bit lines / BL rise simultaneously due to the charge generated in the two reference cells, and thus (ΔV _{BL ″ 1 ″} + ΔV _BL). Maintain a voltage of _{" 0 "} ) / 2. Therefore, the voltage (ΔV _{BL ″ 1 ″} + ΔV _{BL ″ 0 ″} ) / 2 of the subbit line is used as the reference voltage of the sense amplifier to read data “1” or “0” stored in the memory cell.

On the other hand, if the ferroelectric capacitor with constant data is written for a long time for several milliseconds or decades while the electric field is removed, the absolute values of P _"1" and P _"0" decrease in the hysteresis curve of the ferroelectric capacitor. This phenomenon is commonly referred to as polarization relaxation. The hysteresis curve of the electric field-polarization converted by this polarization relaxation is shown in FIG. 4.

This polarization relaxation occurs quickly at high temperatures, and when the polarization relaxation occurs, reference voltages of different magnitudes are generated when the reference cell is repeatedly driven within a few milliseconds and when the reference cell is driven after a certain time. Therefore, when the driving power of the ferroelectric memory device is removed, stored at a high temperature for a long time, and the previously stored data is read, a problem occurs in the operation of the ferroelectric memory device, which is a nonvolatile memory.

The present invention has been made to solve the above problems, and provides a reference voltage generator of a ferroelectric memory device that can increase the reliability of the device by generating a stable reference voltage even after the ferroelectric memory device is stored at a high temperature for a long time. There is a purpose.

According to an aspect of the present invention, there is provided a reference voltage generator of a ferroelectric memory device, comprising: a first switching transistor connected between a first sub bit line and a first storage node and having a gate connected to a reference word line; A first ferroelectric capacitor for storage connected between the first storage node and the reference plate line and always storing a first level of data; And a first reference cell connected between the first storage node and the first reference initialization line and having a second switching transistor connected at a gate thereof to the reference initialization control line. And a third switching transistor connected between the second sub bit line and the second storage node and having a gate connected to the reference word line. A second ferroelectric capacitor for storage connected between the second storage node and the reference plate line and always storing a second level of data; And a second reference cell connected between the second storage node and the second reference initialization line, the second reference cell having a fourth switching transistor connected to a gate of the reference initialization control line.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.                     

According to the present invention, when a ferroelectric memory device stored for a long time is used, a predetermined voltage is applied to the ferroelectric capacitor of the reference cell until the reference cell is driven to recover the polarization lost by the polarization relaxation phenomenon, and then remove the electric field immediately before driving the reference cell. Always generate a constant reference voltage.

FIG. 5A is a hysteresis curve graph showing the positions of the polarizations in which the absolute values of P _"1" and P _"0" of the ferroelectric capacitor in the reference cell are reduced by polarization relaxation phenomenon, and FIG. 5B is a diagram illustrating the recovery of the lost polarization. FIG. 5C is a hysteresis curve graph showing a polarization position when a predetermined voltage is applied to a ferroelectric capacitor of a reference cell. FIG. 5C is a hysteresis curve graph showing a polarization position where a polarization lost at the time of driving a reference cell is recovered.

6 is a circuit diagram of a reference voltage generator according to an embodiment of the present invention.

As shown in the figure, the reference voltage generator according to an embodiment of the present invention is a switching between the sub bit line / BL0 and the storage node (SN1) and the reference word line (RWL) is connected to the gate terminal Information storage ferroelectric capacitor FC1 connected between transistor N1, storage node SN1 and reference plate RCP, and between storage node SN1 and Reference Initialize line RI1. The reference initialization control line RIC is connected between the reference cell 200 including the switching transistor N2 connected to the gate terminal, the sub bit line / BL1 and the storage node SN2, and the reference word line RWL is connected to the gate transistor switching transistor (N4), the storage node (SN2) and the reference plate (RCP) information storage ferroelectric capacitor (FC2) and storage node (SN2) and the reference initialization line (RI0). ) Between The reference initialization control line RIC is formed of a reference cell 220 having a switching transistor N3 connected to a gate terminal. The reference cell 200 always stores data "1", and the other The data "0" is always stored in the reference cell 220.

The reference voltage generator of the present invention configured as described above generates the reference voltage in the same manner as the conventional reference voltage generator, but before the reference voltage is generated, the reference plate line (RCP) to V _cc / 2, the reference initialization line (RI1) Is driven to V _cc and another reference initialization line RI0 to V _ss , respectively, and the reference initialization control line RIC is driven to V _cc to drive the storage node SN1 of the reference cell 200 to the reference initialization line. At RI1, the ferroelectric capacitors FC1 and FC2 are connected by applying the voltage difference across the ferroelectric capacitors FC1 and FC2 by connecting the storage node SN2 of the reference cell 220 to the reference initialization line RI0, respectively. The polarization state of FIG. 5B is obtained.

Thereafter, the reference voltage generation operation is performed in the same manner as in the conventional reference voltage generator.

Accordingly, the reference voltage generator of the present invention can generate a stable reference voltage by removing the polarization relaxation phenomenon that occurs when the ferroelectric memory device is used for a long time before generating the reference voltage in earnest.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above comprises a separate switching transistor connected to the storage node of the reference cell, and by turning on the switching transistor before driving the reference cell by applying a predetermined voltage across the ferroelectric capacitor of the reference cell to reduce polarization By recovering the polarization lost by the phenomenon, and subsequently generating a reference voltage, a stable reference voltage can be generated regardless of the polarization relaxation phenomenon, thereby improving the operating reliability of the ferroelectric memory device.

Claims (3)

delete In the reference voltage generator of the ferroelectric memory device, A first switching transistor connected between the first sub-bitline and the first storage node and having a gate connected to the reference word line, and stored between the first storage node and the reference plateline and storing a first level of data; A first reference cell having a first ferroelectric capacitor, and a second switching transistor connected between the first storage node and the first reference initialization line and whose gate is connected to a reference initialization control line; And A third switching transistor connected between a second sub-bit line and a second storage node and having a gate connected to the reference word line, and connected between the second storage node and the reference plate line to store a second level of data; A second reference cell having a storage second ferroelectric capacitor, and a fourth switching transistor connected between the second storage node and the second reference initialization line and having a gate connected to the reference initialization control line, The reference initialization control line after driving the reference plate line to (power supply voltage level / 2), the first reference initialization line to the power supply voltage level, and the second reference initialization line to the ground power supply level before generating a reference voltage, respectively. Driving to the power supply voltage level to eliminate the polarization relaxation phenomenon of the first and second ferroelectric capacitors. The method of claim 2, And the first level is logic " 1 " and the second level is logic " 0 ".

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