KR100422958B1 - Method for forming fine pattern by argon ion implantation process - Google Patents

Method for forming fine pattern by argon ion implantation process Download PDF

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KR100422958B1
KR100422958B1 KR1019960079901A KR19960079901A KR100422958B1 KR 100422958 B1 KR100422958 B1 KR 100422958B1 KR 1019960079901 A KR1019960079901 A KR 1019960079901A KR 19960079901 A KR19960079901 A KR 19960079901A KR 100422958 B1 KR100422958 B1 KR 100422958B1
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photoresist
pattern
layer
argon ion
forming
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KR19980060539A (en
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김진수
전준성
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE: A method for forming a fine pattern by an argon ion implantation process is provided to simplify a fabricating process and minimize the occurrence of a defect by replacing a conventional TLR(tri-layer resist) process and by using photosensitizer as a bottom ARC(anti-reflective coating). CONSTITUTION: The first photoresist layer is formed on an etching target layer formed on a substrate(10). Argon ions are implanted into the first photoresist layer to form a photoresist layer(30) having good quality on the first photoresist layer. The second photoresist is formed on the photoresist having the improved quality. An exposure and development process is performed on the second photoresist layer to form the second photoresist layer pattern. An etching target layer pattern is formed by an etch process.

Description

아르곤 이온주입 처리를 통한 미세 패턴 형성방법Fine pattern formation method through argon ion implantation

본 발명은 반도체 소자 제조를 위한 리소그래피 공정에서 미세 레지스트 패턴을 형성하는 방법에 관한 것이며, 보다 상세하게는 고집적 반도체 소자의 미세회로 제작시 아르곤(Ar) 이온주입 처리를 통해 감광제의 특성을 변화시켜 간단하고효과적으로 미세 패턴을 형성시키는 방법에 관한 것이다.The present invention relates to a method of forming a fine resist pattern in a lithography process for manufacturing a semiconductor device, and more particularly, by changing the characteristics of the photosensitive agent through the argon (Ar) ion implantation treatment during the fabrication of the microcircuit of the highly integrated semiconductor device And to effectively form a fine pattern.

반도체 소자의 초고집적화로 인한 초미세 패턴을 형성하기 위해 현재 개발되고 있는 공정은 TLR(Tri-Layer Resist) 프로세서가 있다. 이 공정은 단차가 있는 기판 위에 일차 감광제를 1.0 ㎛ 이상 도포하여, 단차부분을 평탄화 한 후 고열로 가열한 다음, 그 위에 옥사이드계 물질을 증착시키고 그 위에 이차로 감광제를 다시 도포하는 방식으로 구성된다. 그리하여 최종적으로 도포된 이차 감광제 위에 노광 공정을 통해 패턴을 형성시킨 후, 이차 감광제 위에 형성된 패턴을 이용하여 옥사이드층을 식각하고, 옥사이드층에 형성된 패턴을 이용하여 일차 감광제 층을 식각하고, 이 식각된 일차 감광제층의 패턴을 최종 마스크로 하여 단차가 있는 기판을 식각하는 공정을 거친다. 그러나, 이러한 TLR 공정은 그 공정이 매우 복잡하고 그로 인하여 결점 (defect)이 많이 발생하여 경제적이지 못하다.A process currently being developed to form an ultrafine pattern due to ultra-high integration of semiconductor devices is a TLR (Tri-Layer Resist) processor. This process consists of applying a primary photoresist at least 1.0 μm on a stepped substrate, flattening the stepped portion, heating it to high heat, then depositing an oxide-based material thereon and re-coating a second photoresist thereon. . Thus, after the pattern is formed on the finally applied secondary photoresist through an exposure process, the oxide layer is etched using the pattern formed on the secondary photoresist, and the primary photoresist layer is etched using the pattern formed on the oxide layer, The substrate having a step is etched using the pattern of the primary photoresist layer as a final mask. However, this TLR process is not economical because the process is very complicated and defects are generated a lot.

그리고 현재 기판의 반사율을 줄여 노칭(notching), 즉 패턴이 끊어지는 현상을 방지하고, 패턴 크기의 차이를 최소화하기 위해 사용되고 있는 ARC(Anti-Reflect Coating) 물질들은 주로 유기 화합물로서, 스트립이 용이하지 않고 그로 인하여 입자가 발생하여 반도체 소자에 악영향을 미칠 뿐만 아니라, 결점이 많이 발생하고, 차후 잔여 ARC 층을 제거해야하는 등 공정이 복잡한 단점이 있다.In addition, ARC (Anti-Reflect Coating) materials, which are currently used to reduce the reflectance of the substrate to prevent notching, that is, break the pattern, and minimize the difference in pattern size, are mainly organic compounds, which are not easily stripped. And not only adversely affect the semiconductor device due to the generation of particles, but also a lot of defects, the process has to be complicated, such as the need to remove the residual ARC layer in the future.

이에 본 발명자들은 기존의 TLR 공정의 문제점을 인식하고 이를 개선하기 위해 연구한 결과, 감광제를 도포한 후 그 위에 일정량의 아르곤 이온을 주입시킴으로써, 감광제의 일정 부분이 개질(탄화: carbonize)되어, 노광광원에 반응하지 않아 현상되지 않으며, 그 위에 감광제를 이중 코팅하였을 때, 표면이 영향을 받지 않고 감광제를 도포할 수 있다는 것을 발견하였다. 그리고, 아르곤 이온의 사용량과 에너지에 따라 아르곤 이온주입 처리된 부분의 감광제의 굴절률 및 흡수율 변화를 유도할 수 있어 노광 빛을 흡수하는 특성을 갖게 할 수 있다는 것을 발견하였다.Accordingly, the present inventors have recognized the problems of the conventional TLR process and studied to improve the results, by applying a certain amount of argon ions thereon after applying the photosensitive agent, a portion of the photosensitive agent is modified (carbonized), exposure It was found that it did not develop because it did not react to the light source, and when double-coated the photoresist thereon, the surface could be applied without affecting the photoresist. In addition, it was found that the refractive index and the absorbance change of the photosensitive agent in the argon ion implanted portion may be induced according to the amount and energy of the argon ion, and thus the exposure light may be absorbed.

따라서, 본 발명의 목적은 기존의 미세 패턴 형성공정에서 이용되던 복잡한 TLR 공정을 대체할 수 있는 새로운 미세패턴 형성방법을 제공하는 데에 있다.Accordingly, an object of the present invention is to provide a new fine pattern forming method that can replace the complex TLR process used in the existing fine pattern forming process.

도 1 은 본 발명의 방법에서 감광제 위에 아르곤 이온을 주입 처리하였을 때 감광제 표면 부위의 일정 부분이 개질된 것을 도식화한 도면.1 is a diagram showing that a portion of the surface portion of the photosensitive agent is modified when the implantation treatment of argon ions on the photosensitive agent in the method of the present invention.

도 2 는 본 발명을 이용한 TLR 대체 공정도.Figure 2 is a TLR replacement process using the present invention.

도 3 은 본 발명을 이용한 바톰 ARC 대체 공정도.3 is a bottom ARC replacement process using the present invention.

도 4 는 본 발명의 감광제 표면의 일정부분을 아르곤 이온을 주입시킨후 톱 감광제를 도포한 후 패턴닝시킨 도면.4 is a pattern of a portion of the surface of the photosensitive agent of the present invention after implanting argon ions and then applying a top photosensitive agent and patterning.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10 : 기판 11: 웨이퍼10: substrate 11: wafer

20, 40 : 감광막20, 40: photosensitive film

30 : 개질된 감광막30: modified photosensitive film

본 발명의 미세 레지스트 패턴을 형성시키는 방법은, (a) 기판 위에 감광제를 도포하는 단계, (b) 여기에 아르곤 이온을 주입처리하여 감광제의 일정부분을 개질하는 단계 (도 1 참조), (c) 개질된 층위에 감광제를 도포하는 단계, (d) 노광공정을 통해 패턴을 형성, 식각 공정을 통해 최종 패턴을 형성시키는 단계로 이루어진다.The method of forming a fine resist pattern of the present invention comprises the steps of (a) applying a photoresist on a substrate, (b) implanting argon ions therein to modify a portion of the photoresist (see FIG. 1), (c ) Applying a photosensitive agent on the modified layer, (d) forming a pattern through the exposure process, and forming a final pattern through the etching process.

본 발명의 미세 레지스트 패턴 형성 방법에서 감광층에 아르곤 이온을 주입처리하는 단계를 통해 개질층은 노광 광원에 반응하지 않아 현상액에 현상되지 않으며, 아르곤 이온의 주입량에 따라 일정 파장대의 빛을 흡수하는 기능을 가지므로 ARC 층으로서 사용할 수 있을 뿐만 아니라, 계면접착력이 우수하고 그 위에 감광제를 이중도포할 때의 도포 특성이 매우 우수하다. 따라서, TLR 공정에서 필요로 하였던 옥사이드 층을 따로 증착시킬 필요가 없다는 장점이 있다.In the method of forming a fine resist pattern of the present invention, the modified layer does not develop in the developer because it does not react to the exposure light source through the step of injecting argon ions into the photosensitive layer, and absorbs light of a predetermined wavelength according to the amount of argon ions injected. In addition to being able to be used as an ARC layer, it is excellent in interfacial adhesion and is excellent in coating properties when double-coating a photosensitive agent thereon. Therefore, there is an advantage that there is no need to deposit an oxide layer that was needed in the TLR process.

이하 도면을 통해 본 발명을 보다 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도 2 는 기존의 TLR 을 본 발명의 미세 패턴 형성 방법으로 대체한 공정도이다. 도시된 바와 같이, 단차가 심한 기판(11)위에 피식각층(10)을 형성하고, 상기 피식각층상에 감광막(20)을 형성하고, (A) 상기 감광막(20) 상부에 아르곤 이온을 주입함으로써 개질된 감광막(30)을 형성시키고(B), 그 위에 감광막(40)를 도포한 다음(C), 노광 및 현상 공정을 통해 감광막(40) 패턴을 형성시키고(D), 상기 감광막(40) 패턴을 이용하여 개질된 감광막(30)과 감광막(20)을 식각시킨 후(E), 상기 피식각층(10)을 식각하여 (E)와 같은 패턴을 얻은 후, 상기 감광막(20,40)과 개질된 감광막(30)을 제거한다(F).2 is a process diagram in which the conventional TLR is replaced with the method for forming a fine pattern of the present invention. As shown, the etching target layer 10 is formed on the substrate 11 having a high level of difference, the photosensitive film 20 is formed on the etching target layer, and (A) an argon ion is implanted on the photosensitive film 20. The modified photosensitive film 30 is formed (B), the photosensitive film 40 is applied thereon (C), and then the photosensitive film 40 pattern is formed through an exposure and development process (D), and the photosensitive film 40 After etching the modified photosensitive film 30 and the photosensitive film 20 by using a pattern (E), the etching target layer 10 is etched to obtain the same pattern as (E), and then the photosensitive films 20, 40 and The modified photosensitive film 30 is removed (F).

도 3 은 본 발명을 이용한 기존의 바톰 ARC 대체 공정도이다. 여기에서는 기판(11)상에 재반사율이 높은 피식각층(10)위에 감광막를 얇게 도포한 후, 아르곤 주입 공정을 통해 감광제의 굴절률과 흡수율을 변화시켜 개질된 감광막(30)을 만든다(A). 2 차로 감광막(40)을 도포한 후, 노광과 현상공정을 거처 감광막(40) 패턴을 형성시킨 후(B), 아크 역할을 하는 개질 감광막(30)과 피식각층(10) 식각하여 (C)와 같은 패턴을 형성한다.Figure 3 is a conventional bottom ARC replacement process using the present invention. Here, after a thin coating of the photoresist on the etched layer 10 having a high re-reflection on the substrate 11, the modified photoresist 30 is made by changing the refractive index and the absorption of the photoresist through an argon implantation process (A). After applying the photoresist film 40 secondly, after forming the photoresist film 40 through exposure and development (B), the modified photoresist film 30 and the etched layer 10 serving as arcs are etched (C). Form a pattern like

도 4 는 본 발명의 미세 패턴 형성 방법에 따라서 실제로 감광제 표면의 일정부분을 아르곤 이온을 주입시킨 후, 톱 감광제를 도포한 후 패턴닝 시킨 도면이다.FIG. 4 is a view in which a portion of the surface of the photoresist is actually implanted with argon ions according to the method for forming a micropattern, and then patterned after application of a top photoresist.

본 발명의 미세 패턴 형성 방법에서 (b)아르곤 이온 주입처리 공정에서 바람직한 아르곤 이온 용량은 약 10x1015이온/cm2이하이며, 에너지는 약 50 MeV 이하이었다.In the method for fine pattern formation of the present invention, the argon ion capacity in the (b) argon ion implantation process is about 10x10 15 ions / cm 2 or less, and the energy is about 50 MeV or less.

또한 실험을 통해, 하기 표 1 에 나타낸 바와 같이 아르곤 이온의 주입 조건에 따라서 노광광의 굴절률과 흡수율이 변화됨을 확인하였다.In addition, through experiments, it was confirmed that the refractive index and the absorbance of the exposure light change according to the implantation conditions of argon ions as shown in Table 1 below.

[표 1]TABLE 1

주입 조건은 5 mA 전류에서 0°의 각도로 실시함.Injection conditions are performed at an angle of 0 ° at 5 mA current.

굴절률은 스펙트로엘립소미터로 측정함.Refractive index is measured by spectro ellipsometer.

데이터는 A + iB 로 나타냈고, 이 때에 A 는 굴절률을 나타내고, B 는 흡수율을 나타냄.Data is shown as A + iB, where A represents the refractive index and B represents the water absorption.

본 발명의 미세 패턴 형성 방법에서 (a) 감광막 도포 단계에서 감광제의 도포 두께는 약 3.0 ㎛ 이하인 것이 바람직하며, (c) 단계에서의 감광제 도포 두께는 약 1.0 ㎛ 이하인 것이 바람직하다. 또한, 바톰 ARC 로 사용할 때의 감광제의 도포 두께는 약 2.0 ㎛ 이하인 것이 바람직하다.In the method for forming a fine pattern of the present invention, the coating thickness of the photosensitive agent in the step (a) of the photosensitive film coating step is preferably about 3.0 μm or less, and the photosensitive agent coating thickness in the step (c) is preferably about 1.0 μm or less. In addition, it is preferable that the application thickness of the photosensitive agent at the time of use by bottom ARC is about 2.0 micrometers or less.

이상과 같이 본 발명에 따르는 미세패턴 형성 방법은, 기존의 TRL 공정을 간단히 대체할 수 있고, 감광제를 이용하여 바톰 ARC 로서 사용할 수 있으므로 공정의 단순화 및 결점 발생의 소지를 최소화할 수 있다.As described above, the method for forming a micropattern according to the present invention can simply replace the existing TRL process and can be used as the bottom ARC by using a photosensitive agent, thereby minimizing the simplification of the process and the occurrence of defects.

이상의 본 발명에 대한 상세한 설명 및 실시예는 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위안에서 다양한 수정, 변경, 부가등이 가능할 것이고, 이러한 수정 변경 등은 이하의 특허 청구의 범위에 속하는 것으로 보아야 할 것이다.The above detailed description and embodiments of the present invention have been disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and the like are defined in the following claims. Should be seen as belonging to.

Claims (3)

(a) 기판상에 형성된 피식각층 상에 제1감광막를 도포하는 단계와,(a) applying a first photoresist film on the etched layer formed on the substrate, (b) 상기 제1감광막상에 아르곤 이온을 주입처리하여 제1감광막 상부에 개질된 감광막을 형성하는 단계와,(b) implanting argon ions onto the first photoresist to form a modified photoresist on the first photoresist; (c) 상기 개질된 감광막 상에 제2감광막을 도포하는 단계와,(c) applying a second photoresist film on the modified photoresist film; (d) 상기 제2감광막을 노광 및 현상하여 제2감광막 패턴을 형성한 후, 식각 공정을 통해 피식각층 패턴을 형성하는 단계로 이루어짐을 특징으로 하여 미세패턴을 형성방법.(d) exposing and developing the second photoresist film to form a second photoresist pattern, and then forming an etched layer pattern through an etching process. 제 1 항에 있어서, (b)아르곤 이온 주입처리 공정에서 아르곤 이온 용량이 약 10x1015이온/cm2이하이며, 에너지는 약 50 MeV 이하임을 특징으로 하는 미세패턴 형성방법.2. The method of claim 1, wherein (b) the argon ion capacity in the argon ion implantation process is about 10x10 15 ions / cm 2 or less and the energy is about 50 MeV or less. 제 1 항에 있어서, (a) 감광막 도포 단계에서 감광제의 두포 두께가 약 3.0 ㎛ 이하이고, (c) 단계에서의 감광제 도포 두께가 약 1.0 ㎛ 이하임을 특징으로 하는 미세패턴 형성방법.The method of forming a micropattern according to claim 1, wherein (a) the thickness of the photosensitive agent in the photoresist coating step is about 3.0 µm or less, and the photoresist coating thickness in (c) is about 1.0 µm or less.
KR1019960079901A 1996-12-31 1996-12-31 Method for forming fine pattern by argon ion implantation process KR100422958B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157523A (en) * 1981-03-25 1982-09-29 Hitachi Ltd Forming method for pattern
JPH06349716A (en) * 1993-06-03 1994-12-22 Fujitsu Ltd Method for manufacturing x-ray mask
JPH08153714A (en) * 1994-09-30 1996-06-11 Sanyo Electric Co Ltd Etching method and production of semiconductor device
KR19980041069A (en) * 1996-11-30 1998-08-17 구자홍 Method for manufacturing mask for X-ray lithography

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157523A (en) * 1981-03-25 1982-09-29 Hitachi Ltd Forming method for pattern
JPH06349716A (en) * 1993-06-03 1994-12-22 Fujitsu Ltd Method for manufacturing x-ray mask
JPH08153714A (en) * 1994-09-30 1996-06-11 Sanyo Electric Co Ltd Etching method and production of semiconductor device
KR19980041069A (en) * 1996-11-30 1998-08-17 구자홍 Method for manufacturing mask for X-ray lithography

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