KR100422816B1 - Method for etching contact of semiconductor device - Google Patents
Method for etching contact of semiconductor device Download PDFInfo
- Publication number
- KR100422816B1 KR100422816B1 KR1019960025415A KR19960025415A KR100422816B1 KR 100422816 B1 KR100422816 B1 KR 100422816B1 KR 1019960025415 A KR1019960025415 A KR 1019960025415A KR 19960025415 A KR19960025415 A KR 19960025415A KR 100422816 B1 KR100422816 B1 KR 100422816B1
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- contact
- semiconductor device
- wafer
- interlayer dielectric
- Prior art date
Links
- 238000005530 etching Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005086 pumping Methods 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 안정된 플라즈마식각을 유도하여 균일한 콘택이 형성될수 있는 반도체 장치의 콘택식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a semiconductor device in which a uniform contact can be formed by inducing stable plasma etching.
일반적으로, 반도체 소자 제조공정중 기판과 전도선간의 접촉을 위한 콘택형성공정은 소자의 집적도가 증가함에 따라 고난이도 공정으로 부각된 것이 현재 반도체의 제조 실정이다.In general, the contact formation process for contact between the substrate and the conductive line during the semiconductor device manufacturing process is currently the manufacturing situation of the semiconductor has emerged as a high difficulty process as the degree of integration of the device increases.
또한, 상기 미세콘택 형성영역이 산화막으로 적층된 구조에서는 플라즈마 건식식각에 의한 에칭가스의 불균일 도포로 CD(Critical dimension) 값이 작아져 불균일한 콘택식각이 형성되어 콘택형성 공정의 제조수율을 저하시키고 있다.In addition, in the structure in which the microcontact formation region is laminated with an oxide film, CD (Critical dimension) value is reduced by non-uniform application of etching gas by plasma dry etching, resulting in non-uniform contact etching, thereby lowering the manufacturing yield of the contact forming process. have.
첨부된 제 1 도는 상기한 종래기술에 따른 반도체 장치의 콘택 식각방법에 대한 문제점을 도시한 것과 아울러 상세히 살펴보겠다.The accompanying drawings of FIG. 1 illustrate problems of the method for etching contacts of a semiconductor device according to the related art, and will be described in detail.
제 1 도에 도시한 바와 같이 실리콘기판(11)상에 게이트산화막(12), 게이트 형성용 폴리실리콘막(13)을 차례로 형성하고 소정크기로 게이트 전극을 패턴닝한 후, 소오스/드레인 영역을 형성하고(도시하지 않았음) 이어서, 기판 전체구조상에 층간절연의 목적으로 산화막(14)을 소정두께 형성하고 콘택 식각마스크인 포토레지스트(15) 패턴을 형성한 후, 콘택식각하여 기판 소정부위을 노출한다. 이때, 웨이퍼의 중앙(Center)영역에 위치한 소자와, 웨이퍼 가장자리(Edge)에 위치한 소자와의 식각선택비 및 CD BIAS(b-a)는 차이를 보인다.As shown in FIG. 1, a gate oxide film 12 and a gate forming polysilicon film 13 are sequentially formed on the silicon substrate 11, and the gate electrode is patterned to a predetermined size, and then source / drain regions are formed. (Not shown), and then a predetermined thickness of the oxide film 14 is formed on the entire structure of the substrate for the purpose of interlayer insulation. do. At this time, the etching selectivity and the CD BIAS (b-a) of the device located in the center region of the wafer and the device located at the edge of the wafer show a difference.
이것은, 소정의 에칭가스가 에칭장비내로 유입되어 웨이퍼 상단에서 샤워(Shower)형식으로 웨이퍼 중앙부위로 공급되고 식각장비의 주변부에서 상기 가스를 펌핑(Pumping)시키는 에칭장비의 특성으로 의하여 웨이퍼 중앙부위의 소자 식각은 반응하지 않은 에칭라디칼(Etching Radical)의 양이 상대적으로 적고, 화학적 반응에 따라 형성된 폴리머의 잔존시간이 길어져 재증착되기 때문이다.This is because a certain etching gas is introduced into the etching equipment and supplied to the center of the wafer in the form of a shower at the top of the wafer and pumped the gas at the periphery of the etching equipment. Etching is because the amount of unreacted etching radicals (Etching Radical) is relatively small, and the remaining time of the polymer formed by the chemical reaction is prolonged and redeposited.
따라서, 균일한 콘택 식각공정의 구현을 방해하는 문제점이 발생한다.Therefore, there is a problem that prevents the implementation of a uniform contact etching process.
상기한 문제점을 해결하기 위하여 안출된 본 발명은 균일한 콘택식각을 형성할수 있는 반도체 장치의 콘택 식각방법을 제공하는 것을 그 목적으로 한다.The present invention devised to solve the above problems is to provide a contact etching method of a semiconductor device capable of forming a uniform contact etching.
상기 목적을 달성하기 위하여 본 발명은 반도체 장치의 제조방법에 있어서,게이트 전극이 형성된 반도체 기판에 층간절연막을 형성하는 단계; 상기 층간절연막상에 콘택 식각마스크를 형성하는 단계; 및 300 ∼ 500 sccm 의 가스플로우양과 2500 ∼ 4000 L/S 인 펌핑량을 갖는 에칭가스를 이용하여 상기 층간절연막을 콘택식각하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor substrate on which a gate electrode is formed; Forming a contact etching mask on the interlayer insulating film; And contact etching the interlayer insulating film using an etching gas having a gas flow amount of 300 to 500 sccm and a pumping amount of 2500 to 4000 L / S.
이하, 첨부된 제 2 도를 참조하며 본 발명에 따른 반도체 장치의 콘택식각의 일실시예를 상세히 설명한다.Hereinafter, an embodiment of contact etching of a semiconductor device according to the present invention will be described in detail with reference to the accompanying FIG. 2.
제 2 도에 도시한 바와 같이, 실리콘 기판(21)상에 게이트산화막(22)을 50Å - 300Å 두께와 게이트 형성용 폴리실리콘막(23)을 2000Å - 4000Å의 두께로 차례로 형성하고 소정크기로 게이트 전극을 패턴닝한 후, 소오스/드레인 영역에 전도형 불순물을 이온주입한다.(도시하지 않았음) 이어서, 기판 전체구조 상에 층간절연의 목적으로 산화막(24)을 4000Å - 10000Å의 두께로 형성하고 콘택식각 마스크인 포토레지스트(25) 패턴을 형성한 후, 플라즈마 건식식각에 의한 콘택영역을 형성하여 기판 소정부위을 노출한다. 이때, 에칭장비내에 에칭가스인 CF4가스를 300 sccm - 500 sccm으로 고속으로 플로우시켜 에칭라디칼의 양을 충분히 공급하며 또한, 2500 L/S - 4000 L/S으로 고속펌핑으로 웨이퍼 상의 콘택형성 영역에 에칭부산물인 폴리머의 잔존시간을 최대한 단축시켜 균일한 콘택식각을 유도한다.As shown in FIG. 2, the gate oxide film 22 is formed on the silicon substrate 21 in a thickness of 50 kPa-300 kPa and the gate forming polysilicon film 23 is formed in a thickness of 2000 kPa-4000 kPa in order, and the gate is formed to a predetermined size. After the electrode is patterned, conduction impurities are implanted into the source / drain regions (not shown). Next, an oxide film 24 is formed to a thickness of 4000 kPa to 10000 kPa on the entire substrate structure for the purpose of interlayer insulation. After forming the photoresist 25 pattern, which is a contact etching mask, a contact region is formed by plasma dry etching to expose a predetermined portion of the substrate. At this time, CF 4 gas, which is an etching gas, is flowed at high speed from 300 sccm-500 sccm in the etching equipment to sufficiently supply the amount of etching radicals, and contact formation area on the wafer by high speed pumping at 2500 L / S-4000 L / S. The remaining time of the polymer as an etching by-product is shortened as much as possible to induce uniform contact etching.
따라서, 웨이퍼 상의 중앙부위와 가장자리가 균일한 식각선택비(Etch Rate). CD BIAS(b-a), 및 에칭 프로파일의 차이를 최소한으로 감소시킴에 따라 초미세 콘택홀을 형성하여 반도체 소자의 제조수율을 향상시킬 수 있는 효과가 있다.Thus, an Etch Rate with a uniform central portion and edges on the wafer. By reducing the difference between the CD BIAS (b-a) and the etching profile to a minimum, it is possible to form an ultra-fine contact hole to improve the manufacturing yield of the semiconductor device.
이상에서, 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가는함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are intended to be made without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in
제 1 도는 종래기술에 의한 반도체장치의 콘택 식각 공정단면도,1 is a cross-sectional view of a contact etching process of a semiconductor device according to the prior art,
제 2 도는 본 발명에 따른 반도체장치의 콘택 식각 공정단면도.2 is a cross-sectional view of a contact etching process of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21: 실리콘기판 22: 게이트산화막21: silicon substrate 22: gate oxide film
23: 폴리실리콘 24: 층간절연막23: polysilicon 24: interlayer insulating film
25: 포토레지스트25: photoresist
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025415A KR100422816B1 (en) | 1996-06-28 | 1996-06-28 | Method for etching contact of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025415A KR100422816B1 (en) | 1996-06-28 | 1996-06-28 | Method for etching contact of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR980005788A KR980005788A (en) | 1998-03-30 |
| KR100422816B1 true KR100422816B1 (en) | 2004-06-16 |
Family
ID=37329111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960025415A KR100422816B1 (en) | 1996-06-28 | 1996-06-28 | Method for etching contact of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100422816B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950030235A (en) * | 1994-04-11 | 1995-11-24 | 김광호 | Contact hole formation method of semiconductor device |
-
1996
- 1996-06-28 KR KR1019960025415A patent/KR100422816B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950030235A (en) * | 1994-04-11 | 1995-11-24 | 김광호 | Contact hole formation method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR980005788A (en) | 1998-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW201822275A (en) | Footing removal for nitride spacer | |
| KR100743873B1 (en) | Techniques for improving etching in a plasma processing chamber | |
| KR100353590B1 (en) | Dry etching treatment method and manufacturing method of semiconductor device | |
| JP2002520848A (en) | Two-step self-aligned contact etching | |
| JPH07193057A (en) | Method for plasma-etching either hole or opening part of high aspect ratio in substrate having siox layer thereon | |
| KR20050016077A (en) | Precise patterning of high-k films | |
| JP2005217240A (en) | Dry etching apparatus and method therefor | |
| KR100422816B1 (en) | Method for etching contact of semiconductor device | |
| KR100669560B1 (en) | Method for forming interconnect of semiconductor device | |
| KR100497609B1 (en) | Method of etching silicon nitride film | |
| KR100342393B1 (en) | a removing method of a photoresist pattern for a semiconductor device | |
| KR100267396B1 (en) | Gate polysilicon etch method for forming gate electrode of semiconuctor devices | |
| KR100283482B1 (en) | How to Form Plate Electrodes for Trench Capacitors | |
| KR100249012B1 (en) | Method for forming contact hole | |
| KR20050000970A (en) | Method of manufacturing semiconductor device | |
| KR20040003474A (en) | Method of forming contact of semicontactor device | |
| KR100431818B1 (en) | Forming method for self aligned contact of semiconductor device | |
| KR100652361B1 (en) | Method for fabricating a semiconductor device using self aligned contact | |
| KR20010003046A (en) | method for forming self-align contact hole in semiconductor device | |
| KR0166134B1 (en) | Forming method for gate electrode of semiconductor device | |
| KR0147713B1 (en) | Method for manufacturing thin film transistor | |
| KR100256798B1 (en) | Forming method of self-align contact of semiconductor devices | |
| JP2000100782A (en) | Manufacture of semiconductor device | |
| KR20000019101A (en) | Etching method of semiconductor device | |
| KR20000020614A (en) | Method for etching semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110222 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |