KR100422353B1 - A method for fabricating semiconductor device - Google Patents

A method for fabricating semiconductor device Download PDF

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Publication number
KR100422353B1
KR100422353B1 KR10-2001-0038566A KR20010038566A KR100422353B1 KR 100422353 B1 KR100422353 B1 KR 100422353B1 KR 20010038566 A KR20010038566 A KR 20010038566A KR 100422353 B1 KR100422353 B1 KR 100422353B1
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South Korea
Prior art keywords
opening
etching
insulating layer
semiconductor device
mask pattern
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KR10-2001-0038566A
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Korean (ko)
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KR20030002844A (en
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조성윤
전범진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

본 발명은 패드(pad)형성용 개구부 식각 시에 발생되는 마이크로트렌치The present invention provides a micro trench generated when etching an opening for forming a pad.

(microtrench)현상을 방지할 수 있는 반도체장치의 제조방법에 관해 개시한다.A method of manufacturing a semiconductor device capable of preventing microtrench phenomenon is disclosed.

개시된 본 발명의 반도체소자의 제조방법은 도전영역을 가진 반도체기판 상에 절연층을 형성하는 공정과, 절연층 상에 도전영역을 개구시키는 마스크패턴을 형성하는 공정과, 마스크패턴을 마스크로 하고, C4H8, CO, Ar 및 O2가스를 이용하여 상기 절연층을 식각하여 개구부를 형성하는 공정과, 마스크패턴을 마스크로 하고, CF4및 Ar가스를 이용하여 개구부를 식각하여 개구부의 바닥면을 평탄화시키는 공정과, 마스크패턴을 제거하는 공정을 포함한다.The disclosed method for manufacturing a semiconductor device of the present invention comprises the steps of forming an insulating layer on a semiconductor substrate having a conductive region, forming a mask pattern for opening the conductive region on the insulating layer, and using the mask pattern as a mask, Etching the insulating layer by using C 4 H 8 , CO, Ar, and O 2 gas to form an opening, using a mask pattern as a mask, and etching the opening using CF 4 and Ar gas to form an opening. And flattening the surface and removing the mask pattern.

Description

반도체장치의 제조방법{A method for fabricating semiconductor device}A method for fabricating semiconductor device

본 발명은 반도체장치의 제조방법에 관한 것으로, 보다 상세하게는 (pad)형성용 개구부 식각 시에 발생되는 마이크로트렌치(microtrench)현상을 방지할 수 있는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing microtrench phenomenon occurring when etching an opening for forming a pad.

일반적으로 알려진 바와 같이, 반도체가 고집적화되어 감에 따라 디자인 룰(design rule)이 서브-쿼터 미크론(sub-quater micron; 0.25㎛)으로 작아지고 있다. 따라서, 반도체소자의 패드/리페어(pad)(repair) 형성용 개구부 식각 시, 개구부의 폭이 좁아짐에 따라 발생되는 마이크로트렌치 현상을 최소화하는 연구가 진행되고 있다.As is generally known, as semiconductors are becoming highly integrated, design rules are becoming smaller with sub-quater microns (0.25 micrometers). Accordingly, studies are being conducted to minimize the micro trench phenomenon generated as the width of the opening becomes narrow when etching the opening for forming a pad / repair of the semiconductor device.

도 1a 내지 도 1b는 종래기술에 따른 반도체장치의 제조공정도이다.1A to 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

종래기술에 따른 반도체장치의 제조방법은, 도 1a에 도시된 바와 같이, 반도체기판(100) 상에 산화막을 화학기상증착하여 절연층(102)을 형성한다.In the method of manufacturing a semiconductor device according to the related art, as illustrated in FIG. 1A, an insulating layer 102 is formed by chemical vapor deposition of an oxide film on a semiconductor substrate 100.

상기 반도체기판(100)은 금속배선 등의 도전영역(미도시)이 형성되어져 있다.The semiconductor substrate 100 is formed with a conductive region (not shown) such as metal wiring.

이어서, 절연층(102) 상에 감광막(photoresist)를 도포한 다음, 노광 및 현상하여 상기 도전영역과 대응된 부분을 노출시키는 감광막패턴(104)을 형성한다.Subsequently, a photoresist is applied on the insulating layer 102, and then exposed and developed to form a photoresist pattern 104 that exposes a portion corresponding to the conductive region.

그 다음, 절연층(104) 상에 감광막패턴(104)을 식각마스크로 하여 C4H8, CO, Ar 및 O2가스를 공급(110)한다.Subsequently, C 4 H 8 , CO, Ar, and O 2 gas are supplied to the insulating layer 104 using the photoresist pattern 104 as an etching mask.

이때, 상기 식각공정은 MERIE(Magnetic Electro Reactive Iin Etch) 타입(type)의 식각 챔버(chamber) 내에서 진행되며, 상기 챔버 내에서 C4H8, CO, Ar 및 O2가스는 플라즈마 처리되어 절연층을 식각한다.In this case, the etching process is carried out in an etch chamber (MER) (Magnetic Electro Reactive Iin Etch) type (chamber) type, C 4 H 8 , CO, Ar and O 2 gas is plasma-treated in the chamber is insulated Etch the layer.

이 후, 도 1b에 도시된 바와 같이, 상기 가스 공급에 의해 절연층이 식각되어 도전영역을 개구시키는 개구부(T1)를 형성한다.Thereafter, as shown in FIG. 1B, the insulating layer is etched by the gas supply to form an opening T1 for opening the conductive region.

그리고 나서, 감광막패턴을 제거한다.Then, the photoresist pattern is removed.

그러나, 종래의 반도체장치의 제조방법에서는, 플라즈마 상태의 C4H8, CO,Ar 및 O2가스는 CW(Continuous Wave) 모드(mode)로, 펄스(pulse)를 사용하지 않기 때문에 전자(electron)활동이 대단히 활발하여 중성원소의 부착효과가 적어 실제 음이온 형성이 제대로 일어나지 않는다.However, in the conventional method of manufacturing a semiconductor device, C 4 H 8 , CO, Ar, and O 2 gases in a plasma state are in CW (Continuous Wave) mode, and do not use pulses. The activity is very active and the adhesion of neutral elements is small, so the formation of anions does not occur properly.

따라서, 이러한 전자는 감광막패턴과 개구부 측면에 전하 축적도를 높여, 도 2에 도시된 바와 같이, 개구부의 바닥면에 있어서, 중심부분과 에지부분 간에 단차가 발생되어 마이크로트렌치와 같은 손상이 발생된 문제점이 발생되었다.Accordingly, the electrons increase the degree of charge accumulation on the photoresist pattern and the side surface of the opening, and as shown in FIG. 2, a step is generated between the center portion and the edge portion of the bottom surface of the opening, thereby causing damage such as a micro trench. A problem has occurred.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 개구부 식각 시에 발생되는 마이크로트렌치 현상을 방지할 수 있는 반도체장치의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the micro trench phenomenon generated during etching of an opening.

도 1a 내지 도 1b는 종래기술에 따른 반도체장치의 제조공정도.1A to 1B are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2는 종래기술에 따른 문제점을 보이기 위한 도면.2 is a view for showing a problem according to the prior art.

도 3a 내지 도 3c는 본 발명에 따른 반도체장치의 제조공정도.3A to 3C are manufacturing process diagrams of a semiconductor device according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

200. 반도체기판 202. 절연층200. Semiconductor substrate 202. Insulation layer

204. 감광막패턴 T2. 개구부204. Photosensitive film pattern T2. Opening

210, 가스공급210, gas supply

상기 목적들을 달성하기 위한 본 발명의 반도체장치의 제조방법은 도전영역을 가진 반도체기판 상에 절연층을 형성하는 공정과, 절연층 상에 도전영역을 개구시키는 마스크패턴을 형성하는 공정과, 마스크패턴을 마스크로 하고, C4H8, CO, Ar 및 O2가스를 이용하여 상기 절연층을 식각하여 개구부를 형성하는 공정과, 마스크패턴을 마스크로 하고, CF4및 Ar가스를 이용하여 개구부를 식각하여 개구부의 바닥면을 평탄화시키는 공정과, 마스크패턴을 제거하는 공정을 포함한 것을 특징으로 한다.A semiconductor device manufacturing method of the present invention for achieving the above objects is a step of forming an insulating layer on a semiconductor substrate having a conductive region, the step of forming a mask pattern for opening the conductive region on the insulating layer, the mask pattern To form an opening by etching the insulating layer using C 4 H 8 , CO, Ar, and O 2 gas, and using the mask pattern as a mask, and opening the opening using CF 4 and Ar gas. And etching to planarize the bottom surface of the opening and removing the mask pattern.

또한, 본 발명은 ICP(Induced Coupled Plasma) 타입의 챔버에서, CF4및 Ar가스를 공급하면서, 음이온의 밀도를 높여 개구부의 바닥면에 축적된 차지를 중화시키어 마이크로트렌치 현상을 최소화시킨다.In addition, the present invention, while supplying CF 4 and Ar gas in the chamber of the ICP (Induced Coupled Plasma) type, by increasing the density of the anion to neutralize the charge accumulated in the bottom surface of the opening to minimize the micro-trench phenomenon.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3c는 본 발명에 따른 반도체장치의 제조공정도이다.3A to 3C are manufacturing process diagrams of a semiconductor device according to the present invention.

본 발명의 반도체장치의 제조방법은, 도 3a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 산화막을 화학기상증착하여 절연층(202)을 형성한다.In the method of manufacturing a semiconductor device of the present invention, as shown in FIG. 3A, first, an oxide layer is chemically vapor deposited on the semiconductor substrate 200 to form an insulating layer 202.

상기 반도체기판(200)은 금속배선 등의 도전영역(미도시)이 형성되어져 있다.The semiconductor substrate 200 is provided with a conductive region (not shown) such as metal wiring.

이어서, 상기 절연층(202) 상에 감광막을 도포한 다음, 노광 및 현상하여 도전영역과 대응된 부분을 개구시키는 감광막패턴(204)를 형성한다.Subsequently, a photoresist film is coated on the insulating layer 202 and then exposed and developed to form a photoresist pattern 204 for opening a portion corresponding to the conductive region.

그 다음, 절연층(202) 상에 감광막패턴(204)을 식각마스크로 이용하여 C4H8, CO, Ar 및 O2가스를 공급(210)한다.Next, C 4 H 8 , CO, Ar, and O 2 gas are supplied 210 using the photoresist pattern 204 as an etching mask on the insulating layer 202.

상기 식각 공정은 CIP 타입의 식각 챔버 내에서 진행된다.The etching process is performed in an etching chamber of the CIP type.

이 후, 도 3b에 도시된 바와 같이, 상기 가스 공급(210)에 의해 절연층이 식각되어 도전영역을 개구시키는 개구부(T2)가 형성된다.Thereafter, as illustrated in FIG. 3B, an opening layer T2 is formed by etching the insulating layer by the gas supply 210 to open the conductive region.

여기에서, 상기 가스공급(210)에 의해 형성된 개구부(T2)는 바닥면에 있어서, 도 3b에 도시된 바와 같이, 중심부분과 에지부분 간의 단차가 발생된다.Here, in the bottom surface of the opening T2 formed by the gas supply 210, as shown in FIG. 3B, a step between the center portion and the edge portion is generated.

따라서, 상기 개구부(T2)의 바닥면에 있어서, 중심부분과 에지부분에서의 단차를 해소하기 위하여, 감광막패턴(204)을 식각마스크로 이용하여 절연층(202)의개구부(T2)에 CF4및 Ar가스를 공급한다.Accordingly, in order to eliminate the step difference between the central portion and the edge portion in the bottom surface of the opening T2, CF 4 is formed in the opening portion T2 of the insulating layer 202 by using the photosensitive film pattern 204 as an etching mask. And Ar gas.

상기 가스 공급에 의한 식각 공정은 CIP 타입의 식각 챔버 내에서 진행된다.The etching process by the gas supply is performed in the CIP type etching chamber.

그 다음, 도 3c에 도시된 바와 같이, 상기 2차 가스 공급(212)에 의해, 개구부(T2) 내에 Ar+등의 양이온 뿐만 아니라, F-, CH3- 등의 음이온이 발생된다.Then, as shown in FIG. 3C, the secondary gas supply 212 generates not only cations such as Ar + but also anions such as F − and CH 3 − in the opening T2.

상기 음이온은 105∼107arb밀도를 가지며, 개구부(T2)의 바닥면에 축적된 차지를 중화시키어 마이크로트렌치 효과를 방지한다.The anion has a density of 10 5-10 7 arb and neutralizes the charge accumulated on the bottom surface of the opening T2 to prevent the micro trench effect.

따라서, 상기 음이온에 의해 개구부(T2)의 바닥면이 평탄화됨으로써, 단차가 해소된다.Therefore, the step is eliminated by flattening the bottom surface of the opening portion T2 by the anion.

이 후, 감광막패턴을 제거하고, 도 3c에 도시된 바와 같이, 바닥면이 평탄화된 반도체장치의 개구부(T2) 제조를 완료한다.Thereafter, the photoresist layer pattern is removed, and as illustrated in FIG. 3C, the opening T2 of the semiconductor device having the flattened bottom surface is completed.

본 발명에서는 CF4및 Ar가스를 이용하고, 소오스 및 바이어스의 주파수를 13.56MHz 로 하고, 게이트펄스를 10kHz로 가하게 되면, F-, CH3- 등의 음이온이 발생한다. 이때, 발생된 음이온이 개구부의 바닥면에 축적된 차지를 중화시키어 마이크로트렌치 효과를 방지하게 된다.In the present invention, when CF 4 and Ar gas are used, and the source and bias frequencies are 13.56 MHz and the gate pulse is 10 kHz, anions such as F- and CH 3 − are generated. At this time, the generated negative ions neutralize the charge accumulated on the bottom surface of the opening to prevent the micro trench effect.

이상에서와 같이, 본 발명의 반도체장치의 제조방법은 CF4및 Ar가스를 공급하고, 소오스 및 바이어스의 주파수를 13.56MHz 로 하고, 게이트펄스를 10kHz로 하여 식각 공정을 진행함으로써, 발생된 음이온이 개구부의 바닥면에 축적된 차지를중화시키어 마이크로트렌치 효과를 방지한다. 즉, 패드 형성용 개구부의 바닥면을 평탄하게 하여 마이크로트렌치 현상을 방지할 수 있다.As described above, in the method of manufacturing a semiconductor device of the present invention, an anion generated by supplying CF 4 and Ar gas, proceeding with an etching process with a source and bias frequency of 13.56 MHz and a gate pulse of 10 kHz is obtained. By neutralizing the charge accumulated on the bottom surface of the opening to prevent the micro trench effect. That is, the micro trench may be prevented by making the bottom surface of the pad forming opening flat.

따라서, 본 발명의 방법을 통해 소자의 특성 및 제품의 수율을 향상시킬 수 있다.Thus, the method of the present invention can improve the characteristics of the device and the yield of the product.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

도전영역을 가진 반도체기판 상에 절연층을 형성하는 공정과,Forming an insulating layer on the semiconductor substrate having a conductive region; 상기 절연층 상에 상기 도전영역을 개구시키는 마스크패턴을 형성하는 공정과,Forming a mask pattern for opening the conductive region on the insulating layer; 상기 마스크패턴을 마스크로 하고, C4H8, CO, Ar 및 O2가스를 공급하여 상기 절연층을 1차 식각하여 상기 도전영역을 노출시키는 개구부를 형성하는 동시에 상기 개구부는 중심부분과 에지부분에 단차가 발생되고 바닥면에는 전자가 축적되는 공정과,The mask pattern is used as a mask, and C 4 H 8 , CO, Ar, and O 2 gases are supplied to form an opening that exposes the conductive region by first etching the insulating layer. A step is generated at the bottom and electrons are accumulated at the bottom, 상기 마스크패턴을 마스크로 하고, CF4및 Ar가스를 공급하여 상기 개구부를 2차 식각하여 상기 개구부의 단차를 해소하는 동시에 상기 개구부 내에 F-및 CH3- 음이온을 발생시키는 공정과,Using the mask pattern as a mask, supplying CF 4 and Ar gas to etch the openings secondly to eliminate the step difference of the openings, and to generate F- and CH3- anions in the openings; 상기 음이온들의 밀도를 높여 상기 개구부의 바닥면에 축적된 차지를 중화시키는 공정과,Increasing the density of the anions to neutralize the charge accumulated on the bottom surface of the opening; 상기 마스크패턴을 제거하는 공정을 포함한 것을 특징으로 하는 반도체장치의 제조방법.And removing the mask pattern. 제 1항에 있어서, 상기 개구부 형성 및 상기 개구부의 평탄화 공정은 ICP타입의 식각장치 내에서 진행하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the opening and the planarization of the opening are performed in an ICP type etching apparatus. 제 1항에 있어서, 상기 2차 식각 공정은 소오스 및 바이어스의 주파수가 13.56MHz 이고, 10kHz의 게이트펄스를 사용하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the second etching process comprises a gate pulse of 10 kHz with a source and bias frequency of 13.56 MHz. 제 1항에 있어서, 상기 2차 식각 공정에서 상기 음이온은 105∼107arbThe method of claim 1, wherein the anion in said second etching step is a step 10 5 ~10 7 arb 의 밀도를 가진도록 하는 것을 특징으로 하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device, characterized by having a density of.
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