KR100421196B1 - Semiconductor memory apparatus that can surely attain discharge operation while reducing discharge period when reading operation is done - Google Patents

Abstract

The semiconductor memory device includes a plurality of memory cells MC1 to MC4; And a recording circuit 44. The recording circuit 44 performs a writing operation on the memory cell MC1. When the write operation is performed on the memory cell MC1, the first voltage is supplied to the write circuit 44. When the read operation is performed on the memory cell MC1, a second voltage equal to or less than the first voltage is supplied to the write circuit 44.

Description

Semiconductor memory apparatus that can surely attain discharge operation while reducing discharge period when reading operation is done}

The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a nonvolatile memory device.

In recent years, nonvolatile memory devices constituted by nonvolatile memory devices having floating gates have been actively developed. As shown in FIG. 1, a conventional nonvolatile memory device includes a word line W1, a word line W2, an X-decoder 41, a bit line B1, a bit line B2, and output signals Y1. Y2), sense amplifier 43, N-channel transistor N1, N-channel transistor N2, N-channel transistor N3, N-channel transistor N4, P-channel transistor P1 and It consists of a P-channel transistor P2.

The word line W1 is connected to the control gates of the memory cells MC1 and MC2. The word line W2 is connected to the control gates of the memory cells MC3 and MC4. The X-decoder 41 is connected to the word lines W1 and W2. The bit line B1 is connected to the drains of the memory cells MC1 and MC3. The bit line B2 is connected to the drains of the memory cells MC2 and MC4. Output signals Y1 and Y2 are connected to a Y-decoder 42. The sense amplifier 43 receives a pre-charge signal PRECH. The N-channel transistor N1 is connected to the bit line B1 and the sense amplifier 43, and receives the output signal Y1 from its gate. The N-channel transistor N2 is connected to the bit line B2 and the sense amplifier 43, and receives the output signal Y2 from its gate. The N-channel transistor N3 is connected to the bit line B1 and the GND power supply, and receives the discharge signal DIS from its gate. The N-channel transistor N4 is connected to the bit line B2 and the GND power supply, and receives the discharge signal DIS from its gate. The P-channel transistor P1 is connected to the bit line B1 and the VDD power supply and receives the input signal DW1 from its gate. The P-channel transistor P2 is connected to the bit line B2 and the VDD power supply, and receives the input signal DW2 from its gate.

Each of the memory cells MC1 to MC4 is a nonvolatile memory cell having a control gate and a floating gate. The threshold of the memory cell is controlled based on the amount of electrons sent to the floating gate.

For example, when electrons are injected into the floating gate, its threshold value VTM is high. For example, it is set to 6V. Also, if electrons are drawn from the floating gate, its threshold value VTM is lowered. For example, it is set to 2V.

Here, if the threshold value VTM of the memory cell is high (for example, VTM = 6V), the memory cell is sufficiently turned off even when a voltage for reading data stored in the memory cell, for example, 4V is applied to the word line. It is assumed that data "0" is stored in its memory cell. If the VTM is low (e.g., VTM = 2V) and the memory cell is sufficiently turned on, it is assumed that data "1" is stored in the memory cell.

The recording circuit 44 has P-channel transistors P1 and P2. It sets the input signal DW1 or DW2 to the low level during the write operation, and supplies the VDD power supply to the bit line B1 or B2 through the transistor P1 or P2.

The sense amplifier 43 receives a pre-charge signal PRECH. When the signal goes high, it supplies 1V to the N-channel transistors N1 and N2 as full-charge levels.

In this conventional example, the operation for reading the data stored in the memory cell is described below with reference to the timing charts of Figs. 2A to 2I.

By the way, it is assumed that data "0" is stored in the memory cells MC1 and MC2, and data "1" is stored in the memory cells MC3 and MC4. It is assumed that data is read from the memory cell MC1.

First, the bit lines B1 and B2 are discharged (section t1). Thus, the output signals Y1 and Y2 of the Y-decoder 42 are set to the low level, and the discharge signal DIS is set to the high level. The input signals DW1 and DW2 are set to high level. Thus, the N-channel transistors N1 and N2 are turned off. N-channel transistors N3 and N4 are turned on. P-channel transistors P1 and P2 are turned off. The bit lines B1 and B2 are set to the GND level.

Next, the selected bit line (here bit line B1) is pre-charged (section t2). Thus, the output signal Y1 is set at the high level, and the output signal Y2 is set at the low level. The pre-charge signal PRECH is set to the high level, and the discharge signal DIS is set to the low level. Accordingly, the N-channel transistors N2 to N4 are turned off and the N-channel transistor N1 is turned on. Therefore, 1 V, which means the full charge level, is supplied from the sense amplifier to the bit line B1 through the transistor N1.

Next, the voltage for performing the read operation is supplied to the word line (here, word line W1) of the selected memory cell, and sampling is performed (section t3). To do so, the pre-charge signal PRECH is set to a low level. The word lines W1 and W2 are switched to high level (eg 4V) and low level (eg 0V), respectively. Therefore, 1V is supplied to the drain of the memory cell MC1, and 4V is supplied to the control gate. Then, the stored data is sampled. Data "0" is stored in the memory cell MC1, and no current flows through the memory cell MC1. Therefore, the potential of the bit line is not changed and is maintained at 1V. The level as data "0" is detected by the sense amplifier 43. However, if data "1" is stored in the memory cell, current flows through the memory cell. Therefore, the potential of the bit line varies from 1V to 0.9V. The level changed as data "1" is detected by the sense amplifier 43. The operation for reading the memory cell MC1 is terminated in accordance with the above-described operations.

In the read operation, the potential of the bit line is once set to the GND level by the discharge operation. After that, it is pre-charged to 1V. Therefore, when data "1" is sampled, the time required for the potential change of the bit line from 1V to 0.9V is shortened so that the read operation can be made faster.

However, even in the discharging operation, the higher the potential of the bit line is, the longer the discharge time is required. Even if 4V is applied to the word line W1 at the sampling time of the memory cell MC1, the data "0" is stored in the memory cell MC2. Thus, memory cell MC2 is in the off-state. For this reason, if a leakage current exists in the P-channel transistor P2 of the recording circuit 44, the bit line B2 is charged by the leakage current during sampling of the memory cell MC1. Therefore, there is a possibility that the potential of the bit line B2 rises to the maximum VDD level. Further, since the data stored in the memory cell MC1 is at " 0 ", the memory cell MC1 is in the off-state. Therefore, the bit line B1 is similarly charged by the leakage current and may rise to the maximum VDD level. To read the memory cell MC2 after reading the memory cell MC1, the bit line is discharged (section t4). However, there is a possibility that the potential of the bit line B2 is 1 V or more, which means an expected value (over-discharge state). Therefore, in order to reliably discharge the bit line, it is necessary to make the discharge period longer. Therefore, the conventional nonvolatile memory device has a problem of inhibiting the speed of the read operation.

Japanese Patent Application Laid-Open (JP-A-Pyeong, 10-64289) discloses the following nonvolatile memory device. The nonvolatile memory device includes: a memory cell array provided with memory cells arranged in rows and columns; A row decoder having voltage transistor circuits for supplying a voltage to the control gates of the memory cells when data is written to the memory cells, wherein the number of voltage supply transistor circuits coincides with the number of columns and each voltage The supply transistor circuits are divided into a plurality of blocks, and the voltage supply force of the voltage supply transistor circuit in each block can be controlled based on the address given to the low decoder.

Japanese Patent Application Laid-Open (JP-A-Pyeong, 11-17519) discloses the following output buffer circuit. It consists of: an output drive buffer driven by an input signal; A transistor connected between the output terminal and the output end of the output drive buffer; A switch for connecting a gate electrode of the transistor to a power supply potential and releasing therefrom; A control circuit for generating a predetermined control signal from the input signal and outputting it from the output terminal; And a capacitance element connected between the gate electrode and the output end of the control circuit. When the input signal is changed, this control circuit once turns off the switch, turns it on after a predetermined period, charges the capacitive element when it is in the off-state, and switches on the transition from the off-state to the on-state. Therefore, the potential of the output terminal is inverted.

The present invention has been made because of the above problems. It is therefore an object of the present invention to provide a semiconductor memory device capable of sufficiently achieving a discharge operation while shortening a discharge period when a read operation is performed.

Still another object of the present invention is to provide a semiconductor memory device which can make a read operation faster.

1 is a circuit diagram showing a conventional semiconductor memory device;

FIG. 2A is a timing chart showing the potential of the discharge signal DIS in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2B is a timing chart showing the potential of the pre-charge signal PRECH in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2C is a timing chart showing the potential of the output signal Y1 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2D is a timing chart showing the potential of the output signal Y2 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2E is a timing chart showing the potential of the word line W1 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2F is a timing chart showing the potential of the word line W2 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2G is a timing chart showing the potentials of the input signals DW1 and DW2 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2H is a timing chart showing the potential of the bit line B1 in the read operation of the semiconductor memory device shown in FIG. 1;

FIG. 2I is a timing chart showing the potential of the bit line B2 in the read operation of the semiconductor memory device shown in FIG. 1;

3 is a circuit diagram showing a first embodiment of the present invention;

FIG. 4A is a timing chart showing the potential of the discharge signal DIS in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4B is a timing chart showing the potential of the pre-charge signal PRECH in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4C is a timing chart showing the potential of the output signal Y1 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4D is a timing chart showing the potential of the output signal Y2 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4E is a timing chart showing the potential of the word line W1 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4F is a timing chart showing the potential of the word line W2 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4G is a timing chart showing the potentials of the input signals DW1 and DW2 in the read operation of the semiconductor memory device shown in FIG. 3;

4H is a timing chart showing the potential of the read signal RD in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4I is a timing chart showing the potential of an inversion read signal RDB in the read operation of the semiconductor memory device shown in FIG. 3;

4J is a timing chart showing the potential of the gate electrode of the N-channel nondoped transistor in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4K is a timing chart showing the potential of the bit line B1 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 4L is a timing chart showing the potential of the bit line B2 in the read operation of the semiconductor memory device shown in FIG. 3;

FIG. 5 is a timing chart showing a circuit configuration of the first sensing amplifier in the embodiment shown in FIG. 3;

FIG. 6 is a circuit diagram showing a circuit configuration of a second sensing amplifier in the embodiment shown in FIG. 3;

7 is a circuit diagram showing a second embodiment of the present invention; And

8 is a circuit diagram showing a third embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

N1, N2, N3, N4, N5 ... N Channel Transistor N01 ... N channel non-transistor

P1, P2, P3, P4, P5 ... P Channel Transistors

MC1, MC2, MC3, MC4 ... non-volatile memory cells

B1, B2 ... bit line VW ... power

R1, R2 ... resistor 1,2,3,21,22 ... inverter

4,5,6,7,24,25,26,27 ... P channel transistor

8,9,10,11,12,28,29,30,31,32 ... N-channel transistor

In order to achieve one aspect of the present invention, a semiconductor memory device includes: a plurality of memory cells; And a write circuit for performing a write operation on the memory cell, wherein a first voltage is supplied to the write circuit when the write operation is performed on the memory cell, and a second below the first voltage when the read operation is performed on the memory cell. Voltage is supplied to the write circuit.

In this case, the semiconductor memory device includes: a plurality of memory cells connected to a plurality of bit lines; And a write circuit for performing a write operation on the memory cell, wherein a specific voltage is supplied to the write circuit when the read operation is performed on the memory cell, and the specified voltage is less than or equal to the voltage of the selected bit line when the read operation is performed.

In order to achieve another aspect of the present invention, a semiconductor memory device includes: a plurality of memory cells; A plurality of bit lines connected to the plurality of memory cells; A recording circuit connected to the plurality of bit lines; And an N-channel transistor for connecting a first power source to the recording circuit when the first operation is performed and connecting a second power source different from the first power source to the recording circuit when a second operation different from the first operation is performed.

In this case, the first electrode of the N-channel transistor is connected to the recording circuit, the second electrode of the N-channel transistor is connected to the specific power supply, and the first voltage corresponding to the first power supply and the first voltage corresponding to the second power supply are used. One of the two voltages is supplied to the control electrode of the N-channel transistor.

Also in this case, the N-channel transistor is an N-channel non-shift transistor.

Furthermore, in this case, the semiconductor memory device further comprises: a first transistor connected to the control electrode of the first power source and the N-channel transistor; And a second transistor connected to the control electrode of the second power supply and the N-channel.

In this case, the first and second transistors are of the same conductive type, where the read signal output when the read operation is performed on the memory cell is supplied to the control electrode of the first transistor, and the inverted signal of the read signal is provided. Is supplied to the control electrode of the second transistor.

Also in this case, the conductivity type of the first transistor is the opposite of the conductivity type of the second transistor, where the output read signal is supplied to the control electrodes of the first and second transistors when the read operation is performed on the memory cell. .

Further in this case, the recording circuit has a P-channel transistor provided between the N-channel transistor and the bit line.

In this case, the semiconductor memory device further includes: a first resistor connected between the first power supply and the second transistor; And a second resistor connected between ground and the second transistor.

Also in this case, the memory cell is a nonvolatile memory cell having a floating gate.

Furthermore, in this case, the second specific voltage corresponding to the second power supply is equal to or less than the first specific voltage corresponding to the first power supply.

In this case, the second operation is a read operation performed on the memory cell, and the first operation is one of operations other than the read operation.

Also in this case, the first operation is a recording operation performed on the memory cell.

Furthermore, in this case, the first specific voltage is the voltage of the selected bit line when the read operation is performed on the memory cell.

In this case, the specific voltage is supplied to the recording circuit so that the bit line is not charged above the specific voltage even if the bit line is charged by the leakage current output from the recording circuit.

Also, in this case, the second power supply may be a third transistor of a conductive type opposite to that of the first and second transistors connected to the second transistor, and a third power supply voltage to the third transistor in response to the read signal. And a second unit for supplying a voltage higher by a threshold voltage than the second power supply voltage to the control electrode of the third transistor in response to the first unit to be supplied and the read signal.

Further, in this case, the second power supply includes a third transistor of the same conductivity type as the second transistor connected to the second transistor, a first unit for supplying a third power supply voltage to the third transistor in accordance with the read signal, and a readout. And a second unit supplying a control electrode of the third transistor according to the signal to a voltage higher than the second power supply voltage by the threshold voltage of the third transistor.

In this case, the semiconductor memory device further includes: in the first mode, the read voltage is supplied to the plurality of bit lines, and in the second mode, the bit is based on whether the memory cell is in the conductive state or the non-conductive state. A sense amplifier connected to a plurality of bit lines for detecting a voltage change of the line.

Also in this case, the sense amplifier includes a current mirror circuit for sensing the voltage level of the bit line, a third unit for outputting a read voltage to the bit line, and a current mirror when the pre-charge signal is at the first level. And a fourth unit for activating the circuit and deactivating the third unit, deactivating the current mirror circuit and activating the third unit when the pre-charge signal is at a second level different from the first level.

Hereinafter, with reference to the accompanying drawings, an embodiment of a semiconductor memory device of the present invention will be described.

The semiconductor memory device of the present invention has the following features. That is, the power supply of the recording circuit 44 connected to the bit line in the read operation is set below the bit line potential in the read operation. Thus, the bit line can be prevented from being overcharged due to the leakage current from the recording circuit 44. Therefore, the discharge time of the bit line can be shortened to a minimum.

In FIG. 3, the N-channel non-doped transistor NO1 is installed between the P-channel transistors P1 and P2 and the terminal to supply a power supply potential VDD (for example, 5V), and the input signal RDB. The P-channel transistor P4 for receiving) from its gate is provided between the second sense amplifier 45 and the contact NOG serving as the gate input of the N-channel non-transistor transistor NO1.

In the read operation, 1V equal to the potential of the selected bit line B1 or B2 is output as the output signal SO of the second sense amplifier 45, and the input signal RDB is at a low level. Thus, 1V is supplied to the contact NOG. Since the threshold of the N-channel non-transistor transistor is 0V, 1V is also supplied to the power supply VW of the recording circuit 44. In addition, since the input signals DW1 and DW2 are at a high level, the P-channel transistors P1 and P2 are turned off. If a leakage current flows through the P-channel transistor P1 or P2 to charge the bit line, its potential is raised only to 1V equal to the potential of the selected bit line.

Thus, the bit lines B1 and B2 can be prevented from being overcharged due to the leakage current of the P-channel transistors P1 and P2 in the recording circuit 44. Further, when the read operation is performed, it is necessary to first set the bit lines B1 and B2 to the GND level by using the N-channel transistors N3 and N4. However, since the bit line is not overcharged, the discharge period can be shortened to a minimum.

However, leakage occurring in the P-channel transistor P1 or P2 is a sub-threshold leakage and / or a junction leak. Today, the presence of such leaks cannot be eliminated due to the development of microstructures.

In addition, the off-leak of the N-channel non-shift transistor NO1 can be essentially ignored. This is because the off-leak of an N-channel transistor is several times smaller than the off-leak of a P-channel transistor. When 1V is supplied to the gate NOG of the transistor NO1, the level of the line VW is 1V. When leakage occurs at transistor NO1 at that point, the voltage between the gate and the source of transistor NO1 increases in the negative direction (ie, the voltage at gate NOG is 1V, but the voltage at line VW 1V or more). Therefore, the leakage current of the transistor NO1 drops significantly. On the other hand, in the conventional semiconductor device shown in Fig. 1, the transistor P2 is a P-channel transistor. Even if leakage occurs in the transistor, the voltage between the gate and the source does not change (i.e., a high level (e.g. 5V) is supplied to the gate and VDD (e.g. 5V) is supplied to the source). Therefore, the leakage amounts of the transistors P1 and P2 do not change. Therefore, the leakage current of the conventional transistors P1 and P2 is incomparably larger than the leakage current in the device of the present invention.

3 shows a first embodiment of a semiconductor memory device of the present invention.

The semiconductor memory device of this embodiment has memory cell arrays each equipped with a plurality of memory cells to be arranged in a matrix form. 3 shows nonvolatile memory cells MC1-MC4 that are part of memory cell arrays. The word line W1 is connected to the control gates of the memory cells MC1 and MC2. The word line W2 is connected to the control gates of the memory cells MC3 and MC4. An X-decoder for receiving the address AD is connected to the word lines W1 and W2. The bit line B1 is connected to the drains of the memory cells MC1 and MC3. The bit line B2 is connected to the drains of the memory cells MC2 and MC4. Each of the sources of the memory cells MC1-MC4 is connected to a source power circuit composed of a P-channel transistor P45 and an N-channel transistor N45. The inversion erase signal ERASE_B is sent to the gates of the transistors P45 and N45. A VPP power supply (e.g., 10V) is supplied to the source of transistor P45. The Y-decoder 42 receives the address signal AD and drives the output signals Y1 and Y2 in response to the signal. The first sensing amplifier 43 receives the pre-charge signal PRECH and the read signal RD. The first sensing amplifier 43 drives the node S1 to 1V when the pre-charge signal PRECH is at a high level under the condition that the read signal RD is at a high level, and the pre-charge signal PRECH is applied to the first sense amplifier 43. When the level is low, the level of the node S1 is sensed, and then the result is output as the output signal Sout. The N-channel transistor N1 is connected between the bit line B1 and the node S1 and receives the output signal Y1 from its gate. The N-channel transistor N2 is connected between the bit line B2 and the first sense amplifier 43, and receives an output signal Y2 from its gate. The N-channel transistor N3 is connected between the bit line B1 and the GND power supply and receives a discharge signal DIS from its gate. The N-channel transistor N4 is connected between the bit line B2 and the GND power supply, and receives a discharge signal DIS from its gate. The P-channel transistor P1 is connected between the bit line B1 and the power supply VW of the write circuit 44, and receives the write signal DW1 from its gate. The P-channel transistor P2 is connected between the bit line B2 and the power supply VW and receives the write signal DW2 from its gate. Transistors P1 and P2 constitute a write circuit 44. An N-channel non-transistor transistor N01 is connected between the P-channel transistors P1 and P2 and the VDD power supply (for example, 5V), and receives a contact NOG from its gate. The threshold value VTNO of the N-channel non-shift transistor NO1 is assumed to be 0V. The P-channel transistor P3 is connected between the VDD power supply and the contact NOG, and receives a read signal RD from its gate. The P-channel transistor P4 is connected between the contact NOG and the output signal SO of the second sense amplifier 45 and receives an inverted output signal RDB from its gate. The second sensing amplifier 45 is a circuit which receives the read signal RD and outputs, for example, 1V when the read signal RD is at a high level.

In the read operation, the P-channel transistor P4 receives the low level read signal RDB, and thus supplies the potential of the output signal SO of the second sense amplifier 45 to the contact point NOG. At this time, the high level read signal RD is sent to the gate of the transistor P3. Thus, it is in the off-state.

In the case of an operation such as a write operation except for the read operation, for example, during the write operation, the P-channel transistor P3 receives the low level read signal RD, and thus supplies the VDD potential to the contact NOG. . At this time, the write signal DW1 or DW2 is set to the low level so that the VDD level of the power supply VW is applied to the bit line B1 or B2 through the P-channel transistor P1 or P2 of the recording circuit 44. Supplied.

In the erase operation, the inversion erase signal ERASE_B goes low and the VPP potential is supplied to the sources of the memory cells MC1-MC4. In cases other than the erase operation, the inversion erase signal ERASE_B goes high and the GND potential (eg, 0V) is supplied to the sources of the memory cells MC1-MC4.

Here, if the memory cell is sufficiently turned off even when the threshold value VTM of the memory cell is high and a voltage for reading data stored in the memory cell = 4V is supplied to the word line, it is assumed that the data "0" is stored in the memory cell. . If the memory cell is sufficiently turned on because VTM (VTM = 2V) is low, it is assumed that data "1" is stored in the memory cell.

An operation for reading data stored in a memory cell according to an embodiment of the present invention is described below with reference to timing charts in Figs. 3, 4A-4L. 4A to 4L show timing charts when data stored in the memory cell MC1 is read. By the way, it is assumed that data "0" is stored in the memory cells MC1 and MC2, and data "1" is stored in the memory cells MC3 and MC4. At this time, since the high level read signal RD is sent, the second sense amplifier 45 has the same potential as the output signal SO at the selection state of the bit lines B1 and B2 as the output signal SO during the read operation. Outputs The high level read signal RD is also sent to the first sensing amplifier 43. Since the inversion erase signal ERASE_B is at a high level, the GND potential is supplied to the sources of the memory cells MC1-MC4. In addition, the read signal RD is at the high level, and the inverted read signal RDB is at the low level. Thus, the P-channel transistors P3 and P4 are turned off and turned on, respectively. 1V is supplied to the contact NOG. 1V is supplied to the power supply VW of the recording circuit 44 through the N-channel non-transistor transistor NO1. The input signals DW1 and DW2 are at a high level to turn off the transistors P1 and P2.

First, the bit line is discharged (section t1 in Figs. 4A to 4L). The output signals Y1 and Y2 of the Y-decoder 42 are initially set to the low level, and the discharge signal DIS is set to the high level. Accordingly, the N-channel transistors N1 and N2 are turned off, and the N-channel transistors N3 and N4 are turned on. P-channel transistors P1 and P2 are turned off. Thus, the bit lines B1 and B2 are set to the GND level.

Next, the selected bit line is pre-charged (interval t2 in FIGS. 4A-4L). In order to read the data stored in the memory cell MC1, the output signal Y1 is set to the high level to pre-charge the bit line B1, the output signal Y2 is set to the low level, and the pre- The charging signal PRE is set to a high level and the discharge signal DIS is set to a low level. Thus, the N-channel transistors N2-N4 are turned off and the N-channel transistor N1 is turned on. Therefore, 1 V, which means the full-charge level, is supplied from the first sense amplifier 43 to the bit line B1.

Next, the voltage for performing the read operation is supplied to the word line of the selected memory cell, and sampling is performed (section t3 in Figs. 4A to 4L). In order to read the data stored in the memory cell MC1, the pre-charge signal PRECH is set to the low level. The word lines W1 and W2 are set to 4V and 0V, respectively. Therefore, 1V is supplied to the drain of the memory cell MC1, and 4V is supplied to the control gate. Then, the stored data is sampled. Since data "0" is stored in the memory cell MC1, no current flows through the memory cell MC1. Therefore, the bit line is kept at 1V. The first sensing amplifier 43 detects the potential 1V of the bit line B1 and outputs the result as an output signal Sout. By the way, when data "1" is stored in the memory cell, current flows through the memory cell. Therefore, the potential of the bit line varies from 1V to 0.9V. The first sensing amplifier 43 outputs a result based on the potential change.

The read operation in the memory cell MC1 is terminated in accordance with the above-described operations.

When the data "1" is sampled in the read operation, if the potential of the bit line is higher than necessary, the time required when the potential of the bit line changes to 0.9V is extended. Thus, the potential of the bit line is once set to the GND level by the discharge operation. After that, it is pre-charged to 1V. However, if the potential of the bit line is higher than necessary, it is necessary to extend the discharge period even in the discharge operation. When the memory cell MC1 is sampled, 4V is applied to the word line W1. However, since data "0" is stored in the memory cell MC2, the memory cell MC2 is in the off-state. If at this time a leakage current exists in the P-channel transistor P2 of the recording circuit 44, the bit line B2 is charged by the leakage current during sampling of the memory cell MC1. However, since the power supply VW is at 1 V, the voltage of the bit line B2 is raised only to 1 V which is equal to the potential of the bit line selected for performing the read operation. For this reason, the bit line B2 is discharged to read the memory cell MC2 after reading the memory cell MC1 (section t4 in Figs. 4A-4L). However, since the potential of the bit line B2 is 1 V, which means an expected value, the bit line can be discharged during the original discharge period.

As described above, in the read operation, the power supply of the write circuit 44 connected to the bit line is set at or below the potential of the selected bit line in the read operation. Therefore, even if a leakage current flows from the recording circuit 44, overcharging of the bit lines can be prevented. Therefore, the discharge period of the bit line is shortened to a minimum. Therefore, the read operation can be faster without any increase in the discharge period.

The erase operation is described below. The transistors N1, N2, P1, and P2 set the output signals Y1, Y2 of the Y-decoder 42 to a low level, and the signals DW1 and DW2 of the write circuit 44 to a high level. Turn it off. Since the pre-charge signal PRECH goes high and the read signal RD goes low, the N-channel transistor N10 is turned off and the bit lines B1 and B2 become floating. The inversion erase signal ERASE_B goes low and the VPP level is supplied to the sources of the memory cells MC1-MC4. The GND potential is supplied to the word lines W1 and W2. The above-described operations can cause the VPP level to be supplied to respective sources of the memory cells MC1-MC4. Since the drain is in the floating state, the GND level is supplied to the gate, and the erase operation is performed in each of the memory cells MC1-MC4. For example, the thresholds VTM of the memory cells MC1-MC4 are reset to 2V (data "1"). However, since the read signal RD is at the low level at this time, the transistor P3 is turned on and the VDD potential is supplied to the node NOG.

The recording operation is described below. Here, an operation for recording data "1" in the memory cell MC1 is described as an example. Since the inverted erase signal ERASE_B is at a high level, the transistor N45 is turned on and the GND potential is supplied to the sources of the memory cells MC1-MC4. Both output signals Y1 and Y2 of the Y-decoder 42 change to the low level, and the discharge signal DIS changes to the low level. Since the read signal RD is at the low level, the VDD level is supplied to the node NOG, and the power supply VW is at the VDD potential. Since the signal DW1 of the recording circuit 44 goes low and the signal DW2 goes high, the VDD level is supplied to the bit line B1. In addition, the word line W1 is changed to the VPP level. Therefore, the VPP level is supplied to the gate of the memory cell MC1, the GND level is supplied to its source, and the VDD level is supplied to its drain. Therefore, the threshold value VTM of the memory cell MC1 becomes 6V, and the data "0" is written there.

FIG. 5 is a diagram showing the circuit configuration of the first sensing amplifier 43 shown in FIG.

The inverter 1 receives the read signal RD and outputs its inverted signal. The P-channel transistor P14 receives the output of the inverter 1 from its gate and the VDD power is supplied to its source. The N-channel transistor N8 receives the output of the inverter 1 from its gate, the GND power supply is supplied to its source, and its drain is connected to the drain of the transistor 14. The inverter 2 receives the pre-charge signal PRECH and outputs an inverted signal. The VDD power supply is supplied to the source of the P-channel transistor P15, and the output of the inverter 2 is sent to its gate. The gate of the P-channel transistor P6 is connected to the drain of the transistor 15, the VDD power source is supplied to its source, and its drain is connected to its gate. The gate of the N-channel transistor N10 is connected to the drain of the transistor 14 and is connected between the transistor 6 and the node S1. The gate of the transistor 9 is connected to the node S1, the VDD power source is supplied to its source, and the drain thereof is connected to the drain of the transistor 14. The gate of the P-channel transistor P7 is connected to the drain of the transistor 15, and its source is connected to the VDD power supply. The related voltage is supplied to the gate of the N-channel transistor N11, and the drain thereof is connected to the drain of the transistor 7. The VDD power supply is supplied to the gate of the transistor 12, the GND power supply is supplied to its source, and the drain thereof is connected to the source of the transistor 11. The input of the inverter 3 is connected to the drain of the transistor 7, which outputs an output signal Sout indicating the sensed result. The biases of each transistor are as shown in the figures.

The first detection amplifier 43 performs a pre-charge operation when the pre-charge signal PREC is at a high level under the condition that the read signal RD is at a high level, and the pre-charge signal PRECH is performed. It is a circuit to perform the sensing operation at the low level. Those operations are described in detail below. However, both the pre-charging operation and the sensing operation are read operations. Therefore, the read signal RD is maintained at a high level in both operation periods. Therefore, in the pre-charge operation and the sensing operation, the transistor 14 is always in the on-state, and the transistor 8 is always in the off-state.

In order to perform the pre-charge operation, the pre-charge signal PRECH is switched to the high level. This causes the low level to be supplied to the gate of transistor 15 so that transistor 15 is turned on and the VDD potential is supplied to the drain of transistor 10. At this time, the gate potential of the transistor 10 is determined by the ratio between the transistor 14 and the transistor 9. Therefore, the gate width W / gate length L of each transistor is set so that the gate potential is equal to (1V + VTN) (VTN is the threshold of the N-channel transistor). Therefore, the transistor 10 outputs a potential of 1V to the node S1.

Next, in order to perform the sensing operation, the pre-charge signal PRECH is switched to the low level. Since the high level is supplied to the gate of the transistor 15, the transistor 15 is turned off. Thus, the current mirror circuit is constituted by transistors 6 and 7. The gate potentials of the transistors 6 and 7 change depending on whether or not current flows through the selected memory cell. Moreover, the transistor 7 is set such that current flows through the transistor 7 in an amount of four times that of the transistor 6, for example. For this reason, if a current flows through the selected memory cell, the gate potential of the transistor 7 falls so that a current four times as large as the current of the transistor 6 flows through the transistor 7. Therefore, the input potential of the inverter 3 rises, and the output Sout becomes low level, that is, data "1" is output. Transistors 11 and 12 function as current sources. The reference voltage is set so that the output Sout becomes a low level when current flows through the selected memory cell. On the other hand, if the current does not flow through the selected memory cell, the amount of current flowing through the transistor 11 is greater than the amount of current flowing through the transistor 7. Therefore, the input potential of the inverter 3 falls. Therefore, the output Sout becomes high level, that is, data "0" is output.

FIG. 6 is a diagram illustrating a circuit configuration of the second sensing amplifier 45 shown in FIG. 3. In the second sense amplifier 45, the inputs of the inverters 21, 22 receive a read signal RD as compared to the first sense amplifier 43 of FIG. 1. The drain of the transistor 30 is connected to the transistor P24, that is, the node SO. Therefore, the inverter 3 is not installed. The configuration other than the above-described structure is the same as that of the first sensing amplifier 43 of FIG. Therefore, the description thereof is omitted.

Since the high level read signal RD is sent in the read operation, the second sense amplifier 45 supplies 1V to the node SO similarly to the first sense amplifier 43 in FIG. Since the low level read signal RD is sent except in the case of the read operation, the second sense amplifier 45 does not supply 1V to the node SO. However, the second sensing amplifier 45 does not require a sensing operation. Thus, the transistors 27, 31 and 32 can be omitted.

7 is a view showing a second embodiment of the semiconductor memory device according to the present invention. In FIG. 7, the same reference numerals are given to the parts similar to those in the first embodiment of the present invention shown in FIG.

This embodiment includes: a resistor R1 connected to a VDD power supply and a contact RO; A resistor R2 connected to the contact RO and the GND power supply; A P-channel transistor P3 connected to the VDD power source and the contact NOG and receiving an input signal RD from its gate; And an N-channel transistor N5 connected to the contact NOG and the contact RO and receiving an input signal RD from its gate. Other configurations are the same as those of the apparatus of FIG. So, its explanation is omitted.

Operation in this embodiment is described below.

In this embodiment, during the read operation, the input signal RD is set to high level. Therefore, the voltage at the contact RO is supplied to the contact NOG through the N-channel transistor N5.

Here, the potential VRO of the contact RO is defined as follows:

VRO = VDD X R2 / (R1 + R2).

Thus, the resistance values of the resistors R1 and R2 determine that VRO becomes 1 V or less, which means the potential of the bit lines B1 and B2 during the read operation.

Therefore, the voltage of the power supply VW of the write circuit 44 is VRO during the read operation. Therefore, even if a leakage current exists in the P-channel transistor P1 or P2 of the recording circuit 44, the voltage of the bit line B1 or B2 is 1 V or less indicating an expected value when a read operation is performed. Thus, the bit line can be discharged during the original discharge period.

8 is a view showing a third embodiment of the semiconductor memory device according to the present invention. In Fig. 8, parts similar to those of the first embodiment of the present invention of Fig. 3 are given the same reference numerals.

This embodiment is equipped with: a resistor R1 connected to the VDD power supply and the contact RO; A resistor R2 connected to the contact RO and the GND power supply; A P-channel transistor P3 connected to the VDD power source and the contact NOG and receiving an input signal RD from its gate; And a P-channel transistor P5 connected to the contact NOG and the contact RO and receiving an inverting input signal RDB from its gate. Other configurations are the same as those of the apparatus of FIG. So, its explanation is omitted.

In this embodiment, the input signal RD is set to the high level in the read operation. Therefore, the voltage at the contact RO is supplied to the contact NOG via the P-channel transistor P5.

Here, the potential VRO of the contact RO is defined as follows:

VRO = VDD X R2 / (R1 + R2).

Thus, the resistance values of the resistors R1 and R2 are determined so that VRO becomes 1 V or less, which means the potential of the bit lines B1 and B2 during the read operation.

Therefore, the voltage of the power supply VW of the write circuit 44 is VRO during the read operation. Therefore, even if a leakage current exists in the P-channel transistor P1 or P2 of the recording circuit 44, the voltage of the bit line B1 or B2 is 1 V or less, which means an expected value when a read operation is performed. Thus, the bit line can be discharged during the original discharge period.

However, the present invention is not limited to the above-described embodiments. Various modifications are possible without departing from the spirit and scope of the invention.

As described above, the power supply of the recording circuit 44 connected to the bit line in the read operation is set below the potential of the selected bit line in the read operation. Therefore, even if a leakage current flows from the recording circuit 44, overcharging of the bit lines can be prevented. Therefore, the discharge period of the bit line can be shortened to a minimum. Therefore, the read operation can be performed more quickly without any increase in the discharge period.

Claims (20)

delete A plurality of memory cells connected to the plurality of bit lines; And A write circuit connected to said plurality of bit lines and performing a write operation on said memory cell, And when a read operation is performed on the memory cell, a specific voltage is supplied to the write circuit, and the specific voltage is lower than the voltage of the bit line selected when the read operation is performed. A plurality of memory cells; A plurality of bit lines connected to the plurality of memory cells; A recording circuit connected to the plurality of bit lines; And N for connecting a first power source to the recording circuit when a first operation is performed, and connecting a second power source different from the first power source to the recording circuit when a second operation different from the first operation is performed. A channel transistor, wherein when the read operation is performed on the memory cell, the N-channel transistor supplies a specific voltage to the write circuit, and the specific voltage is the voltage of the bit line selected when the read operation is performed. Lower semiconductor memory. The first voltage of claim 3, wherein a first electrode of the N-channel transistor is connected to the recording circuit, a second electrode of the N-channel transistor is connected to a specific power source, and a first voltage corresponding to the first power source. And a second voltage corresponding to the second power supply is supplied to the control electrode of the N-channel transistor. The semiconductor memory device according to claim 4, wherein the N-channel transistor is an N-channel non-doped transistor. The method according to claim 4 or 5, A first transistor connected to the first power source and the control electrode of the N-channel transistor; And And a second transistor connected to the second power supply and the control electrode of the N-channel transistor. The method of claim 6, wherein the first and second transistors are of the same conductivity type as each other, The read signal output when the read operation is performed on the memory cell is supplied to the control electrode of the first transistor, And an inverted signal of the read signal is supplied to the control electrode of the second transistor. The method of claim 6, wherein the conductivity type of the first transistor is the opposite of the conductivity type of the second transistor, And a read signal output when the read operation is performed on the memory cell is supplied to the control electrodes of the first and second transistors. The semiconductor memory device according to claim 4, wherein the writing circuit includes a P-channel transistor provided between the N-channel transistor and the bit line. The method of claim 6, A first resistor connected between the first power supply and the second transistor; And And a second resistor connected between ground and the second transistor. 4. The semiconductor memory device according to claim 3, wherein the memory cell is a nonvolatile memory cell having a floating gate. 4. The semiconductor memory device according to claim 3, wherein a second specific voltage corresponding to the second power supply is equal to or less than a first specific voltage corresponding to the first power supply. 4. The semiconductor memory device according to claim 3, wherein the second operation is a read operation performed on the memory cell, and the first operation is one of operations other than the read operation. The semiconductor memory device according to claim 13, wherein said first operation is a writing operation performed on said memory cell. The semiconductor memory device according to claim 12, wherein the second specific voltage is lower than a voltage of a selected bit line when a read operation is performed on the memory cell. The semiconductor memory device according to claim 2, wherein the specific voltage is supplied to the recording circuit so that the bit line is not charged above the specific voltage even when the bit line is charged by a leakage current output from the writing circuit. The semiconductor device of claim 7, wherein the second power supply comprises: a third transistor of a conductive type opposite to the conductive type of the first and second transistors connected to the second transistor, and the third signal in response to the read signal. A first unit supplying a third power supply voltage to a transistor and a second supplying voltage higher than the second power supply voltage to the control electrode of the third transistor by the threshold voltage of the third transistor in response to the read signal; A semiconductor memory device having a unit. 9. The second power supply of claim 8, wherein the second power supply supplies a third power supply voltage to the third transistor in response to the readout signal and a third transistor of the same conductivity type as the second transistor connected to the second transistor. And a second unit supplying a control electrode of the third transistor to a control electrode of the third transistor in response to a read signal, the voltage being higher than the second power supply voltage by the threshold voltage of the third transistor. The method of claim 3, The plurality of bit lines for supplying a read voltage to the plurality of bit lines in a first mode and detecting a voltage change of the bit line based on whether the memory cell is in a conductive state or a non-conductive state in a second mode. And a sensing amplifier connected to the semiconductor memory device. 20. The apparatus of claim 19, wherein the sensing amplifier comprises: a current mirror circuit for sensing the voltage level of the bit line, a third unit for outputting the read voltage to the bit line, and the current when the pre-charge signal is at the first level. And a fourth unit for activating a mirror circuit and deactivating the third unit, deactivating the current mirror circuit and activating the third unit when the pre-charge signal is at a second level different from the first level. Semiconductor memory device.