JPH03150794A - Nonvolatile semiconductor storage - Google Patents

Abstract

PURPOSE:To attain a high-speed reading operation even with a slight cell current by using a flip-flop type sense amplifier. CONSTITUTION:A flip-flop type sense amplifier 8 consists of transistors Q4 - Q9. A normal sense amplifier, e.g., an inverter reads out data on the boundary of the set logical threshold value, e.g., 2.5V. That is, the output data are inverted when the input of an amplifier is changed to 2.5V from 0V or to 2.5V from 5V. Therefore the input of the amplifier must change by 2.5V for inversion of the output data of the sense amplifier. Meanwhile the amplifier 8 can satisfac torily read out the data with about several hundreds of mV required for the difference between two inputs since the input having a higher voltage level is set at 5V with the other input of a lower voltage leve set at 0V respectively. As a result, the input has no large change and the data can be read out at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reading method for an electrically rewritable nonvolatile semiconductor memory device.

[Conventional technology]

FIG. 2 is a circuit diagram showing the basic configuration regarding reading of a conventional nonvolatile semiconductor memory device. In the figure, the drain of the transistor Ql is connected to the bit line 1, the gate is connected to the word line 2, and the source is connected to the drain of the memory transistor M1. The control gate of memory transistor M1 is connected to control gate line 3.
The source is connected to the source line 4. The drain of transistor Q2 is connected to bit line 1, and the gate is connected to reset signal ' to which reset signal R3T is transmitted.
It is connected to fIA5, and its source is grounded.

The source of the transistor Q3 is connected to the bit line l, and the gate is connected to the Y gate signal line 6 to which the Y gate signal YG is transmitted.
The drain is connected to the I/O line 7.

I/O line 7 is connected to current sense amplifier 8.

Next, the operation of the nonvolatile semiconductor memory device having such a configuration will be explained.

Operations include writing and reading. First, writing will be explained. Writing includes erasing and programming. In erasing, word line 2 and control gate line 3 are connected to a high voltage V□
The bit line 1 is grounded, and the source line 4 is grounded or floating. Then, electrons are injected into the floating gate of the memory transistor M1, and the threshold voltage of the memory transistor M1 increases. In programming, the bit line 1 and the word line 2 are boosted to a high voltage ■pp, the control gate line 3 is grounded, and the source line 4 is left floating. Then, electrons are extracted from the floating memory transistor M1, and the threshold value of the memory transistor M1 becomes lower.

Next, reading will be explained. For reading, the word line 2 and the Y gate signal line 6 are set to rHJ level, the source line 4 is grounded, and the control gate line 3 is set to a value midway between the threshold values when the memory transistor M1 is in the erased state and the programmed state. voltage is applied. In this state, I
Current sense amplifier 8 connected to /O line 7 is activated and reading is performed. Continuation is performed by detecting whether or not current flows through the I/O line 7 via the memory transistor Ml. Further, the transistor Q2 is a transistor for resetting the bit line 1 to the rLJ level, and the bit line 1 is reset in writing and reading, especially when necessary.

The configuration of a conventional sense amplifier is shown in FIG. 3, and the output waveform of the sense amplifier is shown in FIG. First, reset signal line 5
(Figure 2) becomes rHJ level, and bit line 1 becomes "L".
level will be reset. The word line 2 and the Y gate signal line 6 are set to the rHJ level, the source vA4 is grounded, and the control gate line 3 is applied with a voltage that is an intermediate value between the threshold values when the memory transistor M1 is in the erased state and the programmed state. be done. In this state, when the reset signal line 5 becomes "L" level, a charging current flows through the transistors T3 to T5 to charge the bit line 1. The output signal a of the current sense amplifier 8 becomes "L" level once due to the potential drop of the transistor T4 (see Fig. 4).
, when the bit line l is charged, the output signal a begins to be charged to the "H" level. memory transistor M
1 is in the programmed state (conducting state B), current continues to flow through the transistors T3 to T5, so the potential of the output signal a remains at the rLJ level due to the potential drop of the transistor T4 (as shown in Fig. 4). In the erase state (non-conducting state), the potential of the output signal a is charged to the "H" level by the transistor T4 (characteristic line S2 in FIG. 4).

Reading is performed by the above operations.

Here, when the cell current (the current flowing through the memory cell, that is, the current flowing through the bit line 1, transistor Ql, memory transistor M1, and source line 4 in FIG. 2) decreases, the memory transistor M1 is in the programmed state &i
(conducting state a), the transistor T
It is necessary to narrow down the size of 4 (increase the impedance). Otherwise, the current driving capability of the transistor T4 will be greater than the cell current, and the potential of the output signal a will be charged to the rHJ level, resulting in erroneous reading. If the size of the transistor T4 is reduced for the above reason, it will take time to charge the potential of the output signal a to the rHJ level when the memory transistor M1 is in the erased state (non-conductive state). Therefore, in the conventional current sense amplifier, when the cell current decreases, reading especially when the memory cell is in an erased state (non-conducting state) is delayed.

[Problem to be solved by the invention]

Since conventional nonvolatile semiconductor memory devices use current sense amplifiers as sense amplifiers, there has been a problem in that the read speed is delayed due to a decrease in cell current that accompanies higher integration.

The reason why cell current (current flowing through memory cells) decreases with higher integration is that cell size decreases with higher integration, effectively shortening the channel width of memory cells. This is due to higher on-resistance.

The present invention has been made in view of these points, and its purpose is to provide a nonvolatile semiconductor memory device that is capable of high-speed reading even with a minute cell current.

[Means to solve the problem]

In order to solve these problems, the present invention uses a flip-flop type sense amplifier as the sense amplifier.

[Effect]

In the nonvolatile semiconductor memory device according to the present invention, high-speed reading is possible.

〔Example〕

FIG. 1 is a circuit diagram showing the basic configuration regarding reading of an embodiment of a nonvolatile semiconductor memory device according to the present invention. In the same figure, the drain of transistor Q1 is connected to bit line 1.
The gate is connected to the word line 2, and the source is connected to the drain of the memory transistor M1.

A control gate of the memory transistor M1 is connected to a control gate line 3, and a source is connected to a source line 4. The drain of the transistor Q2 is connected to the bit line 1, the gate is connected to the reset signal line 5 through which the reset means R5T is transmitted, and the source is grounded. The source of the transistor Q3 is connected to the bit line 1, the gate is connected to the Y gate signal line 6 through which the Y gate signal YG is transmitted, and the drain is connected to the I/O line 7. Also, I/O line 7 is connected to transistor Q4. Commonly connected to the drains of Q5 and connected to the transistor Q6Q
7 gates in common. Transistor Q4
．． The gates of Q5 are connected in common and the gates of transistors Q6. Commonly connected to the drains of Q7. Transistor Q4. The source of Q6 is commonly connected to transistor Q.
8 (activation means connected to the third input), the gate of the transistor Q8 is connected to the sense amplifier activation signal line 9 to which the sense amplifier activation signal ■ is transmitted, and the source is connected to the power supply voltage. Connected to ycc. Transistor Q5. The sources of Q7 are commonly grounded. The drain of the transistor Q9 serving as a reset means is connected to the transistor Q6. It is commonly connected to the drains of Q7, its gate is connected to sense amplifier activation signal line 9, and its source is grounded. Sense amplifier 8 is a flip-flop type sense amplifier, and transistors Q4 to Q
It consists of 9.

Next, we will discuss the reason why high-speed reading is possible when using a flip-flop type sense amplifier.A normal sense amplifier (e.g., an inverter) cannot move beyond a set logic threshold (e.g., 2.5V). and read out. In other words, the input of the sense amplifier is from 0■ to 2.5■
Alternatively, when the voltage changes from 5V to 2.5V, the output data is inverted. Therefore, in this case, in order for the output data of the sense amplifier to be inverted, the input needs to change by 2.5 square meters or more. On the other hand, a flip-flop type sense amplifier (
Differential sense amplifier) has two inputs, the one with the higher voltage is set to 5V, and the input with the lower voltage is set to 0V.
It has the characteristic of making

If the difference between these two inputs is about several hundred mV, reading can be performed sufficiently. Therefore, there is no need for the input to change significantly as in a normal sense amplifier, and high-speed reading is possible.

Next, the operation will be explained.

Operations include writing and reading. Since writing is the same as in the prior art, its explanation will be omitted. In reading, first, the reset signal line 5 and the sense amplifier activation signal line 9 are set to rHJ level.

Further, the I/O line 7 is set to rL by a reset means (not shown).
Reset to J level. Thereby, bit, 1
1 and the nodes Nl and N2 of the sense amplifier 8 are reset to the rLJ level.Next, the reset signal line 5 is set to the rLJ level, and the bit line 1 becomes rLJ floating. Further, the above-mentioned reset means (not shown) becomes inactive, and the 1/O line 7 also enters the rLJ floating state. Word line 2 and Y gate signal line 6 are set to rHJ level, and source line 4 is connected to power supply voltage VCC. A voltage having an intermediate value between the threshold values when the memory transistor M1 is in the erased state and the programmed state is applied to the control gate line 3. In this state, when the memory transistor M1 is in the programmed state, the memory transistor M1 is turned on and the I/O is transmitted from the source line 4 through the bit 1IAl.
A current flows to charge line 7, and the potential of I/O line 7 increases. - On the other hand, when the memory transistor M1 is in the erased state, the memory transistor M1 remains off and the l/O
vA7 maintains the rLJ floating state. after that,
The sense amplifier activation signal r1000 is slowly brought to "L". Then, when the memory transistor M1 is in the programmed state, the potential of l/O17 is rising, so
The sense amplifier 8 sets the potential of the node N1 to the rHJ level, and the potential of the node N2 to the rLJ level.

Furthermore, when the memory transistor Ml is in the erased state, I/
O line 7 is in rLJ floating state and node N2
However, because the I/O line 7 is connected, there is a capacitance imbalance of (capacitance of node N1) > (capacitance of node N2), so the sense amplifier 8 The potential of node N2 is set to rLJ level, and the potential of node N2 is set to rHJ level.

Reading is performed through the above operations.

[Effects of the Invention] As explained above, in the present invention, by using a flip-flop type sense amplifier as the sense amplifier, reading can be performed even if the level difference between two input signals to the flip-flop type sense amplifier is small. This has the effect of enabling high-speed reading even with a minute cell current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a non-volatile semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing a conventional non-volatile semiconductor memory device, and FIG. 3 is a circuit diagram showing a conventional current sense amplifier. , FIG. 4 is a time chart showing the characteristics of the circuit shown in FIG. l...Bit line, 2...Word line, 3...Control gate line, 4...Source line, 5...Reset signal line, 6...Y'y'-) Line, 7... Tsukasa/O
line, 8... sense amplifier, 9... activation signal line, Q
1 to Q9...transistor, Ml...memory transistor, Nl, N2...node. Agent Masuo Oiwa Figure 3 Figure 4 ■

Claims (1)

[Claims] In a nonvolatile semiconductor memory device equipped with a memory cell array in which a plurality of memory transistors each having a floating gate are arranged in the row direction and the column direction,
A flip-flop type sense amplifier is provided on the O line, the I/O line is connected to the first input of this sense amplifier,
A reset means is connected to a second input of the sense amplifier for setting the second input to a ground level, and an activation means for activating the sense amplifier is connected to a third input of the sense amplifier. A nonvolatile semiconductor memory device, characterized in that: