KR100417413B1 - Digital linear apparatus - Google Patents

Abstract

The present invention relates to a digital linearizer, and to accurately detect and compensate an error value generated during QPSK modulation by a digital algorithm. To this end, the present invention includes a predistorter for adjusting the level of the digital input signal and distorting the level-adjusted digital input signal to have characteristics opposite to those of the nonlinear distortion characteristics; An error compensator for compensating the I / Q digital signal output from the predistorter by using an error correction signal in advance; A first digital / analog converter configured to receive an I-digital signal output from the predistorter and convert the I-digital signal into an I-analog signal; A second digital / analog converter for receiving a Q-digital signal output from the predistorter and converting the Q-digital signal into a Q-analog signal; A modulator for modulating an I / Q analog signal output from the first and second digital / analog converters at a frequency of a carrier wave; And an error correction signal detection unit that calculates an output signal of the modulator by a digital algorithm and outputs an error correction signal accordingly.

Description

DIGITAL LINEAR APPARATUS}

TECHNICAL FIELD The present invention relates to digital linearizers, and more particularly, to digital linearizers that compensate for analog modulation errors that are problematic in large power amplifiers.

In general, a large power amplifier is an important part of amplifying a high frequency signal and transferring it from the base station to the air.

The methods for improving the nonlinear characteristics of the power amplifier include a feed forward method, an envelope feedback method, and a predistortion method. Among them, the price is the lowest and wider than the performance. The predistortion method, which is a linearization method that also works in bandwidth, is widely used.

The predistortion method improves linearity by providing an input of a large power amplifier by distorting the input signal in advance as opposed to the nonlinear distortion characteristic of the power amplifier.

FIG. 1 is a block diagram illustrating a configuration of a digital linearizer using a predistortion method. As shown in FIG. 1, a nonlinear distortion characteristic of a large power amplifier 30 is adjusted by adjusting a level of a digital input signal and adjusting a level of the digital input signal. Predistorter (1) for distorting to have the opposite characteristics to; A first digital / analog converter (2) for receiving an I-digital signal (Id) output from the predistorter (1) and converting it into an I-analog signal; A second digital / analog converter (3) for receiving a Q-digital signal (Qd) output from the predistorter (1) and converting it into a Q-analog signal; A modulator (10) for modulating the I / Q analog signals output from the first and second digital / analog converters (2) and (3) at the carrier frequency; A second phase shifter (4) for shifting the phase of the local oscillation frequency signal by 180 degrees; An adder (5) for adding the output signal of the phase shifter (4) and the output signal of the modulator (10); A large power amplifier (HPA) for power amplifying the output signal of the adder (5).

The modulator 10 may include: a first multiplier 11 for multiplying a baseband I-signal output from the first digital / analog converter 2 with a local oscillation frequency signal output from the local oscillator LO; )Wow; A first phase shifter (12) for shifting the phase by a predetermined value to compensate for errors on the Q channel side having a 90 degree phase difference with respect to the local oscillation frequency signal; A second multiplier (14) for multiplying the output signal of the first phase shifter (12) by the baseband Q-signal output from the second digital / analog converter (3); The synthesizer 13 synthesizes the output signals of the first and second multipliers 11 and 14 and outputs a high frequency signal according to the present invention.

First, the predistorter 1 adjusts the level of the digital input signal and generates an I / Q digital signal that distorts the level-adjusted digital input signal to have characteristics opposite to the nonlinear distortion characteristics of the HPA. Output

Then, the first digital / analog converter 2 receives the I-digital signal output from the predistorter 1, converts it into an I-analog signal, and applies it to the modulator 10. The analog converter 3 also receives a Q-digital signal output from the predistorter 1, converts it into a Q-analog signal, and applies it to the modulator 10.

Accordingly, the modulator 10 receives the I / Q analog signals output from the first and second digital / analog converters 2 and 3, modulates them by QPSK, and outputs them as a high frequency signal of a carrier wave. This modulation operation will be described.

First, the first multiplier 11 multiplies the baseband I-signal output from the first digital-to-analog converter 2 with a local oscillation frequency signal output from the local oscillator LO to up-convert the frequency. The second multiplier 14 also multiplies the baseband Q-signal output from the second digital / analog converter 3 by a signal having a 90-degree phase difference with respect to the local oscillation frequency, thereby up-converting the frequency. Signals having a phase difference of 90 degrees with respect to the oscillation frequency are compensated for errors in the first phase shifter 12.

Thereafter, the synthesizer 13 synthesizes the output signals of the first multiplier 11 and the second multiplier 14 and applies a high frequency signal according to the adder 5.

Accordingly, the adder 5 adds and outputs the local oscillation frequency signal whose phase is inverted by 180 degrees in the second phase shifter 4 and the output signal of the modulator 10, and outputs a high power amplifier (HPA). Amplifies and outputs the output signal of the adder 5.

Here, the output signal of the modulator 10 is input to the large power amplifier (HPA) and amplified, so that an error component generated during modulation and a self distortion component of the large power amplifier (HPA) are added to the large power amplifier. There exists a problem that the output characteristic of (HPA) falls.

In order to solve this problem, conventionally, the modulation error is eliminated by using an analog method. In this case, the accuracy of the phase shifters must be prioritized, and the modulation value must be adjusted by artificially finding the modulation error value to precisely correct the modulation error. There is a problem that does not compensate.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital linearizer that accurately detects and compensates an error value generated during QPSK modulation by a digital algorithm.

1 is a block diagram showing a configuration for a digital linearizer using a conventional predistortion method.

Figure 2 is a block diagram showing the configuration of the digital linearizer of the present invention.

3 is a vector diagram for explaining detection of a phase correction signal in FIG. 2; FIG.

4 is a block diagram showing the configuration of an error compensator in FIG.

FIG. 5 is a block diagram showing the configuration of an error compensator in FIG. 2; FIG.

6 is a flowchart showing an operation of detecting first and second offset signals in FIG.

7 is a flowchart showing an operation of detecting first and second gain correction signals in FIG.

FIG. 8 is a flowchart showing an operation of detecting a phase correction signal in FIG. 2; FIG.

***** Description of the symbols for the main parts of the drawings *****

1: Predistorter 2,3: Digital / Analog Converter

10: modulator 11, 12: multiplier

13: Synthesis part 100: Error compensation part

200: error correction signal detection unit 201: op amp

202: diode detector 203: analog / digital converter

204: digital signal processing unit

According to an aspect of the present invention, there is provided a predistorter that adjusts a level of a digital input signal and distorts the leveled digital input signal to have characteristics opposite to those of the nonlinear distortion. An error compensator for compensating the I / Q digital signal output from the predistorter by using an error correction signal in advance; A first digital / analog converter configured to receive an I-digital signal output from the predistorter and convert the I-digital signal into an I-analog signal; A second digital / analog converter for receiving a Q-digital signal output from the predistorter and converting the Q-digital signal into a Q-analog signal; A modulator for modulating an I / Q analog signal output from the first and second digital / analog converters at a frequency of a carrier wave; And an error correction signal detection unit for outputting the error correction signal according to a predetermined operation of the output signal of the modulator by a digital algorithm.

Hereinafter, the operation and effects of the digital linearizer according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram showing the configuration of an embodiment of the present invention digital linearizer, in which the level of the digital input signal is adjusted and the level-adjusted digital input signal is opposed to the nonlinear distortion characteristics of the high power amplifier (HPA). A predistorter 1 for distorting to have a characteristic of; An error compensator (100) for receiving an I / Q digital signal (Id, Qd) output from the predistorter (1) and compensating for the error correction signal in advance and outputting the same; A first digital / analog converter (2) for receiving an I-digital signal (Id) output from the predistorter (1) and converting it into an I-analog signal; A second digital / analog converter (3) for receiving a Q-digital signal (Qd) output from the predistorter (1) and converting it into a Q-analog signal; A modulator (10) for modulating the I / Q analog signals output from the first and second digital / analog converters (2) and (3) at the carrier frequency; An error correction signal detection unit 200 which receives an output signal of the modulator 10 and outputs an error correction signal according to a predetermined operation; A high power amplifier (HPA) for amplifying the output signal of the modulator 10 is configured.

The modulator 10 includes: a first multiplier 11 for multiplying a baseband I-signal output from the first digital-to-analog converter 2 with a local oscillation frequency signal output from the local oscillator LO; A second multiplier (12) for multiplying a 90 degree phase-converted local oscillation frequency signal output from the local oscillator (LO) and a baseband Q-signal output from the second digital / analog converter (3); The synthesizer 13 synthesizes an output signal of the first and second multipliers 1 and 2 and outputs a high frequency signal accordingly.

The error correction signal detecting unit 200 includes an op amp 201 for amplifying the output signal of the modulator 10 to a predetermined level; A diode detector 202 for outputting the output signal of the op amp 201 as a DC average value; An analog / digital converter (203) for converting the DC average value output from the diode detector (202) into a digital signal; The digital signal processor 204 receives an output signal of the analog / digital converter 203, measures an error value, and outputs an error correction signal for correcting the error value.

As shown in Fig. 4, the error compensator 100 includes a first op amp 101 for gain control of the predistorted I-digital signal Id by the first gain correction signal?. ; A second op amp 102 for gain control of the predistorted Q-digital signal Qd by a second gain correction signal β; A third op amp 103 for gain control of the output signal of the second op amp 102 by a first phase correction signal sin? A fourth op amp 105 for gain controlling the output signal of the second op amp 102 by a second phase correction signal cos phi; A first adder (104) for adding the output signals of the first and third operational amplifiers (103); A second adder (106) for adding an output signal of the first adder (101) and a first offset signal (C1); The third adder 107 adds the output signal of the fourth op amp 105 and the second offset signal C2.

FIG. 5 is a block diagram showing another embodiment of the error compensator 100, and includes a first multiplier 108 for multiplying the predistorted I-digital signal Id and the first gain compensation signal α. A second multiplier 109 for multiplying the predistorted Q-digital signal Qd by a signal? X sin? Multiplied by the second gain correction signal? And the first phase correction signal sin? A third multiplier (110) for multiplying the predistorted Q-digital signal (Qd) by a signal (β x cosφ) of the second gain correction signal (beta) and the second phase correction signal (cosφ); A first adder (111) for adding an output signal of the first and second multipliers (108, 109) and a first offset signal (C1) to compensate for an error on an I-channel; Comprising a second adder 112 for adding the output signal and the second offset signal (C2) of the third multiplier 110 to compensate for the error for the Q-channel and outputs, the operation of the present invention configured as described above do.

First, the predistorter 1 adjusts the level of the digital input signal and distorts the level-adjusted digital input signal to have characteristics opposite to the nonlinear distortion characteristics of the high power amplifier (HPA). The signal Id Qd is applied to the first and second digital / analog converters 2 and 3 by correcting the error in the error compensator 100, and the operation of the error compensator 100 will be described later. do.

Then, the first digital / analog converter 2 receives the I-digital signal Id, converts it into an I-analog signal, and applies it to the modulator 10, and the second digital / analog converter 3 In addition, the Q-digital signal Qd is received and converted into a Q-analog signal and applied to the modulator 10.

Accordingly, the modulator 10 receives the I / Q analog signals output from the first and second digital / analog converters 2 and 3, modulates them by QPSK, and outputs them as a high frequency signal of a carrier wave. .

That is, the first multiplier 11 of the modulator 10 multiplies the baseband I-signal output from the first digital / analog converter with the local oscillation frequency signal output from the local oscillator LO. After the frequency up-conversion, it is applied to the synthesizer 13, and the second multiplier 12 of the modulator 10 also outputs the baseband Q-signal output from the second digital / analog converter 3 and After multiplying a signal having a phase difference of 90 degrees with respect to the local oscillation frequency and up-converting the frequency, it is applied to the synthesizer 13 of the modulator 10, whereby the synthesizer 13 of the modulator 10 The output signals of the first multiplier 11 and the second multiplier 12 are synthesized, and a high frequency signal corresponding thereto is applied to the large power amplifier HPA.

At this time, the error correction signal detection unit 200 receives the output signal of the modulator 10 and performs a predetermined calculation to apply the error correction signal according to the error compensation unit 100.

That is, the op amp 201 amplifies the output signal of the modulator 10 to a predetermined level, and the diode detector 202 converts the output signal of the op amp 201 to a DC average value as an analog / digital converter 203. To apply.

Accordingly, the analog / digital converter 203 converts the DC average value output from the diode detector 202 into a digital signal and applies the digital signal to the digital signal processing unit 204, whereby the digital signal processing unit 204 After receiving the output signal of the analog / digital converter 203 and measuring an error value, an error correction signal for correcting the error value is applied to the error compensator 100.

In this case, the error correction signal includes first and second gain correction signals α and β for correcting an error of the I / Q channel signal, and first and second DC offsets for correcting the I / Q channel signal. And a second offset signal C1, C2 and a phase correction signal? For correcting the phase error of the I / Q channel signal.

The first offset signal C1 is as shown in the flowchart of FIG. After fixing the offset signal Cq of the Q channel, the output signal of the diode detector 202 is detected while varying the offset signal Ci of the I channel, and the I channel offset signal Ci at the time when the output signal becomes the minimum. Determine with).

As shown in the flowchart of FIG. 6, the second offset signal C2 fixes the output signal of the diode detector 202 while fixing the offset signal Ci of the I channel and then varying the offset signal Cq of the Q channel. It detects and determines by the Q channel offset signal Cq at the time when the output signal becomes minimum.

The first and second gain correction signals? And? Are detected as shown in the flowchart of FIG. 7 while the I channel signal is fixed at a predetermined value 'A' and the Q channel signal is fixed at '0'. After detecting the second output signal of the diode detector 202 detected with the first output signal and the Q channel signal of the detector 202 fixed to a predetermined value 'A' and the I channel signal '0', The value obtained by dividing the first output signal by the second output signal is determined to be approximately '1'. When the value obtained by dividing the first output signal by the second output signal is greater than '1', the second gain information signal ( In a state in which β) is fixed to '1', the first gain information signal α is determined to be changed to a value smaller than '1', and a value obtained by dividing the first output signal by the second output signal is smaller than '1'. In this case, while the first gain information signal α is fixed to '1', the second gain information signal β is determined to be variable to a value smaller than '1'.

The phase correction signal φ is explained with reference to the vector diagram of FIG. 3. As shown in the flowchart of FIG. 8, the I channel signal is fixed to the predetermined value vector 'A' and the Q channel signal is fixed to the predetermined value vector 'A'. Diode detector 202 detected in a state where the first output signal of the diode detector 202 detected in the above state and the I channel signal are fixed to the predetermined value vector '-A' and the Q channel signal to the predetermined value vector 'A'. After detecting the second output signal of < RTI ID = 0.0 >),< / RTI > ) Is determined by substituting the following equation.

[Equation]

At this time, the size ratio ( ) Is detected by dividing the first output signal by the second output signal when the angle of the predetermined value vector 'A' is smaller than 90 degrees, and the second output signal when the angle of the predetermined value vector 'A' is larger than 90 degrees. Is detected by dividing by the first output signal.

Here, the error compensator 100 receives the error correction signal and compensates for the error accordingly and outputs the error correction signal, which will be described in detail with reference to FIG. 4.

First, in order to compensate for the predistorted I-digital signal, the first op amp 101 is gain-controlled and output by the first gain correction signal α, and the second op amp 102 is predistorted. In order to compensate for the Q-digital signal Qd, the gain is controlled and output by the second gain correction signal β.

In order to correct the phase of the I / Q channel, the third operational amplifier 103 outputs the output signal of the second operational amplifier 102 by gain control using the first phase correction signal sinφ. The fourth op amp 105 gain-controls the output signal of the second op amp 102 by a second phase correction signal cosφ.

Thereafter, the first adder 104 adds and outputs output signals of the first op amp 101 and the third op amp 103, and the second adder 106 outputs the first adder 104. The signal and the first offset signal C1 are added to compensate for the error of the I channel, and the third adder 107 outputs the output signal of the fourth op amp 105 and the second offset signal C2. Add and compensate for the error for the Q channel and output.

When the compensation circuit of FIG. 4 is derived by the equation, it is as follows.

[Equation]

5 is a schematic view showing another embodiment of the error compensator 100. The first multiplier 108 multiplies the predistorted I-digital signal Id by the first gain correction signal α. The second multiplier 109 multiplies the predistorted Q-digital signal Qd by the product of the second gain correction signal β and the first phase correction signal sinφ, and outputs the multiplied signal. The sum signal of the two gain correction signals β and the first phase correction signal sin Φ is processed and output by the digital signal processing unit 204.

The third multiplier 110 multiplies the predistorted Q-digital signal Qd by a multiplied signal of the second gain correction signal β and the second phase correction signal cos Φ and outputs the first adder. 111 adds the output signals of the first and second multipliers 108 and 109 and the first offset signal C1 to compensate for the error for the I-channel, and outputs the second adder 112. The output signal of the third multiplier 110 and the second offset signal C2 are added to compensate for the error of the Q-channel and output.

Specific embodiments or examples made in the detailed description of the invention are intended to clarify the technical details of the present invention to the extent that they should not be construed as limited to these specific embodiments and should not be construed as consultations. Various changes can be made within the scope.

As described in detail above, the present invention has an effect of accurately detecting an error value generated during QPSK modulation by using a digital algorithm, and interworking with an arbitrary QPSK modulator by providing a compensation circuit in front of the QPSK modulator. In addition to this, there is an effect of easily detecting the error of the QPSK modulator.

Claims (12)

A predistorter that adjusts the level of the digital input signal and distorts the leveled digital input signal to have characteristics opposite to the nonlinear distortion characteristics; An error compensator for compensating the I / Q digital signal output from the predistorter by using an error correction signal in advance; A first digital / analog converter configured to receive an I-digital signal output from the predistorter and convert the I-digital signal into an I-analog signal; A second digital / analog converter for receiving a Q-digital signal output from the predistorter and converting the Q-digital signal into a Q-analog signal; A modulator for modulating an I / Q analog signal output from the first and second digital / analog converters at a frequency of a carrier wave; And an error correction signal detection unit configured to perform a predetermined operation on the output signal of the modulator by a digital algorithm and output an error correction signal according to the digital signal. 2. The apparatus of claim 1, wherein the error correction signal detection unit comprises: an operational amplifier for amplifying the output signal of the modulator to a predetermined level; A diode detector for outputting the output signal of the op amp as a DC average value; An analog / digital converter for converting the DC average value output from the diode detector into a digital signal; And a digital signal processor configured to receive an output signal of the analog / digital converter, measure an error value, and output an error correction signal for correcting the error value. The error correction signal according to claim 1 or 2, wherein the error correction signal comprises: first and second gain correction signals for correcting an error of the I / Q channel signal and a first offset for correcting a DC offset of the I / Q channel signal. And a second offset signal and a phase correction signal for correcting a phase error of the I / Q channel signal. 4. The I-channel offset of claim 3, wherein the first offset signal is configured to detect an output signal of the diode detector while fixing the offset signal of the Q-channel, and then vary the offset signal of the I-channel and detect the output signal of the diode detector. 5. Digital linearizer, characterized in that determined by the signal. 4. The second offset signal according to claim 3, wherein the second offset signal is fixed at the I-channel offset signal, and then the Q-channel offset at the time when the output signal of the diode detector is detected while the offset signal of the Q-channel is varied and the output signal is minimized. Digital linearizer, characterized in that determined by the signal. The first and second gain correction signals of claim 2, wherein the first and second gain correction signals are detected while the I channel signal is fixed at a predetermined value 'A' and the Q channel signal is set to '0'. After detecting the second output signal of the diode detector detected while the signal is fixed to the predetermined value 'A' and the I channel signal to '0', the value obtained by dividing the first output signal by the second output signal is approximately ' Digital linearizer characterized in that it is determined to vary by 1 '. The method of claim 4, wherein when the value obtained by dividing the first output signal by the second output signal is greater than '1', the first gain information is smaller than '1' while the second gain information signal is fixed to '1'. Is determined by varying the value, and when the first output signal is divided by the second output signal smaller than '1', the second gain information is set to '1' while the second gain information is fixed to '1'. Digital linearizer characterized in that the variable to determine a small value. 3. The phase correction signal of claim 2, wherein the phase correction signal comprises: a first output signal of the diode detector detected in a state where the I channel signal is fixed to the predetermined value vector 'A', and the Q channel signal is fixed to the predetermined value vector 'A'; After detecting the second output signal of the diode detector detected while the signal is fixed to the predetermined value vector '-A' and the Q channel signal to the predetermined value vector 'A', the magnitude of the first and second output signals is detected. ratio( Digital linearizer, characterized in that determined by a predetermined operation. The method of claim 8, wherein the size ratio ( ) Is detected by dividing the first output signal by the second output signal when the angle of the predetermined value vector 'A' is smaller than 90 degrees, and the second output signal when the angle of the predetermined value vector 'A' is larger than 90 degrees. Digital linearizer for detecting by dividing by the first output signal. The digital linearizer of claim 8, wherein the phase correction signal is implemented by the following equation. [Equation] 2. The apparatus of claim 1, wherein the error compensator comprises: a first op amp for gain control of the predistorted I-digital signal by a first gain compensation signal; A second op amp for gain controlling the predistorted Q-digital signal by a second gain correction signal; A third op amp for gain controlling the output signal of the second op amp by a first phase correction signal; A fourth op amp for gain controlling the output signal of the second op amp by a second phase correction signal; A first adder for adding output signals of the first and third operational amplifiers; A second adder for adding an output signal of the first adder and a first offset signal; And a third adder for adding the output signal and the second offset signal of the fourth op amp. 2. The apparatus of claim 1, further comprising: a first multiplier that multiplies the predistorted I-digital signal and the first gain correction signal, and a signal obtained by multiplying the predistorted Q-digital signal by the second gain correction signal and the first phase correction signal; A second multiplier for multiplying; A third multiplier for multiplying the predistorted Q-digital signal with a signal multiplied by a second gain correction signal and a second phase correction signal; A first adder configured to add an output signal of the first and second multipliers and a first offset signal to compensate for an error on an I-channel; And a second adder configured to add an output signal of the third multiplier and a second offset signal to compensate for an error of a Q-channel, and output the compensated error.